2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
26 void aiger_encode(std::ostream
&f
, int x
)
31 f
.put((x
& 0x7f) | 0x80);
44 dict
<SigBit
, bool> init_map
;
45 pool
<SigBit
> input_bits
, output_bits
;
46 dict
<SigBit
, SigBit
> not_map
, ff_map
, alias_map
;
47 dict
<SigBit
, pair
<SigBit
, SigBit
>> and_map
;
48 vector
<pair
<SigBit
, SigBit
>> asserts
, assumes
;
49 vector
<pair
<SigBit
, SigBit
>> liveness
, fairness
;
50 pool
<SigBit
> initstate_bits
;
52 vector
<pair
<int, int>> aig_gates
;
53 vector
<int> aig_latchin
, aig_latchinit
, aig_outputs
;
54 int aig_m
= 0, aig_i
= 0, aig_l
= 0, aig_o
= 0, aig_a
= 0;
55 int aig_b
= 0, aig_c
= 0, aig_j
= 0, aig_f
= 0;
57 dict
<SigBit
, int> aig_map
;
58 dict
<SigBit
, int> ordered_outputs
;
59 dict
<SigBit
, int> ordered_latches
;
61 dict
<SigBit
, int> init_inputs
;
64 int mkgate(int a0
, int a1
)
67 aig_gates
.push_back(a0
> a1
? make_pair(a0
, a1
) : make_pair(a1
, a0
));
71 int bit2aig(SigBit bit
)
73 auto it
= aig_map
.find(bit
);
74 if (it
!= aig_map
.end()) {
75 log_assert(it
->second
>= 0);
79 // NB: Cannot use iterator returned from aig_map.insert()
80 // since this function is called recursively
83 if (not_map
.count(bit
)) {
84 a
= bit2aig(not_map
.at(bit
)) ^ 1;
86 if (and_map
.count(bit
)) {
87 auto args
= and_map
.at(bit
);
88 int a0
= bit2aig(args
.first
);
89 int a1
= bit2aig(args
.second
);
92 if (alias_map
.count(bit
)) {
93 a
= bit2aig(alias_map
.at(bit
));
95 if (initstate_bits
.count(bit
)) {
99 if (bit
== State::Sx
|| bit
== State::Sz
)
100 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
107 AigerWriter(Module
*module
, bool zinit_mode
, bool imode
, bool omode
, bool bmode
, bool lmode
) : module(module
), zinit_mode(zinit_mode
), sigmap(module
)
109 pool
<SigBit
> undriven_bits
;
110 pool
<SigBit
> unused_bits
;
112 // promote public wires
113 for (auto wire
: module
->wires())
114 if (wire
->name
[0] == '\\')
117 // promote input wires
118 for (auto wire
: module
->wires())
119 if (wire
->port_input
)
122 // promote output wires
123 for (auto wire
: module
->wires())
124 if (wire
->port_output
)
127 for (auto wire
: module
->wires())
129 if (wire
->attributes
.count(ID::init
)) {
130 SigSpec initsig
= sigmap(wire
);
131 Const initval
= wire
->attributes
.at(ID::init
);
132 for (int i
= 0; i
< GetSize(wire
) && i
< GetSize(initval
); i
++)
133 if (initval
[i
] == State::S0
|| initval
[i
] == State::S1
)
134 init_map
[initsig
[i
]] = initval
[i
] == State::S1
;
137 for (int i
= 0; i
< GetSize(wire
); i
++)
139 SigBit
wirebit(wire
, i
);
140 SigBit bit
= sigmap(wirebit
);
142 if (bit
.wire
== nullptr) {
143 if (wire
->port_output
) {
144 aig_map
[wirebit
] = (bit
== State::S1
) ? 1 : 0;
145 output_bits
.insert(wirebit
);
150 undriven_bits
.insert(bit
);
151 unused_bits
.insert(bit
);
153 if (wire
->port_input
)
154 input_bits
.insert(bit
);
156 if (wire
->port_output
) {
158 alias_map
[wirebit
] = bit
;
159 output_bits
.insert(wirebit
);
164 for (auto bit
: input_bits
)
165 undriven_bits
.erase(bit
);
167 for (auto bit
: output_bits
)
168 unused_bits
.erase(bit
);
170 for (auto cell
: module
->cells())
172 if (cell
->type
== ID($_NOT_
))
174 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
175 SigBit Y
= sigmap(cell
->getPort(ID::Y
).as_bit());
176 unused_bits
.erase(A
);
177 undriven_bits
.erase(Y
);
182 if (cell
->type
.in(ID($_FF_
), ID($_DFF_N_
), ID($_DFF_P_
)))
184 SigBit D
= sigmap(cell
->getPort(ID::D
).as_bit());
185 SigBit Q
= sigmap(cell
->getPort(ID::Q
).as_bit());
186 unused_bits
.erase(D
);
187 undriven_bits
.erase(Q
);
192 if (cell
->type
== ID($_AND_
))
194 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
195 SigBit B
= sigmap(cell
->getPort(ID::B
).as_bit());
196 SigBit Y
= sigmap(cell
->getPort(ID::Y
).as_bit());
197 unused_bits
.erase(A
);
198 unused_bits
.erase(B
);
199 undriven_bits
.erase(Y
);
200 and_map
[Y
] = make_pair(A
, B
);
204 if (cell
->type
== ID($initstate
))
206 SigBit Y
= sigmap(cell
->getPort(ID::Y
).as_bit());
207 undriven_bits
.erase(Y
);
208 initstate_bits
.insert(Y
);
212 if (cell
->type
== ID($
assert))
214 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
215 SigBit EN
= sigmap(cell
->getPort(ID::EN
).as_bit());
216 unused_bits
.erase(A
);
217 unused_bits
.erase(EN
);
218 asserts
.push_back(make_pair(A
, EN
));
222 if (cell
->type
== ID($assume
))
224 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
225 SigBit EN
= sigmap(cell
->getPort(ID::EN
).as_bit());
226 unused_bits
.erase(A
);
227 unused_bits
.erase(EN
);
228 assumes
.push_back(make_pair(A
, EN
));
232 if (cell
->type
== ID($live
))
234 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
235 SigBit EN
= sigmap(cell
->getPort(ID::EN
).as_bit());
236 unused_bits
.erase(A
);
237 unused_bits
.erase(EN
);
238 liveness
.push_back(make_pair(A
, EN
));
242 if (cell
->type
== ID($fair
))
244 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
245 SigBit EN
= sigmap(cell
->getPort(ID::EN
).as_bit());
246 unused_bits
.erase(A
);
247 unused_bits
.erase(EN
);
248 fairness
.push_back(make_pair(A
, EN
));
252 if (cell
->type
== ID($anyconst
))
254 for (auto bit
: sigmap(cell
->getPort(ID::Y
))) {
255 undriven_bits
.erase(bit
);
261 if (cell
->type
== ID($anyseq
))
263 for (auto bit
: sigmap(cell
->getPort(ID::Y
))) {
264 undriven_bits
.erase(bit
);
265 input_bits
.insert(bit
);
270 log_error("Unsupported cell type: %s (%s)\n", log_id(cell
->type
), log_id(cell
));
273 for (auto bit
: unused_bits
)
274 undriven_bits
.erase(bit
);
276 if (!undriven_bits
.empty()) {
277 undriven_bits
.sort();
278 for (auto bit
: undriven_bits
) {
279 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module
), log_signal(bit
));
280 input_bits
.insert(bit
);
282 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits
), log_id(module
));
292 aig_map
[State::S0
] = 0;
293 aig_map
[State::S1
] = 1;
295 for (auto bit
: input_bits
) {
297 aig_map
[bit
] = 2*aig_m
;
300 if (imode
&& input_bits
.empty()) {
306 for (auto it
: ff_map
) {
307 if (init_map
.count(it
.first
))
310 init_inputs
[it
.first
] = 2*aig_m
;
314 int fair_live_inputs_cnt
= GetSize(liveness
);
315 int fair_live_inputs_m
= aig_m
;
317 aig_m
+= fair_live_inputs_cnt
;
318 aig_i
+= fair_live_inputs_cnt
;
320 for (auto it
: ff_map
) {
322 aig_map
[it
.first
] = 2*aig_m
;
323 ordered_latches
[it
.first
] = aig_l
-1;
324 if (init_map
.count(it
.first
) == 0)
325 aig_latchinit
.push_back(2);
327 aig_latchinit
.push_back(init_map
.at(it
.first
) ? 1 : 0);
330 if (!initstate_bits
.empty() || !init_inputs
.empty()) {
332 initstate_ff
= 2*aig_m
+1;
333 aig_latchinit
.push_back(0);
336 int fair_live_latches_cnt
= GetSize(fairness
) + 2*GetSize(liveness
);
337 int fair_live_latches_m
= aig_m
;
338 int fair_live_latches_l
= aig_l
;
340 aig_m
+= fair_live_latches_cnt
;
341 aig_l
+= fair_live_latches_cnt
;
343 for (int i
= 0; i
< fair_live_latches_cnt
; i
++)
344 aig_latchinit
.push_back(0);
348 for (auto it
: ff_map
)
350 int l
= ordered_latches
[it
.first
];
352 if (aig_latchinit
.at(l
) == 1)
353 aig_map
[it
.first
] ^= 1;
355 if (aig_latchinit
.at(l
) == 2)
357 int gated_ffout
= mkgate(aig_map
[it
.first
], initstate_ff
^1);
358 int gated_initin
= mkgate(init_inputs
[it
.first
], initstate_ff
);
359 aig_map
[it
.first
] = mkgate(gated_ffout
^1, gated_initin
^1)^1;
364 for (auto it
: ff_map
) {
365 int a
= bit2aig(it
.second
);
366 int l
= ordered_latches
[it
.first
];
367 if (zinit_mode
&& aig_latchinit
.at(l
) == 1)
368 aig_latchin
.push_back(a
^ 1);
370 aig_latchin
.push_back(a
);
373 if (lmode
&& aig_l
== 0) {
375 aig_latchinit
.push_back(0);
376 aig_latchin
.push_back(0);
379 if (!initstate_bits
.empty() || !init_inputs
.empty())
380 aig_latchin
.push_back(1);
382 for (auto bit
: output_bits
) {
384 ordered_outputs
[bit
] = aig_o
-1;
385 aig_outputs
.push_back(bit2aig(bit
));
388 if (omode
&& output_bits
.empty()) {
390 aig_outputs
.push_back(0);
393 for (auto it
: asserts
) {
395 int bit_a
= bit2aig(it
.first
);
396 int bit_en
= bit2aig(it
.second
);
397 aig_outputs
.push_back(mkgate(bit_a
^1, bit_en
));
400 if (bmode
&& asserts
.empty()) {
402 aig_outputs
.push_back(0);
405 for (auto it
: assumes
) {
407 int bit_a
= bit2aig(it
.first
);
408 int bit_en
= bit2aig(it
.second
);
409 aig_outputs
.push_back(mkgate(bit_a
^1, bit_en
)^1);
412 for (auto it
: liveness
)
414 int input_m
= ++fair_live_inputs_m
;
415 int latch_m1
= ++fair_live_latches_m
;
416 int latch_m2
= ++fair_live_latches_m
;
418 log_assert(GetSize(aig_latchin
) == fair_live_latches_l
);
419 fair_live_latches_l
+= 2;
421 int bit_a
= bit2aig(it
.first
);
422 int bit_en
= bit2aig(it
.second
);
423 int bit_s
= 2*input_m
;
424 int bit_q1
= 2*latch_m1
;
425 int bit_q2
= 2*latch_m2
;
427 int bit_d1
= mkgate(mkgate(bit_s
, bit_en
)^1, bit_q1
^1)^1;
428 int bit_d2
= mkgate(mkgate(bit_d1
, bit_a
)^1, bit_q2
^1)^1;
431 aig_latchin
.push_back(bit_d1
);
432 aig_latchin
.push_back(bit_d2
);
433 aig_outputs
.push_back(mkgate(bit_q1
, bit_q2
^1));
436 for (auto it
: fairness
)
438 int latch_m
= ++fair_live_latches_m
;
440 log_assert(GetSize(aig_latchin
) == fair_live_latches_l
);
441 fair_live_latches_l
+= 1;
443 int bit_a
= bit2aig(it
.first
);
444 int bit_en
= bit2aig(it
.second
);
445 int bit_q
= 2*latch_m
;
448 aig_latchin
.push_back(mkgate(mkgate(bit_q
^1, bit_en
^1)^1, bit_a
^1));
449 aig_outputs
.push_back(bit_q
^1);
453 void write_aiger(std::ostream
&f
, bool ascii_mode
, bool miter_mode
, bool symbols_mode
)
455 int aig_obc
= aig_o
+ aig_b
+ aig_c
;
456 int aig_obcj
= aig_obc
+ aig_j
;
457 int aig_obcjf
= aig_obcj
+ aig_f
;
459 log_assert(aig_m
== aig_i
+ aig_l
+ aig_a
);
460 log_assert(aig_l
== GetSize(aig_latchin
));
461 log_assert(aig_l
== GetSize(aig_latchinit
));
462 log_assert(aig_obcjf
== GetSize(aig_outputs
));
465 if (aig_b
|| aig_c
|| aig_j
|| aig_f
)
466 log_error("Running AIGER back-end in -miter mode, but design contains $assert, $assume, $live and/or $fair cells!\n");
467 f
<< stringf("%s %d %d %d 0 %d %d\n", ascii_mode
? "aag" : "aig", aig_m
, aig_i
, aig_l
, aig_a
, aig_o
);
469 f
<< stringf("%s %d %d %d %d %d", ascii_mode
? "aag" : "aig", aig_m
, aig_i
, aig_l
, aig_o
, aig_a
);
470 if (aig_b
|| aig_c
|| aig_j
|| aig_f
)
471 f
<< stringf(" %d %d %d %d", aig_b
, aig_c
, aig_j
, aig_f
);
477 for (int i
= 0; i
< aig_i
; i
++)
478 f
<< stringf("%d\n", 2*i
+2);
480 for (int i
= 0; i
< aig_l
; i
++) {
481 if (zinit_mode
|| aig_latchinit
.at(i
) == 0)
482 f
<< stringf("%d %d\n", 2*(aig_i
+i
)+2, aig_latchin
.at(i
));
483 else if (aig_latchinit
.at(i
) == 1)
484 f
<< stringf("%d %d 1\n", 2*(aig_i
+i
)+2, aig_latchin
.at(i
));
485 else if (aig_latchinit
.at(i
) == 2)
486 f
<< stringf("%d %d %d\n", 2*(aig_i
+i
)+2, aig_latchin
.at(i
), 2*(aig_i
+i
)+2);
489 for (int i
= 0; i
< aig_obc
; i
++)
490 f
<< stringf("%d\n", aig_outputs
.at(i
));
492 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
495 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
496 f
<< stringf("%d\n", aig_outputs
.at(i
));
498 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
499 f
<< stringf("%d\n", aig_outputs
.at(i
));
501 for (int i
= 0; i
< aig_a
; i
++)
502 f
<< stringf("%d %d %d\n", 2*(aig_i
+aig_l
+i
)+2, aig_gates
.at(i
).first
, aig_gates
.at(i
).second
);
506 for (int i
= 0; i
< aig_l
; i
++) {
507 if (zinit_mode
|| aig_latchinit
.at(i
) == 0)
508 f
<< stringf("%d\n", aig_latchin
.at(i
));
509 else if (aig_latchinit
.at(i
) == 1)
510 f
<< stringf("%d 1\n", aig_latchin
.at(i
));
511 else if (aig_latchinit
.at(i
) == 2)
512 f
<< stringf("%d %d\n", aig_latchin
.at(i
), 2*(aig_i
+i
)+2);
515 for (int i
= 0; i
< aig_obc
; i
++)
516 f
<< stringf("%d\n", aig_outputs
.at(i
));
518 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
521 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
522 f
<< stringf("%d\n", aig_outputs
.at(i
));
524 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
525 f
<< stringf("%d\n", aig_outputs
.at(i
));
527 for (int i
= 0; i
< aig_a
; i
++) {
528 int lhs
= 2*(aig_i
+aig_l
+i
)+2;
529 int rhs0
= aig_gates
.at(i
).first
;
530 int rhs1
= aig_gates
.at(i
).second
;
531 int delta0
= lhs
- rhs0
;
532 int delta1
= rhs0
- rhs1
;
533 aiger_encode(f
, delta0
);
534 aiger_encode(f
, delta1
);
540 dict
<string
, vector
<string
>> symbols
;
542 for (auto wire
: module
->wires())
544 if (wire
->name
[0] == '$')
547 SigSpec sig
= sigmap(wire
);
549 for (int i
= 0; i
< GetSize(wire
); i
++)
551 if (sig
[i
].wire
== nullptr) {
552 if (wire
->port_output
)
553 sig
[i
] = SigBit(wire
, i
);
558 if (wire
->port_input
) {
559 int a
= aig_map
.at(sig
[i
]);
560 log_assert((a
& 1) == 0);
561 if (GetSize(wire
) != 1)
562 symbols
[stringf("i%d", (a
>> 1)-1)].push_back(stringf("%s[%d]", log_id(wire
), i
));
564 symbols
[stringf("i%d", (a
>> 1)-1)].push_back(stringf("%s", log_id(wire
)));
567 if (wire
->port_output
) {
568 int o
= ordered_outputs
.at(SigSpec(wire
, i
));
569 if (GetSize(wire
) != 1)
570 symbols
[stringf("%c%d", miter_mode
? 'b' : 'o', o
)].push_back(stringf("%s[%d]", log_id(wire
), i
));
572 symbols
[stringf("%c%d", miter_mode
? 'b' : 'o', o
)].push_back(stringf("%s", log_id(wire
)));
575 if (init_inputs
.count(sig
[i
])) {
576 int a
= init_inputs
.at(sig
[i
]);
577 log_assert((a
& 1) == 0);
578 if (GetSize(wire
) != 1)
579 symbols
[stringf("i%d", (a
>> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire
), i
));
581 symbols
[stringf("i%d", (a
>> 1)-1)].push_back(stringf("init:%s", log_id(wire
)));
584 if (ordered_latches
.count(sig
[i
])) {
585 int l
= ordered_latches
.at(sig
[i
]);
586 const char *p
= (zinit_mode
&& (aig_latchinit
.at(l
) == 1)) ? "!" : "";
587 if (GetSize(wire
) != 1)
588 symbols
[stringf("l%d", l
)].push_back(stringf("%s%s[%d]", p
, log_id(wire
), i
));
590 symbols
[stringf("l%d", l
)].push_back(stringf("%s%s", p
, log_id(wire
)));
597 for (auto &sym
: symbols
) {
599 std::sort(sym
.second
.begin(), sym
.second
.end());
600 for (auto &s
: sym
.second
)
606 f
<< stringf("c\nGenerated by %s\n", yosys_version_str
);
609 void write_map(std::ostream
&f
, bool verbose_map
)
611 dict
<int, string
> input_lines
;
612 dict
<int, string
> init_lines
;
613 dict
<int, string
> output_lines
;
614 dict
<int, string
> latch_lines
;
615 dict
<int, string
> wire_lines
;
617 for (auto wire
: module
->wires())
619 if (!verbose_map
&& wire
->name
[0] == '$')
622 SigSpec sig
= sigmap(wire
);
624 for (int i
= 0; i
< GetSize(wire
); i
++)
626 if (aig_map
.count(sig
[i
]) == 0 || sig
[i
].wire
== nullptr)
629 int a
= aig_map
.at(sig
[i
]);
632 wire_lines
[a
] += stringf("wire %d %d %s\n", a
, wire
->start_offset
+i
, log_id(wire
));
634 if (wire
->port_input
) {
635 log_assert((a
& 1) == 0);
636 input_lines
[a
] += stringf("input %d %d %s\n", (a
>> 1)-1, wire
->start_offset
+i
, log_id(wire
));
639 if (wire
->port_output
) {
640 int o
= ordered_outputs
.at(sig
[i
]);
641 output_lines
[o
] += stringf("output %d %d %s\n", o
, wire
->start_offset
+i
, log_id(wire
));
644 if (init_inputs
.count(sig
[i
])) {
645 int a
= init_inputs
.at(sig
[i
]);
646 log_assert((a
& 1) == 0);
647 init_lines
[a
] += stringf("init %d %d %s\n", (a
>> 1)-1, wire
->start_offset
+i
, log_id(wire
));
650 if (ordered_latches
.count(sig
[i
])) {
651 int l
= ordered_latches
.at(sig
[i
]);
652 if (zinit_mode
&& (aig_latchinit
.at(l
) == 1))
653 latch_lines
[l
] += stringf("invlatch %d %d %s\n", l
, wire
->start_offset
+i
, log_id(wire
));
655 latch_lines
[l
] += stringf("latch %d %d %s\n", l
, wire
->start_offset
+i
, log_id(wire
));
661 for (auto &it
: input_lines
)
665 for (auto &it
: init_lines
)
669 for (auto &it
: output_lines
)
673 for (auto &it
: latch_lines
)
677 for (auto &it
: wire_lines
)
682 struct AigerBackend
: public Backend
{
683 AigerBackend() : Backend("aiger", "write design to AIGER file") { }
686 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
688 log(" write_aiger [options] [filename]\n");
690 log("Write the current design to an AIGER file. The design must be flattened and\n");
691 log("must not contain any cell types except $_AND_, $_NOT_, simple FF types,\n");
692 log("$assert and $assume cells, and $initstate cells.\n");
694 log("$assert and $assume cells are converted to AIGER bad state properties and\n");
695 log("invariant constraints.\n");
698 log(" write ASCII version of AIGER format\n");
701 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
702 log(" uninitialized FFs.\n");
705 log(" design outputs are AIGER bad state properties\n");
708 log(" include a symbol table in the generated AIGER file\n");
710 log(" -map <filename>\n");
711 log(" write an extra file with port and latch symbols\n");
713 log(" -vmap <filename>\n");
714 log(" like -map, but more verbose\n");
716 log(" -I, -O, -B, -L\n");
717 log(" If the design contains no input/output/assert/flip-flop then create one\n");
718 log(" dummy input/output/bad_state-pin or latch to make the tools reading the\n");
719 log(" AIGER file happy.\n");
722 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) override
724 bool ascii_mode
= false;
725 bool zinit_mode
= false;
726 bool miter_mode
= false;
727 bool symbols_mode
= false;
728 bool verbose_map
= false;
733 std::string map_filename
;
735 log_header(design
, "Executing AIGER backend.\n");
738 for (argidx
= 1; argidx
< args
.size(); argidx
++)
740 if (args
[argidx
] == "-ascii") {
744 if (args
[argidx
] == "-zinit") {
748 if (args
[argidx
] == "-miter") {
752 if (args
[argidx
] == "-symbols") {
756 if (map_filename
.empty() && args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
757 map_filename
= args
[++argidx
];
760 if (map_filename
.empty() && args
[argidx
] == "-vmap" && argidx
+1 < args
.size()) {
761 map_filename
= args
[++argidx
];
765 if (args
[argidx
] == "-I") {
769 if (args
[argidx
] == "-O") {
773 if (args
[argidx
] == "-B") {
777 if (args
[argidx
] == "-L") {
783 extra_args(f
, filename
, args
, argidx
, !ascii_mode
);
785 Module
*top_module
= design
->top_module();
787 if (top_module
== nullptr)
788 log_error("Can't find top module in current design!\n");
790 if (!design
->selected_whole_module(top_module
))
791 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module
));
793 if (!top_module
->processes
.empty())
794 log_error("Found unmapped processes in module %s: unmapped processes are not supported in AIGER backend!\n", log_id(top_module
));
795 if (!top_module
->memories
.empty())
796 log_error("Found unmapped memories in module %s: unmapped memories are not supported in AIGER backend!\n", log_id(top_module
));
798 AigerWriter
writer(top_module
, zinit_mode
, imode
, omode
, bmode
, lmode
);
799 writer
.write_aiger(*f
, ascii_mode
, miter_mode
, symbols_mode
);
801 if (!map_filename
.empty()) {
802 rewrite_filename(filename
);
804 mapf
.open(map_filename
.c_str(), std::ofstream::trunc
);
806 log_error("Can't open file `%s' for writing: %s\n", map_filename
.c_str(), strerror(errno
));
807 writer
.write_map(mapf
, verbose_map
);
812 PRIVATE_NAMESPACE_END