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Merge remote-tracking branch 'origin/master' into xaig_dff
[yosys.git] / backends / aiger / aiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 void aiger_encode(std::ostream &f, int x)
27 {
28 log_assert(x >= 0);
29
30 while (x & ~0x7f) {
31 f.put((x & 0x7f) | 0x80);
32 x = x >> 7;
33 }
34
35 f.put(x);
36 }
37
38 struct AigerWriter
39 {
40 Module *module;
41 bool zinit_mode;
42 SigMap sigmap;
43
44 dict<SigBit, bool> init_map;
45 pool<SigBit> input_bits, output_bits;
46 dict<SigBit, SigBit> not_map, ff_map, alias_map;
47 dict<SigBit, pair<SigBit, SigBit>> and_map;
48 vector<pair<SigBit, SigBit>> asserts, assumes;
49 vector<pair<SigBit, SigBit>> liveness, fairness;
50 pool<SigBit> initstate_bits;
51
52 vector<pair<int, int>> aig_gates;
53 vector<int> aig_latchin, aig_latchinit, aig_outputs;
54 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
55 int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0;
56
57 dict<SigBit, int> aig_map;
58 dict<SigBit, int> ordered_outputs;
59 dict<SigBit, int> ordered_latches;
60
61 dict<SigBit, int> init_inputs;
62 int initstate_ff = 0;
63
64 int mkgate(int a0, int a1)
65 {
66 aig_m++, aig_a++;
67 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
68 return 2*aig_m;
69 }
70
71 int bit2aig(SigBit bit)
72 {
73 auto it = aig_map.find(bit);
74 if (it != aig_map.end()) {
75 log_assert(it->second >= 0);
76 return it->second;
77 }
78
79 // NB: Cannot use iterator returned from aig_map.insert()
80 // since this function is called recursively
81
82 int a = -1;
83 if (not_map.count(bit)) {
84 a = bit2aig(not_map.at(bit)) ^ 1;
85 } else
86 if (and_map.count(bit)) {
87 auto args = and_map.at(bit);
88 int a0 = bit2aig(args.first);
89 int a1 = bit2aig(args.second);
90 a = mkgate(a0, a1);
91 } else
92 if (alias_map.count(bit)) {
93 a = bit2aig(alias_map.at(bit));
94 }
95
96 if (bit == State::Sx || bit == State::Sz)
97 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
98
99 log_assert(a >= 0);
100 aig_map[bit] = a;
101 return a;
102 }
103
104 AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
105 {
106 pool<SigBit> undriven_bits;
107 pool<SigBit> unused_bits;
108
109 // promote public wires
110 for (auto wire : module->wires())
111 if (wire->name[0] == '\\')
112 sigmap.add(wire);
113
114 // promote input wires
115 for (auto wire : module->wires())
116 if (wire->port_input)
117 sigmap.add(wire);
118
119 // promote output wires
120 for (auto wire : module->wires())
121 if (wire->port_output)
122 sigmap.add(wire);
123
124 for (auto wire : module->wires())
125 {
126 if (wire->attributes.count("\\init")) {
127 SigSpec initsig = sigmap(wire);
128 Const initval = wire->attributes.at("\\init");
129 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
130 if (initval[i] == State::S0 || initval[i] == State::S1)
131 init_map[initsig[i]] = initval[i] == State::S1;
132 }
133
134 for (int i = 0; i < GetSize(wire); i++)
135 {
136 SigBit wirebit(wire, i);
137 SigBit bit = sigmap(wirebit);
138
139 if (bit.wire == nullptr) {
140 if (wire->port_output) {
141 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
142 output_bits.insert(wirebit);
143 }
144 continue;
145 }
146
147 undriven_bits.insert(bit);
148 unused_bits.insert(bit);
149
150 if (wire->port_input)
151 input_bits.insert(bit);
152
153 if (wire->port_output) {
154 if (bit != wirebit)
155 alias_map[wirebit] = bit;
156 output_bits.insert(wirebit);
157 }
158 }
159 }
160
161 for (auto bit : input_bits)
162 undriven_bits.erase(bit);
163
164 for (auto bit : output_bits)
165 unused_bits.erase(bit);
166
167 for (auto cell : module->cells())
168 {
169 if (cell->type == "$_NOT_")
170 {
171 SigBit A = sigmap(cell->getPort("\\A").as_bit());
172 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
173 unused_bits.erase(A);
174 undriven_bits.erase(Y);
175 not_map[Y] = A;
176 continue;
177 }
178
179 if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
180 {
181 SigBit D = sigmap(cell->getPort("\\D").as_bit());
182 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
183 unused_bits.erase(D);
184 undriven_bits.erase(Q);
185 ff_map[Q] = D;
186 continue;
187 }
188
189 if (cell->type == "$_AND_")
190 {
191 SigBit A = sigmap(cell->getPort("\\A").as_bit());
192 SigBit B = sigmap(cell->getPort("\\B").as_bit());
193 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
194 unused_bits.erase(A);
195 unused_bits.erase(B);
196 undriven_bits.erase(Y);
197 and_map[Y] = make_pair(A, B);
198 continue;
199 }
200
201 if (cell->type == "$initstate")
202 {
203 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
204 undriven_bits.erase(Y);
205 initstate_bits.insert(Y);
206 continue;
207 }
208
209 if (cell->type == "$assert")
210 {
211 SigBit A = sigmap(cell->getPort("\\A").as_bit());
212 SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
213 unused_bits.erase(A);
214 unused_bits.erase(EN);
215 asserts.push_back(make_pair(A, EN));
216 continue;
217 }
218
219 if (cell->type == "$assume")
220 {
221 SigBit A = sigmap(cell->getPort("\\A").as_bit());
222 SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
223 unused_bits.erase(A);
224 unused_bits.erase(EN);
225 assumes.push_back(make_pair(A, EN));
226 continue;
227 }
228
229 if (cell->type == "$live")
230 {
231 SigBit A = sigmap(cell->getPort("\\A").as_bit());
232 SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
233 unused_bits.erase(A);
234 unused_bits.erase(EN);
235 liveness.push_back(make_pair(A, EN));
236 continue;
237 }
238
239 if (cell->type == "$fair")
240 {
241 SigBit A = sigmap(cell->getPort("\\A").as_bit());
242 SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
243 unused_bits.erase(A);
244 unused_bits.erase(EN);
245 fairness.push_back(make_pair(A, EN));
246 continue;
247 }
248
249 if (cell->type == "$anyconst")
250 {
251 for (auto bit : sigmap(cell->getPort("\\Y"))) {
252 undriven_bits.erase(bit);
253 ff_map[bit] = bit;
254 }
255 continue;
256 }
257
258 if (cell->type == "$anyseq")
259 {
260 for (auto bit : sigmap(cell->getPort("\\Y"))) {
261 undriven_bits.erase(bit);
262 input_bits.insert(bit);
263 }
264 continue;
265 }
266
267 log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
268 }
269
270 for (auto bit : unused_bits)
271 undriven_bits.erase(bit);
272
273 if (!undriven_bits.empty()) {
274 undriven_bits.sort();
275 for (auto bit : undriven_bits) {
276 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
277 input_bits.insert(bit);
278 }
279 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
280 }
281
282 init_map.sort();
283 input_bits.sort();
284 output_bits.sort();
285 not_map.sort();
286 ff_map.sort();
287 and_map.sort();
288
289 aig_map[State::S0] = 0;
290 aig_map[State::S1] = 1;
291
292 for (auto bit : input_bits) {
293 aig_m++, aig_i++;
294 aig_map[bit] = 2*aig_m;
295 }
296
297 if (imode && input_bits.empty()) {
298 aig_m++, aig_i++;
299 }
300
301 if (zinit_mode)
302 {
303 for (auto it : ff_map) {
304 if (init_map.count(it.first))
305 continue;
306 aig_m++, aig_i++;
307 init_inputs[it.first] = 2*aig_m;
308 }
309 }
310
311 int fair_live_inputs_cnt = GetSize(liveness);
312 int fair_live_inputs_m = aig_m;
313
314 aig_m += fair_live_inputs_cnt;
315 aig_i += fair_live_inputs_cnt;
316
317 for (auto it : ff_map) {
318 aig_m++, aig_l++;
319 aig_map[it.first] = 2*aig_m;
320 ordered_latches[it.first] = aig_l-1;
321 if (init_map.count(it.first) == 0)
322 aig_latchinit.push_back(2);
323 else
324 aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
325 }
326
327 if (!initstate_bits.empty() || !init_inputs.empty()) {
328 aig_m++, aig_l++;
329 initstate_ff = 2*aig_m+1;
330 aig_latchinit.push_back(0);
331 }
332
333 int fair_live_latches_cnt = GetSize(fairness) + 2*GetSize(liveness);
334 int fair_live_latches_m = aig_m;
335 int fair_live_latches_l = aig_l;
336
337 aig_m += fair_live_latches_cnt;
338 aig_l += fair_live_latches_cnt;
339
340 for (int i = 0; i < fair_live_latches_cnt; i++)
341 aig_latchinit.push_back(0);
342
343 if (zinit_mode)
344 {
345 for (auto it : ff_map)
346 {
347 int l = ordered_latches[it.first];
348
349 if (aig_latchinit.at(l) == 1)
350 aig_map[it.first] ^= 1;
351
352 if (aig_latchinit.at(l) == 2)
353 {
354 int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
355 int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
356 aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
357 }
358 }
359 }
360
361 for (auto it : ff_map) {
362 int a = bit2aig(it.second);
363 int l = ordered_latches[it.first];
364 if (zinit_mode && aig_latchinit.at(l) == 1)
365 aig_latchin.push_back(a ^ 1);
366 else
367 aig_latchin.push_back(a);
368 }
369
370 if (!initstate_bits.empty() || !init_inputs.empty())
371 aig_latchin.push_back(1);
372
373 for (auto bit : output_bits) {
374 aig_o++;
375 ordered_outputs[bit] = aig_o-1;
376 aig_outputs.push_back(bit2aig(bit));
377 }
378
379 if (omode && output_bits.empty()) {
380 aig_o++;
381 aig_outputs.push_back(0);
382 }
383
384 for (auto it : asserts) {
385 aig_b++;
386 int bit_a = bit2aig(it.first);
387 int bit_en = bit2aig(it.second);
388 aig_outputs.push_back(mkgate(bit_a^1, bit_en));
389 }
390
391 if (bmode && asserts.empty()) {
392 aig_b++;
393 aig_outputs.push_back(0);
394 }
395
396 for (auto it : assumes) {
397 aig_c++;
398 int bit_a = bit2aig(it.first);
399 int bit_en = bit2aig(it.second);
400 aig_outputs.push_back(mkgate(bit_a^1, bit_en)^1);
401 }
402
403 for (auto it : liveness)
404 {
405 int input_m = ++fair_live_inputs_m;
406 int latch_m1 = ++fair_live_latches_m;
407 int latch_m2 = ++fair_live_latches_m;
408
409 log_assert(GetSize(aig_latchin) == fair_live_latches_l);
410 fair_live_latches_l += 2;
411
412 int bit_a = bit2aig(it.first);
413 int bit_en = bit2aig(it.second);
414 int bit_s = 2*input_m;
415 int bit_q1 = 2*latch_m1;
416 int bit_q2 = 2*latch_m2;
417
418 int bit_d1 = mkgate(mkgate(bit_s, bit_en)^1, bit_q1^1)^1;
419 int bit_d2 = mkgate(mkgate(bit_d1, bit_a)^1, bit_q2^1)^1;
420
421 aig_j++;
422 aig_latchin.push_back(bit_d1);
423 aig_latchin.push_back(bit_d2);
424 aig_outputs.push_back(mkgate(bit_q1, bit_q2^1));
425 }
426
427 for (auto it : fairness)
428 {
429 int latch_m = ++fair_live_latches_m;
430
431 log_assert(GetSize(aig_latchin) == fair_live_latches_l);
432 fair_live_latches_l += 1;
433
434 int bit_a = bit2aig(it.first);
435 int bit_en = bit2aig(it.second);
436 int bit_q = 2*latch_m;
437
438 aig_f++;
439 aig_latchin.push_back(mkgate(mkgate(bit_q^1, bit_en^1)^1, bit_a^1));
440 aig_outputs.push_back(bit_q^1);
441 }
442 }
443
444 void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
445 {
446 int aig_obc = aig_o + aig_b + aig_c;
447 int aig_obcj = aig_obc + aig_j;
448 int aig_obcjf = aig_obcj + aig_f;
449
450 log_assert(aig_m == aig_i + aig_l + aig_a);
451 log_assert(aig_l == GetSize(aig_latchin));
452 log_assert(aig_l == GetSize(aig_latchinit));
453 log_assert(aig_obcjf == GetSize(aig_outputs));
454
455 if (miter_mode) {
456 if (aig_b || aig_c || aig_j || aig_f)
457 log_error("Running AIGER back-end in -miter mode, but design contains $assert, $assume, $live and/or $fair cells!\n");
458 f << stringf("%s %d %d %d 0 %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_a, aig_o);
459 } else {
460 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
461 if (aig_b || aig_c || aig_j || aig_f)
462 f << stringf(" %d %d %d %d", aig_b, aig_c, aig_j, aig_f);
463 f << stringf("\n");
464 }
465
466 if (ascii_mode)
467 {
468 for (int i = 0; i < aig_i; i++)
469 f << stringf("%d\n", 2*i+2);
470
471 for (int i = 0; i < aig_l; i++) {
472 if (zinit_mode || aig_latchinit.at(i) == 0)
473 f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
474 else if (aig_latchinit.at(i) == 1)
475 f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
476 else if (aig_latchinit.at(i) == 2)
477 f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
478 }
479
480 for (int i = 0; i < aig_obc; i++)
481 f << stringf("%d\n", aig_outputs.at(i));
482
483 for (int i = aig_obc; i < aig_obcj; i++)
484 f << stringf("1\n");
485
486 for (int i = aig_obc; i < aig_obcj; i++)
487 f << stringf("%d\n", aig_outputs.at(i));
488
489 for (int i = aig_obcj; i < aig_obcjf; i++)
490 f << stringf("%d\n", aig_outputs.at(i));
491
492 for (int i = 0; i < aig_a; i++)
493 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
494 }
495 else
496 {
497 for (int i = 0; i < aig_l; i++) {
498 if (zinit_mode || aig_latchinit.at(i) == 0)
499 f << stringf("%d\n", aig_latchin.at(i));
500 else if (aig_latchinit.at(i) == 1)
501 f << stringf("%d 1\n", aig_latchin.at(i));
502 else if (aig_latchinit.at(i) == 2)
503 f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
504 }
505
506 for (int i = 0; i < aig_obc; i++)
507 f << stringf("%d\n", aig_outputs.at(i));
508
509 for (int i = aig_obc; i < aig_obcj; i++)
510 f << stringf("1\n");
511
512 for (int i = aig_obc; i < aig_obcj; i++)
513 f << stringf("%d\n", aig_outputs.at(i));
514
515 for (int i = aig_obcj; i < aig_obcjf; i++)
516 f << stringf("%d\n", aig_outputs.at(i));
517
518 for (int i = 0; i < aig_a; i++) {
519 int lhs = 2*(aig_i+aig_l+i)+2;
520 int rhs0 = aig_gates.at(i).first;
521 int rhs1 = aig_gates.at(i).second;
522 int delta0 = lhs - rhs0;
523 int delta1 = rhs0 - rhs1;
524 aiger_encode(f, delta0);
525 aiger_encode(f, delta1);
526 }
527 }
528
529 if (symbols_mode)
530 {
531 dict<string, vector<string>> symbols;
532
533 for (auto wire : module->wires())
534 {
535 if (wire->name[0] == '$')
536 continue;
537
538 SigSpec sig = sigmap(wire);
539
540 for (int i = 0; i < GetSize(wire); i++)
541 {
542 if (sig[i].wire == nullptr) {
543 if (wire->port_output)
544 sig[i] = SigBit(wire, i);
545 else
546 continue;
547 }
548
549 if (wire->port_input) {
550 int a = aig_map.at(sig[i]);
551 log_assert((a & 1) == 0);
552 if (GetSize(wire) != 1)
553 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
554 else
555 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
556 }
557
558 if (wire->port_output) {
559 int o = ordered_outputs.at(SigSpec(wire, i));
560 if (GetSize(wire) != 1)
561 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
562 else
563 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
564 }
565
566 if (init_inputs.count(sig[i])) {
567 int a = init_inputs.at(sig[i]);
568 log_assert((a & 1) == 0);
569 if (GetSize(wire) != 1)
570 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
571 else
572 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
573 }
574
575 if (ordered_latches.count(sig[i])) {
576 int l = ordered_latches.at(sig[i]);
577 const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
578 if (GetSize(wire) != 1)
579 symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
580 else
581 symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
582 }
583 }
584 }
585
586 symbols.sort();
587
588 for (auto &sym : symbols) {
589 f << sym.first;
590 std::sort(sym.second.begin(), sym.second.end());
591 for (auto &s : sym.second)
592 f << " " << s;
593 f << std::endl;
594 }
595 }
596
597 f << stringf("c\nGenerated by %s\n", yosys_version_str);
598 }
599
600 void write_map(std::ostream &f, bool verbose_map)
601 {
602 dict<int, string> input_lines;
603 dict<int, string> init_lines;
604 dict<int, string> output_lines;
605 dict<int, string> latch_lines;
606 dict<int, string> wire_lines;
607
608 for (auto wire : module->wires())
609 {
610 if (!verbose_map && wire->name[0] == '$')
611 continue;
612
613 SigSpec sig = sigmap(wire);
614
615 for (int i = 0; i < GetSize(wire); i++)
616 {
617 if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr)
618 continue;
619
620 int a = aig_map.at(sig[i]);
621
622 if (verbose_map)
623 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
624
625 if (wire->port_input) {
626 log_assert((a & 1) == 0);
627 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
628 }
629
630 if (wire->port_output) {
631 int o = ordered_outputs.at(sig[i]);
632 output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
633 }
634
635 if (init_inputs.count(sig[i])) {
636 int a = init_inputs.at(sig[i]);
637 log_assert((a & 1) == 0);
638 init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
639 }
640
641 if (ordered_latches.count(sig[i])) {
642 int l = ordered_latches.at(sig[i]);
643 if (zinit_mode && (aig_latchinit.at(l) == 1))
644 latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
645 else
646 latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
647 }
648 }
649 }
650
651 input_lines.sort();
652 for (auto &it : input_lines)
653 f << it.second;
654
655 init_lines.sort();
656 for (auto &it : init_lines)
657 f << it.second;
658
659 output_lines.sort();
660 for (auto &it : output_lines)
661 f << it.second;
662
663 latch_lines.sort();
664 for (auto &it : latch_lines)
665 f << it.second;
666
667 wire_lines.sort();
668 for (auto &it : wire_lines)
669 f << it.second;
670 }
671 };
672
673 struct AigerBackend : public Backend {
674 AigerBackend() : Backend("aiger", "write design to AIGER file") { }
675 void help() YS_OVERRIDE
676 {
677 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
678 log("\n");
679 log(" write_aiger [options] [filename]\n");
680 log("\n");
681 log("Write the current design to an AIGER file. The design must be flattened and\n");
682 log("must not contain any cell types except $_AND_, $_NOT_, simple FF types,\n");
683 log("$assert and $assume cells, and $initstate cells.\n");
684 log("\n");
685 log("$assert and $assume cells are converted to AIGER bad state properties and\n");
686 log("invariant constraints.\n");
687 log("\n");
688 log(" -ascii\n");
689 log(" write ASCII version of AIGER format\n");
690 log("\n");
691 log(" -zinit\n");
692 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
693 log(" uninitialized FFs.\n");
694 log("\n");
695 log(" -miter\n");
696 log(" design outputs are AIGER bad state properties\n");
697 log("\n");
698 log(" -symbols\n");
699 log(" include a symbol table in the generated AIGER file\n");
700 log("\n");
701 log(" -map <filename>\n");
702 log(" write an extra file with port and latch symbols\n");
703 log("\n");
704 log(" -vmap <filename>\n");
705 log(" like -map, but more verbose\n");
706 log("\n");
707 log(" -I, -O, -B\n");
708 log(" If the design contains no input/output/assert then create one\n");
709 log(" dummy input/output/bad_state pin to make the tools reading the\n");
710 log(" AIGER file happy.\n");
711 log("\n");
712 }
713 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
714 {
715 bool ascii_mode = false;
716 bool zinit_mode = false;
717 bool miter_mode = false;
718 bool symbols_mode = false;
719 bool verbose_map = false;
720 bool imode = false;
721 bool omode = false;
722 bool bmode = false;
723 std::string map_filename;
724
725 log_header(design, "Executing AIGER backend.\n");
726
727 size_t argidx;
728 for (argidx = 1; argidx < args.size(); argidx++)
729 {
730 if (args[argidx] == "-ascii") {
731 ascii_mode = true;
732 continue;
733 }
734 if (args[argidx] == "-zinit") {
735 zinit_mode = true;
736 continue;
737 }
738 if (args[argidx] == "-miter") {
739 miter_mode = true;
740 continue;
741 }
742 if (args[argidx] == "-symbols") {
743 symbols_mode = true;
744 continue;
745 }
746 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
747 map_filename = args[++argidx];
748 continue;
749 }
750 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
751 map_filename = args[++argidx];
752 verbose_map = true;
753 continue;
754 }
755 if (args[argidx] == "-I") {
756 imode = true;
757 continue;
758 }
759 if (args[argidx] == "-O") {
760 omode = true;
761 continue;
762 }
763 if (args[argidx] == "-B") {
764 bmode = true;
765 continue;
766 }
767 break;
768 }
769 extra_args(f, filename, args, argidx);
770
771 Module *top_module = design->top_module();
772
773 if (top_module == nullptr)
774 log_error("Can't find top module in current design!\n");
775
776 AigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
777 writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
778
779 if (!map_filename.empty()) {
780 rewrite_filename(filename);
781 std::ofstream mapf;
782 mapf.open(map_filename.c_str(), std::ofstream::trunc);
783 if (mapf.fail())
784 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
785 writer.write_map(mapf, verbose_map);
786 }
787 }
788 } AigerBackend;
789
790 PRIVATE_NAMESPACE_END