projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge pull request #7 from YosysHQ/master
[yosys.git] / backends / aiger / aiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 void aiger_encode(std::ostream &f, int x)
27 {
28 log_assert(x >= 0);
29
30 while (x & ~0x7f) {
31 f.put((x & 0x7f) | 0x80);
32 x = x >> 7;
33 }
34
35 f.put(x);
36 }
37
38 struct AigerWriter
39 {
40 Module *module;
41 bool zinit_mode;
42 SigMap sigmap;
43
44 dict<SigBit, bool> init_map;
45 pool<SigBit> input_bits, output_bits;
46 dict<SigBit, SigBit> not_map, ff_map, alias_map;
47 dict<SigBit, pair<SigBit, SigBit>> and_map;
48 vector<pair<SigBit, SigBit>> asserts, assumes;
49 vector<pair<SigBit, SigBit>> liveness, fairness;
50 pool<SigBit> initstate_bits;
51
52 vector<pair<int, int>> aig_gates;
53 vector<int> aig_latchin, aig_latchinit, aig_outputs;
54 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
55 int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0;
56
57 dict<SigBit, int> aig_map;
58 dict<SigBit, int> ordered_outputs;
59 dict<SigBit, int> ordered_latches;
60
61 dict<SigBit, int> init_inputs;
62 int initstate_ff = 0;
63
64 int mkgate(int a0, int a1)
65 {
66 aig_m++, aig_a++;
67 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
68 return 2*aig_m;
69 }
70
71 int bit2aig(SigBit bit)
72 {
73 auto it = aig_map.find(bit);
74 if (it != aig_map.end()) {
75 log_assert(it->second >= 0);
76 return it->second;
77 }
78
79 // NB: Cannot use iterator returned from aig_map.insert()
80 // since this function is called recursively
81
82 int a = -1;
83 if (not_map.count(bit)) {
84 a = bit2aig(not_map.at(bit)) ^ 1;
85 } else
86 if (and_map.count(bit)) {
87 auto args = and_map.at(bit);
88 int a0 = bit2aig(args.first);
89 int a1 = bit2aig(args.second);
90 a = mkgate(a0, a1);
91 } else
92 if (alias_map.count(bit)) {
93 a = bit2aig(alias_map.at(bit));
94 }
95
96 if (bit == State::Sx || bit == State::Sz)
97 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
98
99 log_assert(a >= 0);
100 aig_map[bit] = a;
101 return a;
102 }
103
104 AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
105 {
106 pool<SigBit> undriven_bits;
107 pool<SigBit> unused_bits;
108
109 // promote public wires
110 for (auto wire : module->wires())
111 if (wire->name[0] == '\\')
112 sigmap.add(wire);
113
114 // promote input wires
115 for (auto wire : module->wires())
116 if (wire->port_input)
117 sigmap.add(wire);
118
119 // promote output wires
120 for (auto wire : module->wires())
121 if (wire->port_output)
122 sigmap.add(wire);
123
124 for (auto wire : module->wires())
125 {
126 if (wire->attributes.count("\\init")) {
127 SigSpec initsig = sigmap(wire);
128 Const initval = wire->attributes.at("\\init");
129 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
130 if (initval[i] == State::S0 || initval[i] == State::S1)
131 init_map[initsig[i]] = initval[i] == State::S1;
132 }
133
134 for (int i = 0; i < GetSize(wire); i++)
135 {
136 SigBit wirebit(wire, i);
137 SigBit bit = sigmap(wirebit);
138
139 if (bit.wire == nullptr) {
140 if (wire->port_output) {
141 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
142 output_bits.insert(wirebit);
143 }
144 continue;
145 }
146
147 undriven_bits.insert(bit);
148 unused_bits.insert(bit);
149
150 if (wire->port_input)
151 input_bits.insert(bit);
152
153 if (wire->port_output) {
154 if (bit != wirebit)
155 alias_map[wirebit] = bit;
156 output_bits.insert(wirebit);
157 }
158 }
159 }
160
161 for (auto bit : input_bits)
162 undriven_bits.erase(bit);
163
164 for (auto bit : output_bits)
165 unused_bits.erase(bit);
166
167 for (auto cell : module->cells())
168 {
169 if (cell->type == "$_NOT_")
170 {
171 SigBit A = sigmap(cell->getPort("\\A").as_bit());
172 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
173 unused_bits.erase(A);
174 undriven_bits.erase(Y);
175 not_map[Y] = A;
176 continue;
177 }
178
179 if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
180 {
181 SigBit D = sigmap(cell->getPort("\\D").as_bit());
182 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
183 unused_bits.erase(D);
184 undriven_bits.erase(Q);
185 ff_map[Q] = D;
186 continue;
187 }
188
189 if (cell->type == "$_AND_")
190 {
191 SigBit A = sigmap(cell->getPort("\\A").as_bit());
192 SigBit B = sigmap(cell->getPort("\\B").as_bit());
193 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
194 unused_bits.erase(A);
195 unused_bits.erase(B);
196 undriven_bits.erase(Y);
197 and_map[Y] = make_pair(A, B);
198 continue;
199 }
200
201 if (cell->type == "$initstate")
202 {
203 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
204 undriven_bits.erase(Y);
205 initstate_bits.insert(Y);
206 continue;
207 }
208
209 if (cell->type == "$assert")
210 {
211 SigBit A = sigmap(cell->getPort("\\A").as_bit());
212 SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
213 unused_bits.erase(A);
214 unused_bits.erase(EN);
215 asserts.push_back(make_pair(A, EN));
216 continue;
217 }
218
219 if (cell->type == "$assume")
220 {
221 SigBit A = sigmap(cell->getPort("\\A").as_bit());
222 SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
223 unused_bits.erase(A);
224 unused_bits.erase(EN);
225 assumes.push_back(make_pair(A, EN));
226 continue;
227 }
228
229 if (cell->type == "$live")
230 {
231 SigBit A = sigmap(cell->getPort("\\A").as_bit());
232 SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
233 unused_bits.erase(A);
234 unused_bits.erase(EN);
235 liveness.push_back(make_pair(A, EN));
236 continue;
237 }
238
239 if (cell->type == "$fair")
240 {
241 SigBit A = sigmap(cell->getPort("\\A").as_bit());
242 SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
243 unused_bits.erase(A);
244 unused_bits.erase(EN);
245 fairness.push_back(make_pair(A, EN));
246 continue;
247 }
248
249 if (cell->type == "$anyconst")
250 {
251 for (auto bit : sigmap(cell->getPort("\\Y"))) {
252 undriven_bits.erase(bit);
253 ff_map[bit] = bit;
254 }
255 continue;
256 }
257
258 if (cell->type == "$anyseq")
259 {
260 for (auto bit : sigmap(cell->getPort("\\Y"))) {
261 undriven_bits.erase(bit);
262 input_bits.insert(bit);
263 }
264 continue;
265 }
266
267 log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
268 }
269
270 for (auto bit : unused_bits)
271 undriven_bits.erase(bit);
272
273 if (!undriven_bits.empty()) {
274 undriven_bits.sort();
275 for (auto bit : undriven_bits) {
276 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
277 input_bits.insert(bit);
278 }
279 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
280 }
281
282 init_map.sort();
283 input_bits.sort();
284 output_bits.sort();
285 not_map.sort();
286 ff_map.sort();
287 and_map.sort();
288
289 aig_map[State::S0] = 0;
290 aig_map[State::S1] = 1;
291
292 for (auto bit : input_bits) {
293 aig_m++, aig_i++;
294 aig_map[bit] = 2*aig_m;
295 }
296
297 if (imode && input_bits.empty()) {
298 aig_m++, aig_i++;
299 }
300
301 if (zinit_mode)
302 {
303 for (auto it : ff_map) {
304 if (init_map.count(it.first))
305 continue;
306 aig_m++, aig_i++;
307 init_inputs[it.first] = 2*aig_m;
308 }
309 }
310
311 int fair_live_inputs_cnt = GetSize(liveness);
312 int fair_live_inputs_m = aig_m;
313
314 aig_m += fair_live_inputs_cnt;
315 aig_i += fair_live_inputs_cnt;
316
317 for (auto it : ff_map) {
318 aig_m++, aig_l++;
319 aig_map[it.first] = 2*aig_m;
320 ordered_latches[it.first] = aig_l-1;
321 if (init_map.count(it.first) == 0)
322 aig_latchinit.push_back(2);
323 else
324 aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
325 }
326
327 if (!initstate_bits.empty() || !init_inputs.empty()) {
328 aig_m++, aig_l++;
329 initstate_ff = 2*aig_m+1;
330 aig_latchinit.push_back(0);
331 }
332
333 int fair_live_latches_cnt = GetSize(fairness) + 2*GetSize(liveness);
334 int fair_live_latches_m = aig_m;
335 int fair_live_latches_l = aig_l;
336
337 aig_m += fair_live_latches_cnt;
338 aig_l += fair_live_latches_cnt;
339
340 for (int i = 0; i < fair_live_latches_cnt; i++)
341 aig_latchinit.push_back(0);
342
343 if (zinit_mode)
344 {
345 for (auto it : ff_map)
346 {
347 int l = ordered_latches[it.first];
348
349 if (aig_latchinit.at(l) == 1)
350 aig_map[it.first] ^= 1;
351
352 if (aig_latchinit.at(l) == 2)
353 {
354 int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
355 int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
356 aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
357 }
358 }
359 }
360
361 for (auto it : ff_map) {
362 int a = bit2aig(it.second);
363 int l = ordered_latches[it.first];
364 if (zinit_mode && aig_latchinit.at(l) == 1)
365 aig_latchin.push_back(a ^ 1);
366 else
367 aig_latchin.push_back(a);
368 }
369
370 if (lmode && aig_l == 0) {
371 aig_m++, aig_l++;
372 aig_latchinit.push_back(0);
373 aig_latchin.push_back(0);
374 }
375
376 if (!initstate_bits.empty() || !init_inputs.empty())
377 aig_latchin.push_back(1);
378
379 for (auto bit : output_bits) {
380 aig_o++;
381 ordered_outputs[bit] = aig_o-1;
382 aig_outputs.push_back(bit2aig(bit));
383 }
384
385 if (omode && output_bits.empty()) {
386 aig_o++;
387 aig_outputs.push_back(0);
388 }
389
390 for (auto it : asserts) {
391 aig_b++;
392 int bit_a = bit2aig(it.first);
393 int bit_en = bit2aig(it.second);
394 aig_outputs.push_back(mkgate(bit_a^1, bit_en));
395 }
396
397 if (bmode && asserts.empty()) {
398 aig_b++;
399 aig_outputs.push_back(0);
400 }
401
402 for (auto it : assumes) {
403 aig_c++;
404 int bit_a = bit2aig(it.first);
405 int bit_en = bit2aig(it.second);
406 aig_outputs.push_back(mkgate(bit_a^1, bit_en)^1);
407 }
408
409 for (auto it : liveness)
410 {
411 int input_m = ++fair_live_inputs_m;
412 int latch_m1 = ++fair_live_latches_m;
413 int latch_m2 = ++fair_live_latches_m;
414
415 log_assert(GetSize(aig_latchin) == fair_live_latches_l);
416 fair_live_latches_l += 2;
417
418 int bit_a = bit2aig(it.first);
419 int bit_en = bit2aig(it.second);
420 int bit_s = 2*input_m;
421 int bit_q1 = 2*latch_m1;
422 int bit_q2 = 2*latch_m2;
423
424 int bit_d1 = mkgate(mkgate(bit_s, bit_en)^1, bit_q1^1)^1;
425 int bit_d2 = mkgate(mkgate(bit_d1, bit_a)^1, bit_q2^1)^1;
426
427 aig_j++;
428 aig_latchin.push_back(bit_d1);
429 aig_latchin.push_back(bit_d2);
430 aig_outputs.push_back(mkgate(bit_q1, bit_q2^1));
431 }
432
433 for (auto it : fairness)
434 {
435 int latch_m = ++fair_live_latches_m;
436
437 log_assert(GetSize(aig_latchin) == fair_live_latches_l);
438 fair_live_latches_l += 1;
439
440 int bit_a = bit2aig(it.first);
441 int bit_en = bit2aig(it.second);
442 int bit_q = 2*latch_m;
443
444 aig_f++;
445 aig_latchin.push_back(mkgate(mkgate(bit_q^1, bit_en^1)^1, bit_a^1));
446 aig_outputs.push_back(bit_q^1);
447 }
448 }
449
450 void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
451 {
452 int aig_obc = aig_o + aig_b + aig_c;
453 int aig_obcj = aig_obc + aig_j;
454 int aig_obcjf = aig_obcj + aig_f;
455
456 log_assert(aig_m == aig_i + aig_l + aig_a);
457 log_assert(aig_l == GetSize(aig_latchin));
458 log_assert(aig_l == GetSize(aig_latchinit));
459 log_assert(aig_obcjf == GetSize(aig_outputs));
460
461 if (miter_mode) {
462 if (aig_b || aig_c || aig_j || aig_f)
463 log_error("Running AIGER back-end in -miter mode, but design contains $assert, $assume, $live and/or $fair cells!\n");
464 f << stringf("%s %d %d %d 0 %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_a, aig_o);
465 } else {
466 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
467 if (aig_b || aig_c || aig_j || aig_f)
468 f << stringf(" %d %d %d %d", aig_b, aig_c, aig_j, aig_f);
469 f << stringf("\n");
470 }
471
472 if (ascii_mode)
473 {
474 for (int i = 0; i < aig_i; i++)
475 f << stringf("%d\n", 2*i+2);
476
477 for (int i = 0; i < aig_l; i++) {
478 if (zinit_mode || aig_latchinit.at(i) == 0)
479 f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
480 else if (aig_latchinit.at(i) == 1)
481 f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
482 else if (aig_latchinit.at(i) == 2)
483 f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
484 }
485
486 for (int i = 0; i < aig_obc; i++)
487 f << stringf("%d\n", aig_outputs.at(i));
488
489 for (int i = aig_obc; i < aig_obcj; i++)
490 f << stringf("1\n");
491
492 for (int i = aig_obc; i < aig_obcj; i++)
493 f << stringf("%d\n", aig_outputs.at(i));
494
495 for (int i = aig_obcj; i < aig_obcjf; i++)
496 f << stringf("%d\n", aig_outputs.at(i));
497
498 for (int i = 0; i < aig_a; i++)
499 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
500 }
501 else
502 {
503 for (int i = 0; i < aig_l; i++) {
504 if (zinit_mode || aig_latchinit.at(i) == 0)
505 f << stringf("%d\n", aig_latchin.at(i));
506 else if (aig_latchinit.at(i) == 1)
507 f << stringf("%d 1\n", aig_latchin.at(i));
508 else if (aig_latchinit.at(i) == 2)
509 f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
510 }
511
512 for (int i = 0; i < aig_obc; i++)
513 f << stringf("%d\n", aig_outputs.at(i));
514
515 for (int i = aig_obc; i < aig_obcj; i++)
516 f << stringf("1\n");
517
518 for (int i = aig_obc; i < aig_obcj; i++)
519 f << stringf("%d\n", aig_outputs.at(i));
520
521 for (int i = aig_obcj; i < aig_obcjf; i++)
522 f << stringf("%d\n", aig_outputs.at(i));
523
524 for (int i = 0; i < aig_a; i++) {
525 int lhs = 2*(aig_i+aig_l+i)+2;
526 int rhs0 = aig_gates.at(i).first;
527 int rhs1 = aig_gates.at(i).second;
528 int delta0 = lhs - rhs0;
529 int delta1 = rhs0 - rhs1;
530 aiger_encode(f, delta0);
531 aiger_encode(f, delta1);
532 }
533 }
534
535 if (symbols_mode)
536 {
537 dict<string, vector<string>> symbols;
538
539 for (auto wire : module->wires())
540 {
541 if (wire->name[0] == '$')
542 continue;
543
544 SigSpec sig = sigmap(wire);
545
546 for (int i = 0; i < GetSize(wire); i++)
547 {
548 if (sig[i].wire == nullptr) {
549 if (wire->port_output)
550 sig[i] = SigBit(wire, i);
551 else
552 continue;
553 }
554
555 if (wire->port_input) {
556 int a = aig_map.at(sig[i]);
557 log_assert((a & 1) == 0);
558 if (GetSize(wire) != 1)
559 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
560 else
561 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
562 }
563
564 if (wire->port_output) {
565 int o = ordered_outputs.at(SigSpec(wire, i));
566 if (GetSize(wire) != 1)
567 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
568 else
569 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
570 }
571
572 if (init_inputs.count(sig[i])) {
573 int a = init_inputs.at(sig[i]);
574 log_assert((a & 1) == 0);
575 if (GetSize(wire) != 1)
576 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
577 else
578 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
579 }
580
581 if (ordered_latches.count(sig[i])) {
582 int l = ordered_latches.at(sig[i]);
583 const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
584 if (GetSize(wire) != 1)
585 symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
586 else
587 symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
588 }
589 }
590 }
591
592 symbols.sort();
593
594 for (auto &sym : symbols) {
595 f << sym.first;
596 std::sort(sym.second.begin(), sym.second.end());
597 for (auto &s : sym.second)
598 f << " " << s;
599 f << std::endl;
600 }
601 }
602
603 f << stringf("c\nGenerated by %s\n", yosys_version_str);
604 }
605
606 void write_map(std::ostream &f, bool verbose_map)
607 {
608 dict<int, string> input_lines;
609 dict<int, string> init_lines;
610 dict<int, string> output_lines;
611 dict<int, string> latch_lines;
612 dict<int, string> wire_lines;
613
614 for (auto wire : module->wires())
615 {
616 if (!verbose_map && wire->name[0] == '$')
617 continue;
618
619 SigSpec sig = sigmap(wire);
620
621 for (int i = 0; i < GetSize(wire); i++)
622 {
623 if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr)
624 continue;
625
626 int a = aig_map.at(sig[i]);
627
628 if (verbose_map)
629 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
630
631 if (wire->port_input) {
632 log_assert((a & 1) == 0);
633 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
634 }
635
636 if (wire->port_output) {
637 int o = ordered_outputs.at(sig[i]);
638 output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
639 }
640
641 if (init_inputs.count(sig[i])) {
642 int a = init_inputs.at(sig[i]);
643 log_assert((a & 1) == 0);
644 init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
645 }
646
647 if (ordered_latches.count(sig[i])) {
648 int l = ordered_latches.at(sig[i]);
649 if (zinit_mode && (aig_latchinit.at(l) == 1))
650 latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
651 else
652 latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
653 }
654 }
655 }
656
657 input_lines.sort();
658 for (auto &it : input_lines)
659 f << it.second;
660
661 init_lines.sort();
662 for (auto &it : init_lines)
663 f << it.second;
664
665 output_lines.sort();
666 for (auto &it : output_lines)
667 f << it.second;
668
669 latch_lines.sort();
670 for (auto &it : latch_lines)
671 f << it.second;
672
673 wire_lines.sort();
674 for (auto &it : wire_lines)
675 f << it.second;
676 }
677 };
678
679 struct AigerBackend : public Backend {
680 AigerBackend() : Backend("aiger", "write design to AIGER file") { }
681 void help() YS_OVERRIDE
682 {
683 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
684 log("\n");
685 log(" write_aiger [options] [filename]\n");
686 log("\n");
687 log("Write the current design to an AIGER file. The design must be flattened and\n");
688 log("must not contain any cell types except $_AND_, $_NOT_, simple FF types,\n");
689 log("$assert and $assume cells, and $initstate cells.\n");
690 log("\n");
691 log("$assert and $assume cells are converted to AIGER bad state properties and\n");
692 log("invariant constraints.\n");
693 log("\n");
694 log(" -ascii\n");
695 log(" write ASCII version of AIGER format\n");
696 log("\n");
697 log(" -zinit\n");
698 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
699 log(" uninitialized FFs.\n");
700 log("\n");
701 log(" -miter\n");
702 log(" design outputs are AIGER bad state properties\n");
703 log("\n");
704 log(" -symbols\n");
705 log(" include a symbol table in the generated AIGER file\n");
706 log("\n");
707 log(" -map <filename>\n");
708 log(" write an extra file with port and latch symbols\n");
709 log("\n");
710 log(" -vmap <filename>\n");
711 log(" like -map, but more verbose\n");
712 log("\n");
713 log(" -I, -O, -B, -L\n");
714 log(" If the design contains no input/output/assert/flip-flop then create one\n");
715 log(" dummy input/output/bad_state-pin or latch to make the tools reading the\n");
716 log(" AIGER file happy.\n");
717 log("\n");
718 }
719 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
720 {
721 bool ascii_mode = false;
722 bool zinit_mode = false;
723 bool miter_mode = false;
724 bool symbols_mode = false;
725 bool verbose_map = false;
726 bool imode = false;
727 bool omode = false;
728 bool bmode = false;
729 bool lmode = false;
730 std::string map_filename;
731
732 log_header(design, "Executing AIGER backend.\n");
733
734 size_t argidx;
735 for (argidx = 1; argidx < args.size(); argidx++)
736 {
737 if (args[argidx] == "-ascii") {
738 ascii_mode = true;
739 continue;
740 }
741 if (args[argidx] == "-zinit") {
742 zinit_mode = true;
743 continue;
744 }
745 if (args[argidx] == "-miter") {
746 miter_mode = true;
747 continue;
748 }
749 if (args[argidx] == "-symbols") {
750 symbols_mode = true;
751 continue;
752 }
753 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
754 map_filename = args[++argidx];
755 continue;
756 }
757 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
758 map_filename = args[++argidx];
759 verbose_map = true;
760 continue;
761 }
762 if (args[argidx] == "-I") {
763 imode = true;
764 continue;
765 }
766 if (args[argidx] == "-O") {
767 omode = true;
768 continue;
769 }
770 if (args[argidx] == "-B") {
771 bmode = true;
772 continue;
773 }
774 if (args[argidx] == "-L") {
775 lmode = true;
776 continue;
777 }
778 break;
779 }
780 extra_args(f, filename, args, argidx);
781
782 Module *top_module = design->top_module();
783
784 if (top_module == nullptr)
785 log_error("Can't find top module in current design!\n");
786
787 AigerWriter writer(top_module, zinit_mode, imode, omode, bmode, lmode);
788 writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
789
790 if (!map_filename.empty()) {
791 rewrite_filename(filename);
792 std::ofstream mapf;
793 mapf.open(map_filename.c_str(), std::ofstream::trunc);
794 if (mapf.fail())
795 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
796 writer.write_map(mapf, verbose_map);
797 }
798 }
799 } AigerBackend;
800
801 PRIVATE_NAMESPACE_END