2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 // https://stackoverflow.com/a/46137633
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
32 inline static uint32_t bswap32(uint32_t x
)
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value
= number_to_be_reversed
;
36 uint8_t lolo
= (value
>> 0) & 0xFF;
37 uint8_t lohi
= (value
>> 8) & 0xFF;
38 uint8_t hilo
= (value
>> 16) & 0xFF;
39 uint8_t hihi
= (value
>> 24) & 0xFF;
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
52 PRIVATE_NAMESPACE_BEGIN
54 inline int32_t to_big_endian(int32_t i32
) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
60 #error "Unknown endianness"
64 void aiger_encode(std::ostream
&f
, int x
)
69 f
.put((x
& 0x7f) | 0x80);
81 pool
<SigBit
> input_bits
, output_bits
;
82 dict
<SigBit
, SigBit
> not_map
, alias_map
;
83 dict
<SigBit
, pair
<SigBit
, SigBit
>> and_map
;
84 vector
<SigBit
> ci_bits
, co_bits
;
85 dict
<SigBit
, Cell
*> ff_bits
;
86 dict
<SigBit
, float> arrival_times
;
88 vector
<pair
<int, int>> aig_gates
;
89 vector
<int> aig_outputs
;
90 int aig_m
= 0, aig_i
= 0, aig_l
= 0, aig_o
= 0, aig_a
= 0;
92 dict
<SigBit
, int> aig_map
;
93 dict
<SigBit
, int> ordered_outputs
;
95 vector
<Cell
*> box_list
;
97 int mkgate(int a0
, int a1
)
100 aig_gates
.push_back(a0
> a1
? make_pair(a0
, a1
) : make_pair(a1
, a0
));
104 int bit2aig(SigBit bit
)
106 auto it
= aig_map
.find(bit
);
107 if (it
!= aig_map
.end()) {
108 log_assert(it
->second
>= 0);
112 // NB: Cannot use iterator returned from aig_map.insert()
113 // since this function is called recursively
116 if (not_map
.count(bit
)) {
117 a
= bit2aig(not_map
.at(bit
)) ^ 1;
119 if (and_map
.count(bit
)) {
120 auto args
= and_map
.at(bit
);
121 int a0
= bit2aig(args
.first
);
122 int a1
= bit2aig(args
.second
);
125 if (alias_map
.count(bit
)) {
126 a
= bit2aig(alias_map
.at(bit
));
129 if (bit
== State::Sx
|| bit
== State::Sz
) {
130 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
131 a
= aig_map
.at(State::S0
);
139 XAigerWriter(Module
*module
, bool holes_mode
=false) : module(module
), sigmap(module
)
141 pool
<SigBit
> undriven_bits
;
142 pool
<SigBit
> unused_bits
;
144 // promote public wires
145 for (auto wire
: module
->wires())
146 if (wire
->name
[0] == '\\')
149 // promote input wires
150 for (auto wire
: module
->wires())
151 if (wire
->port_input
)
154 // promote keep wires
155 for (auto wire
: module
->wires())
156 if (wire
->get_bool_attribute(ID::keep
))
160 for (auto wire
: module
->wires())
161 for (int i
= 0; i
< GetSize(wire
); i
++)
163 SigBit
wirebit(wire
, i
);
164 SigBit bit
= sigmap(wirebit
);
166 if (bit
.wire
== nullptr) {
167 if (wire
->port_output
) {
168 aig_map
[wirebit
] = (bit
== State::S1
) ? 1 : 0;
169 output_bits
.insert(wirebit
);
174 undriven_bits
.insert(bit
);
175 unused_bits
.insert(bit
);
177 if (wire
->port_input
)
178 input_bits
.insert(bit
);
180 if (wire
->port_output
) {
182 alias_map
[wirebit
] = bit
;
183 output_bits
.insert(wirebit
);
187 dict
<IdString
,dict
<IdString
,int>> arrival_cache
;
188 for (auto cell
: module
->cells()) {
189 if (cell
->type
== "$_NOT_")
191 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
192 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
193 unused_bits
.erase(A
);
194 undriven_bits
.erase(Y
);
199 if (cell
->type
== "$_AND_")
201 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
202 SigBit B
= sigmap(cell
->getPort("\\B").as_bit());
203 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
204 unused_bits
.erase(A
);
205 unused_bits
.erase(B
);
206 undriven_bits
.erase(Y
);
207 and_map
[Y
] = make_pair(A
, B
);
211 if (cell
->type
== "$__ABC9_FF_" &&
212 // The presence of an abc9_mergeability attribute indicates
213 // that we do want to pass this flop to ABC
214 cell
->attributes
.count("\\abc9_mergeability"))
216 SigBit D
= sigmap(cell
->getPort("\\D").as_bit());
217 SigBit Q
= sigmap(cell
->getPort("\\Q").as_bit());
218 unused_bits
.erase(D
);
219 undriven_bits
.erase(Q
);
221 auto r
YS_ATTRIBUTE(unused
) = ff_bits
.insert(std::make_pair(D
, cell
));
222 log_assert(r
.second
);
226 RTLIL::Module
* inst_module
= module
->design
->module(cell
->type
);
228 auto it
= cell
->attributes
.find("\\abc9_box_seq");
229 if (it
!= cell
->attributes
.end()) {
230 int abc9_box_seq
= it
->second
.as_int();
231 if (GetSize(box_list
) <= abc9_box_seq
)
232 box_list
.resize(abc9_box_seq
+1);
233 box_list
[abc9_box_seq
] = cell
;
234 // Only flop boxes may have arrival times
235 if (!inst_module
->get_bool_attribute("\\abc9_flop"))
239 auto &cell_arrivals
= arrival_cache
[cell
->type
];
240 for (const auto &conn
: cell
->connections()) {
241 auto r
= cell_arrivals
.insert(conn
.first
);
242 auto &arrival
= r
.first
->second
;
244 auto port_wire
= inst_module
->wire(conn
.first
);
245 if (port_wire
->port_output
) {
246 auto it
= port_wire
->attributes
.find("\\abc9_arrival");
247 if (it
!= port_wire
->attributes
.end()) {
248 if (it
->second
.flags
!= 0)
249 log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire
), log_id(cell
->type
));
250 arrival
= it
->second
.as_int();
255 for (auto bit
: sigmap(conn
.second
))
256 arrival_times
[bit
] = arrival
;
260 bool cell_known
= inst_module
|| cell
->known();
261 for (const auto &c
: cell
->connections()) {
262 if (c
.second
.is_fully_const()) continue;
263 auto port_wire
= inst_module
? inst_module
->wire(c
.first
) : nullptr;
264 auto is_input
= (port_wire
&& port_wire
->port_input
) || !cell_known
|| cell
->input(c
.first
);
265 auto is_output
= (port_wire
&& port_wire
->port_output
) || !cell_known
|| cell
->output(c
.first
);
266 if (!is_input
&& !is_output
)
267 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c
.first
), log_id(cell
), log_id(cell
->type
));
270 for (auto b
: c
.second
) {
273 if (!w
->port_output
|| !cell_known
) {
274 SigBit I
= sigmap(b
);
277 output_bits
.insert(b
);
282 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
285 dict
<IdString
, std::vector
<IdString
>> box_ports
;
286 for (auto cell
: box_list
) {
289 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
290 log_assert(box_module
);
291 log_assert(box_module
->attributes
.count("\\abc9_box_id"));
293 auto r
= box_ports
.insert(cell
->type
);
295 // Make carry in the last PI, and carry out the last PO
296 // since ABC requires it this way
297 IdString carry_in
, carry_out
;
298 for (const auto &port_name
: box_module
->ports
) {
299 auto w
= box_module
->wire(port_name
);
301 if (w
->get_bool_attribute("\\abc9_carry")) {
303 if (carry_in
!= IdString())
304 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module
));
305 carry_in
= port_name
;
307 if (w
->port_output
) {
308 if (carry_out
!= IdString())
309 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module
));
310 carry_out
= port_name
;
314 r
.first
->second
.push_back(port_name
);
317 if (carry_in
!= IdString() && carry_out
== IdString())
318 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module
));
319 if (carry_in
== IdString() && carry_out
!= IdString())
320 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module
));
321 if (carry_in
!= IdString()) {
322 r
.first
->second
.push_back(carry_in
);
323 r
.first
->second
.push_back(carry_out
);
327 // Fully pad all unused input connections of this box cell with S0
328 // Fully pad all undriven output connections of this box cell with anonymous wires
329 for (auto port_name
: r
.first
->second
) {
330 auto w
= box_module
->wire(port_name
);
332 auto rhs
= cell
->getPort(port_name
);
335 SigBit I
= sigmap(b
);
340 alias_map
[b
] = State::S0
;
344 co_bits
.emplace_back(b
);
345 unused_bits
.erase(I
);
348 for (const auto &b
: rhs
.bits()) {
349 SigBit O
= sigmap(b
);
352 ci_bits
.emplace_back(b
);
353 undriven_bits
.erase(O
);
357 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
358 if (box_module
->get_bool_attribute("\\abc9_flop")) {
359 SigSpec rhs
= module
->wire(stringf("%s.abc9_ff.Q", cell
->name
.c_str()));
361 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell
), log_id(module
));
364 SigBit I
= sigmap(b
);
369 alias_map
[b
] = State::S0
;
373 co_bits
.emplace_back(b
);
374 unused_bits
.erase(I
);
379 for (auto bit
: input_bits
)
380 undriven_bits
.erase(bit
);
381 for (auto bit
: output_bits
)
382 unused_bits
.erase(sigmap(bit
));
383 for (auto bit
: unused_bits
)
384 undriven_bits
.erase(bit
);
386 // Make all undriven bits a primary input
387 for (auto bit
: undriven_bits
) {
388 input_bits
.insert(bit
);
389 undriven_bits
.erase(bit
);
393 struct sort_by_port_id
{
394 bool operator()(const RTLIL::SigBit
& a
, const RTLIL::SigBit
& b
) const {
395 return a
.wire
->port_id
< b
.wire
->port_id
||
396 (a
.wire
->port_id
== b
.wire
->port_id
&& a
.offset
< b
.offset
);
399 input_bits
.sort(sort_by_port_id());
400 output_bits
.sort(sort_by_port_id());
403 aig_map
[State::S0
] = 0;
404 aig_map
[State::S1
] = 1;
406 for (const auto &bit
: input_bits
) {
408 log_assert(!aig_map
.count(bit
));
409 aig_map
[bit
] = 2*aig_m
;
412 for (const auto &i
: ff_bits
) {
413 const Cell
*cell
= i
.second
;
414 const SigBit
&q
= sigmap(cell
->getPort("\\Q"));
416 log_assert(!aig_map
.count(q
));
417 aig_map
[q
] = 2*aig_m
;
420 for (auto &bit
: ci_bits
) {
422 log_assert(!aig_map
.count(bit
));
423 aig_map
[bit
] = 2*aig_m
;
426 for (auto bit
: co_bits
) {
427 ordered_outputs
[bit
] = aig_o
++;
428 aig_outputs
.push_back(bit2aig(bit
));
431 for (const auto &bit
: output_bits
) {
432 ordered_outputs
[bit
] = aig_o
++;
433 aig_outputs
.push_back(bit2aig(bit
));
436 for (auto &i
: ff_bits
) {
437 const SigBit
&d
= i
.first
;
439 aig_outputs
.push_back(aig_map
.at(d
));
443 void write_aiger(std::ostream
&f
, bool ascii_mode
)
446 int aig_obcj
= aig_obc
;
447 int aig_obcjf
= aig_obcj
;
449 log_assert(aig_m
== aig_i
+ aig_l
+ aig_a
);
450 log_assert(aig_obcjf
== GetSize(aig_outputs
));
452 f
<< stringf("%s %d %d %d %d %d", ascii_mode
? "aag" : "aig", aig_m
, aig_i
, aig_l
, aig_o
, aig_a
);
457 for (int i
= 0; i
< aig_i
; i
++)
458 f
<< stringf("%d\n", 2*i
+2);
460 for (int i
= 0; i
< aig_obc
; i
++)
461 f
<< stringf("%d\n", aig_outputs
.at(i
));
463 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
466 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
467 f
<< stringf("%d\n", aig_outputs
.at(i
));
469 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
470 f
<< stringf("%d\n", aig_outputs
.at(i
));
472 for (int i
= 0; i
< aig_a
; i
++)
473 f
<< stringf("%d %d %d\n", 2*(aig_i
+aig_l
+i
)+2, aig_gates
.at(i
).first
, aig_gates
.at(i
).second
);
477 for (int i
= 0; i
< aig_obc
; i
++)
478 f
<< stringf("%d\n", aig_outputs
.at(i
));
480 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
483 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
484 f
<< stringf("%d\n", aig_outputs
.at(i
));
486 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
487 f
<< stringf("%d\n", aig_outputs
.at(i
));
489 for (int i
= 0; i
< aig_a
; i
++) {
490 int lhs
= 2*(aig_i
+aig_l
+i
)+2;
491 int rhs0
= aig_gates
.at(i
).first
;
492 int rhs1
= aig_gates
.at(i
).second
;
493 int delta0
= lhs
- rhs0
;
494 int delta1
= rhs0
- rhs1
;
495 aiger_encode(f
, delta0
);
496 aiger_encode(f
, delta1
);
502 auto write_buffer
= [](std::stringstream
&buffer
, int i32
) {
503 int32_t i32_be
= to_big_endian(i32
);
504 buffer
.write(reinterpret_cast<const char*>(&i32_be
), sizeof(i32_be
));
506 std::stringstream h_buffer
;
507 auto write_h_buffer
= std::bind(write_buffer
, std::ref(h_buffer
), std::placeholders::_1
);
509 log_debug("ciNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
) + GetSize(ci_bits
));
510 write_h_buffer(input_bits
.size() + ff_bits
.size() + ci_bits
.size());
511 log_debug("coNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
) + GetSize(co_bits
));
512 write_h_buffer(output_bits
.size() + GetSize(ff_bits
) + GetSize(co_bits
));
513 log_debug("piNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
));
514 write_h_buffer(input_bits
.size() + ff_bits
.size());
515 log_debug("poNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
));
516 write_h_buffer(output_bits
.size() + ff_bits
.size());
517 log_debug("boxNum = %d\n", GetSize(box_list
));
518 write_h_buffer(box_list
.size());
520 auto write_buffer_float
= [](std::stringstream
&buffer
, float f32
) {
521 buffer
.write(reinterpret_cast<const char*>(&f32
), sizeof(f32
));
523 std::stringstream i_buffer
;
524 auto write_i_buffer
= std::bind(write_buffer_float
, std::ref(i_buffer
), std::placeholders::_1
);
525 for (auto bit
: input_bits
)
526 write_i_buffer(arrival_times
.at(bit
, 0));
527 //std::stringstream o_buffer;
528 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
529 //for (auto bit : output_bits)
530 // write_o_buffer(0);
532 if (!box_list
.empty() || !ff_bits
.empty()) {
533 RTLIL::Module
*holes_module
= module
->design
->module(stringf("%s$holes", module
->name
.c_str()));
534 log_assert(holes_module
);
536 dict
<IdString
, std::tuple
<int,int,int>> cell_cache
;
539 for (auto cell
: box_list
) {
542 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
543 log_assert(box_module
);
545 auto r
= cell_cache
.insert(cell
->type
);
546 auto &v
= r
.first
->second
;
548 int box_inputs
= 0, box_outputs
= 0;
549 for (auto port_name
: box_module
->ports
) {
550 RTLIL::Wire
*w
= box_module
->wire(port_name
);
553 box_inputs
+= GetSize(w
);
555 box_outputs
+= GetSize(w
);
558 // For flops only, create an extra 1-bit input that drives a new wire
559 // called "<cell>.abc9_ff.Q" that is used below
560 if (box_module
->get_bool_attribute("\\abc9_flop"))
563 std::get
<0>(v
) = box_inputs
;
564 std::get
<1>(v
) = box_outputs
;
565 std::get
<2>(v
) = box_module
->attributes
.at("\\abc9_box_id").as_int();
568 write_h_buffer(std::get
<0>(v
));
569 write_h_buffer(std::get
<1>(v
));
570 write_h_buffer(std::get
<2>(v
));
571 write_h_buffer(box_count
++);
574 std::stringstream r_buffer
;
575 auto write_r_buffer
= std::bind(write_buffer
, std::ref(r_buffer
), std::placeholders::_1
);
576 log_debug("flopNum = %d\n", GetSize(ff_bits
));
577 write_r_buffer(ff_bits
.size());
579 std::stringstream s_buffer
;
580 auto write_s_buffer
= std::bind(write_buffer
, std::ref(s_buffer
), std::placeholders::_1
);
581 write_s_buffer(ff_bits
.size());
583 for (const auto &i
: ff_bits
) {
584 const SigBit
&d
= i
.first
;
585 const Cell
*cell
= i
.second
;
587 int mergeability
= cell
->attributes
.at(ID(abc9_mergeability
)).as_int();
588 log_assert(mergeability
> 0);
589 write_r_buffer(mergeability
);
591 Const init
= cell
->attributes
.at(ID(abc9_init
));
592 log_assert(GetSize(init
) == 1);
593 if (init
== State::S1
)
595 else if (init
== State::S0
)
598 log_assert(init
== State::Sx
);
602 write_i_buffer(arrival_times
.at(d
, 0));
607 std::string buffer_str
= r_buffer
.str();
608 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
609 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
610 f
.write(buffer_str
.data(), buffer_str
.size());
613 buffer_str
= s_buffer
.str();
614 buffer_size_be
= to_big_endian(buffer_str
.size());
615 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
616 f
.write(buffer_str
.data(), buffer_str
.size());
619 std::stringstream a_buffer
;
620 XAigerWriter
writer(holes_module
, true /* holes_mode */);
621 writer
.write_aiger(a_buffer
, false /*ascii_mode*/);
624 std::string buffer_str
= a_buffer
.str();
625 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
626 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
627 f
.write(buffer_str
.data(), buffer_str
.size());
632 std::string buffer_str
= h_buffer
.str();
633 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
634 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
635 f
.write(buffer_str
.data(), buffer_str
.size());
638 buffer_str
= i_buffer
.str();
639 buffer_size_be
= to_big_endian(buffer_str
.size());
640 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
641 f
.write(buffer_str
.data(), buffer_str
.size());
643 //buffer_str = o_buffer.str();
644 //buffer_size_be = to_big_endian(buffer_str.size());
645 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
646 //f.write(buffer_str.data(), buffer_str.size());
648 f
<< stringf("Generated by %s\n", yosys_version_str
);
650 module
->design
->scratchpad_set_int("write_xaiger.num_ands", and_map
.size());
651 module
->design
->scratchpad_set_int("write_xaiger.num_wires", aig_map
.size());
652 module
->design
->scratchpad_set_int("write_xaiger.num_inputs", input_bits
.size());
653 module
->design
->scratchpad_set_int("write_xaiger.num_outputs", output_bits
.size());
656 void write_map(std::ostream
&f
)
658 dict
<int, string
> input_lines
;
659 dict
<int, string
> output_lines
;
661 for (auto wire
: module
->wires())
663 SigSpec sig
= sigmap(wire
);
665 for (int i
= 0; i
< GetSize(wire
); i
++)
667 RTLIL::SigBit
b(wire
, i
);
668 if (input_bits
.count(b
)) {
669 int a
= aig_map
.at(b
);
670 log_assert((a
& 1) == 0);
671 input_lines
[a
] += stringf("input %d %d %s\n", (a
>> 1)-1, i
, log_id(wire
));
674 if (output_bits
.count(b
)) {
675 int o
= ordered_outputs
.at(b
);
677 output_lines
[o
] += stringf("output %d %d %s %d\n", o
- GetSize(co_bits
), i
, log_id(wire
), init
);
684 for (auto &it
: input_lines
)
686 log_assert(input_lines
.size() == input_bits
.size());
689 for (auto cell
: box_list
)
690 f
<< stringf("box %d %d %s\n", box_count
++, 0, log_id(cell
->name
));
693 for (auto &it
: output_lines
)
695 log_assert(output_lines
.size() == output_bits
.size());
699 struct XAigerBackend
: public Backend
{
700 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
701 void help() YS_OVERRIDE
703 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
705 log(" write_xaiger [options] [filename]\n");
707 log("Write the top module (according to the (* top *) attribute or if only one module\n");
708 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
709 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
710 log("pseudo-outputs.\n");
713 log(" write ASCII version of AIGER format\n");
715 log(" -map <filename>\n");
716 log(" write an extra file with port and box symbols\n");
719 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
721 bool ascii_mode
= false;
722 std::string map_filename
;
724 log_header(design
, "Executing XAIGER backend.\n");
727 for (argidx
= 1; argidx
< args
.size(); argidx
++)
729 if (args
[argidx
] == "-ascii") {
733 if (map_filename
.empty() && args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
734 map_filename
= args
[++argidx
];
739 extra_args(f
, filename
, args
, argidx
, !ascii_mode
);
741 Module
*top_module
= design
->top_module();
743 if (top_module
== nullptr)
744 log_error("Can't find top module in current design!\n");
746 if (!design
->selected_whole_module(top_module
))
747 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module
));
749 if (!top_module
->processes
.empty())
750 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module
));
751 if (!top_module
->memories
.empty())
752 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module
));
754 XAigerWriter
writer(top_module
);
755 writer
.write_aiger(*f
, ascii_mode
);
757 if (!map_filename
.empty()) {
759 mapf
.open(map_filename
.c_str(), std::ofstream::trunc
);
761 log_error("Can't open file `%s' for writing: %s\n", map_filename
.c_str(), strerror(errno
));
762 writer
.write_map(mapf
);
767 PRIVATE_NAMESPACE_END