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1956422bc131165f4f4d15cec009d38325b05bea
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50
51 USING_YOSYS_NAMESPACE
52 PRIVATE_NAMESPACE_BEGIN
53
54 inline int32_t to_big_endian(int32_t i32) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
56 return bswap32(i32);
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
58 return i32;
59 #else
60 #error "Unknown endianness"
61 #endif
62 }
63
64 void aiger_encode(std::ostream &f, int x)
65 {
66 log_assert(x >= 0);
67
68 while (x & ~0x7f) {
69 f.put((x & 0x7f) | 0x80);
70 x = x >> 7;
71 }
72
73 f.put(x);
74 }
75
76 struct XAigerWriter
77 {
78 Module *module;
79 SigMap sigmap;
80
81 pool<SigBit> input_bits, output_bits;
82 dict<SigBit, SigBit> not_map, alias_map;
83 dict<SigBit, pair<SigBit, SigBit>> and_map;
84 vector<SigBit> ci_bits, co_bits;
85 dict<SigBit, Cell*> ff_bits;
86 dict<SigBit, float> arrival_times;
87
88 vector<pair<int, int>> aig_gates;
89 vector<int> aig_outputs;
90 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
91
92 dict<SigBit, int> aig_map;
93 dict<SigBit, int> ordered_outputs;
94
95 vector<Cell*> box_list;
96 dict<IdString, std::vector<IdString>> box_ports;
97
98 int mkgate(int a0, int a1)
99 {
100 aig_m++, aig_a++;
101 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
102 return 2*aig_m;
103 }
104
105 int bit2aig(SigBit bit)
106 {
107 auto it = aig_map.find(bit);
108 if (it != aig_map.end()) {
109 log_assert(it->second >= 0);
110 return it->second;
111 }
112
113 // NB: Cannot use iterator returned from aig_map.insert()
114 // since this function is called recursively
115
116 int a = -1;
117 if (not_map.count(bit)) {
118 a = bit2aig(not_map.at(bit)) ^ 1;
119 } else
120 if (and_map.count(bit)) {
121 auto args = and_map.at(bit);
122 int a0 = bit2aig(args.first);
123 int a1 = bit2aig(args.second);
124 a = mkgate(a0, a1);
125 } else
126 if (alias_map.count(bit)) {
127 a = bit2aig(alias_map.at(bit));
128 }
129
130 if (bit == State::Sx || bit == State::Sz) {
131 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
132 a = aig_map.at(State::S0);
133 }
134
135 log_assert(a >= 0);
136 aig_map[bit] = a;
137 return a;
138 }
139
140 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
141 {
142 pool<SigBit> undriven_bits;
143 pool<SigBit> unused_bits;
144
145 // promote public wires
146 for (auto wire : module->wires())
147 if (wire->name[0] == '\\')
148 sigmap.add(wire);
149
150 // promote input wires
151 for (auto wire : module->wires())
152 if (wire->port_input)
153 sigmap.add(wire);
154
155 // promote keep wires
156 for (auto wire : module->wires())
157 if (wire->get_bool_attribute(ID::keep))
158 sigmap.add(wire);
159
160
161 for (auto wire : module->wires())
162 for (int i = 0; i < GetSize(wire); i++)
163 {
164 SigBit wirebit(wire, i);
165 SigBit bit = sigmap(wirebit);
166
167 if (bit.wire == nullptr) {
168 if (wire->port_output) {
169 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
170 output_bits.insert(wirebit);
171 }
172 continue;
173 }
174
175 undriven_bits.insert(bit);
176 unused_bits.insert(bit);
177
178 if (wire->port_input)
179 input_bits.insert(bit);
180
181 if (wire->port_output) {
182 if (bit != wirebit)
183 alias_map[wirebit] = bit;
184 output_bits.insert(wirebit);
185 }
186 }
187
188 std::vector<int> arrivals;
189 for (auto cell : module->cells()) {
190 if (cell->type == "$_NOT_")
191 {
192 SigBit A = sigmap(cell->getPort("\\A").as_bit());
193 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
194 unused_bits.erase(A);
195 undriven_bits.erase(Y);
196 not_map[Y] = A;
197 continue;
198 }
199
200 if (cell->type == "$_AND_")
201 {
202 SigBit A = sigmap(cell->getPort("\\A").as_bit());
203 SigBit B = sigmap(cell->getPort("\\B").as_bit());
204 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
205 unused_bits.erase(A);
206 unused_bits.erase(B);
207 undriven_bits.erase(Y);
208 and_map[Y] = make_pair(A, B);
209 continue;
210 }
211
212 if (cell->type == "$__ABC9_FF_" &&
213 // The presence of an abc9_mergeability attribute indicates
214 // that we do want to pass this flop to ABC
215 cell->attributes.count("\\abc9_mergeability"))
216 {
217 SigBit D = sigmap(cell->getPort("\\D").as_bit());
218 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
219 unused_bits.erase(D);
220 undriven_bits.erase(Q);
221 alias_map[Q] = D;
222 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
223 log_assert(r.second);
224 continue;
225 }
226
227 RTLIL::Module* inst_module = module->design->module(cell->type);
228 if (inst_module && inst_module->get_blackbox_attribute()) {
229 auto it = cell->attributes.find("\\abc9_box_seq");
230 if (it != cell->attributes.end()) {
231 int abc9_box_seq = it->second.as_int();
232 if (GetSize(box_list) <= abc9_box_seq)
233 box_list.resize(abc9_box_seq+1);
234 box_list[abc9_box_seq] = cell;
235 // Only flop boxes may have arrival times
236 // (all others are combinatorial)
237 if (!inst_module->get_bool_attribute("\\abc9_flop"))
238 continue;
239 }
240
241 for (const auto &conn : cell->connections()) {
242 auto port_wire = inst_module->wire(conn.first);
243 if (port_wire->port_output) {
244 arrivals.clear();
245 auto it = port_wire->attributes.find("\\abc9_arrival");
246 if (it != port_wire->attributes.end()) {
247 if (it->second.flags == 0)
248 arrivals.emplace_back(it->second.as_int());
249 else
250 for (const auto &tok : split_tokens(it->second.decode_string()))
251 arrivals.push_back(atoi(tok.c_str()));
252 }
253 if (!arrivals.empty()) {
254 if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
255 log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
256 GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
257 auto jt = arrivals.begin();
258 for (auto bit : sigmap(conn.second)) {
259 arrival_times[bit] = *jt;
260 if (arrivals.size() > 1)
261 jt++;
262 }
263 }
264 }
265 }
266 }
267
268 bool cell_known = inst_module || cell->known();
269 for (const auto &c : cell->connections()) {
270 if (c.second.is_fully_const()) continue;
271 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
272 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
273 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
274 if (!is_input && !is_output)
275 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
276
277 if (is_input)
278 for (auto b : c.second) {
279 Wire *w = b.wire;
280 if (!w) continue;
281 if (!w->port_output || !cell_known) {
282 SigBit I = sigmap(b);
283 if (I != b)
284 alias_map[b] = I;
285 output_bits.insert(b);
286 }
287 }
288 }
289
290 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
291 }
292
293 for (auto cell : box_list) {
294 log_assert(cell);
295
296 RTLIL::Module* box_module = module->design->module(cell->type);
297 log_assert(box_module);
298 log_assert(box_module->attributes.count("\\abc9_box_id"));
299
300 auto r = box_ports.insert(cell->type);
301 if (r.second) {
302 // Make carry in the last PI, and carry out the last PO
303 // since ABC requires it this way
304 IdString carry_in, carry_out;
305 for (const auto &port_name : box_module->ports) {
306 auto w = box_module->wire(port_name);
307 log_assert(w);
308 if (w->get_bool_attribute("\\abc9_carry")) {
309 if (w->port_input) {
310 if (carry_in != IdString())
311 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
312 carry_in = port_name;
313 }
314 if (w->port_output) {
315 if (carry_out != IdString())
316 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
317 carry_out = port_name;
318 }
319 }
320 else
321 r.first->second.push_back(port_name);
322 }
323
324 if (carry_in != IdString() && carry_out == IdString())
325 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
326 if (carry_in == IdString() && carry_out != IdString())
327 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
328 if (carry_in != IdString()) {
329 r.first->second.push_back(carry_in);
330 r.first->second.push_back(carry_out);
331 }
332 }
333
334 // Fully pad all unused input connections of this box cell with S0
335 // Fully pad all undriven output connections of this box cell with anonymous wires
336 for (auto port_name : r.first->second) {
337 auto w = box_module->wire(port_name);
338 log_assert(w);
339 auto rhs = cell->getPort(port_name);
340 if (w->port_input)
341 for (auto b : rhs) {
342 SigBit I = sigmap(b);
343 if (b == RTLIL::Sx)
344 b = State::S0;
345 else if (I != b) {
346 if (I == RTLIL::Sx)
347 alias_map[b] = State::S0;
348 else
349 alias_map[b] = I;
350 }
351 co_bits.emplace_back(b);
352 unused_bits.erase(I);
353 }
354 if (w->port_output)
355 for (const auto &b : rhs.bits()) {
356 SigBit O = sigmap(b);
357 if (O != b)
358 alias_map[O] = b;
359 ci_bits.emplace_back(b);
360 undriven_bits.erase(O);
361 }
362 }
363
364 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
365 if (box_module->get_bool_attribute("\\abc9_flop")) {
366 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
367 if (rhs.empty())
368 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
369
370 for (auto b : rhs) {
371 SigBit I = sigmap(b);
372 if (b == RTLIL::Sx)
373 b = State::S0;
374 else if (I != b) {
375 if (I == RTLIL::Sx)
376 alias_map[b] = State::S0;
377 else
378 alias_map[b] = I;
379 }
380 co_bits.emplace_back(b);
381 unused_bits.erase(I);
382 }
383 }
384 }
385
386 for (auto bit : input_bits)
387 undriven_bits.erase(bit);
388 for (auto bit : output_bits)
389 unused_bits.erase(sigmap(bit));
390 for (auto bit : unused_bits)
391 undriven_bits.erase(bit);
392
393 // Make all undriven bits a primary input
394 for (auto bit : undriven_bits) {
395 input_bits.insert(bit);
396 undriven_bits.erase(bit);
397 }
398
399 if (holes_mode) {
400 struct sort_by_port_id {
401 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
402 return a.wire->port_id < b.wire->port_id;
403 }
404 };
405 input_bits.sort(sort_by_port_id());
406 output_bits.sort(sort_by_port_id());
407 }
408
409 aig_map[State::S0] = 0;
410 aig_map[State::S1] = 1;
411
412 for (const auto &bit : input_bits) {
413 aig_m++, aig_i++;
414 log_assert(!aig_map.count(bit));
415 aig_map[bit] = 2*aig_m;
416 }
417
418 for (const auto &i : ff_bits) {
419 const Cell *cell = i.second;
420 const SigBit &q = sigmap(cell->getPort("\\Q"));
421 aig_m++, aig_i++;
422 log_assert(!aig_map.count(q));
423 aig_map[q] = 2*aig_m;
424 }
425
426 for (auto &bit : ci_bits) {
427 aig_m++, aig_i++;
428 log_assert(!aig_map.count(bit));
429 aig_map[bit] = 2*aig_m;
430 }
431
432 for (auto bit : co_bits) {
433 ordered_outputs[bit] = aig_o++;
434 aig_outputs.push_back(bit2aig(bit));
435 }
436
437 for (const auto &bit : output_bits) {
438 ordered_outputs[bit] = aig_o++;
439 aig_outputs.push_back(bit2aig(bit));
440 }
441
442 for (auto &i : ff_bits) {
443 const SigBit &d = i.first;
444 aig_o++;
445 aig_outputs.push_back(aig_map.at(d));
446 }
447 }
448
449 void write_aiger(std::ostream &f, bool ascii_mode)
450 {
451 int aig_obc = aig_o;
452 int aig_obcj = aig_obc;
453 int aig_obcjf = aig_obcj;
454
455 log_assert(aig_m == aig_i + aig_l + aig_a);
456 log_assert(aig_obcjf == GetSize(aig_outputs));
457
458 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
459 f << stringf("\n");
460
461 if (ascii_mode)
462 {
463 for (int i = 0; i < aig_i; i++)
464 f << stringf("%d\n", 2*i+2);
465
466 for (int i = 0; i < aig_obc; i++)
467 f << stringf("%d\n", aig_outputs.at(i));
468
469 for (int i = aig_obc; i < aig_obcj; i++)
470 f << stringf("1\n");
471
472 for (int i = aig_obc; i < aig_obcj; i++)
473 f << stringf("%d\n", aig_outputs.at(i));
474
475 for (int i = aig_obcj; i < aig_obcjf; i++)
476 f << stringf("%d\n", aig_outputs.at(i));
477
478 for (int i = 0; i < aig_a; i++)
479 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
480 }
481 else
482 {
483 for (int i = 0; i < aig_obc; i++)
484 f << stringf("%d\n", aig_outputs.at(i));
485
486 for (int i = aig_obc; i < aig_obcj; i++)
487 f << stringf("1\n");
488
489 for (int i = aig_obc; i < aig_obcj; i++)
490 f << stringf("%d\n", aig_outputs.at(i));
491
492 for (int i = aig_obcj; i < aig_obcjf; i++)
493 f << stringf("%d\n", aig_outputs.at(i));
494
495 for (int i = 0; i < aig_a; i++) {
496 int lhs = 2*(aig_i+aig_l+i)+2;
497 int rhs0 = aig_gates.at(i).first;
498 int rhs1 = aig_gates.at(i).second;
499 int delta0 = lhs - rhs0;
500 int delta1 = rhs0 - rhs1;
501 aiger_encode(f, delta0);
502 aiger_encode(f, delta1);
503 }
504 }
505
506 f << "c";
507
508 auto write_buffer = [](std::stringstream &buffer, int i32) {
509 int32_t i32_be = to_big_endian(i32);
510 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
511 };
512 std::stringstream h_buffer;
513 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
514 write_h_buffer(1);
515 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
516 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
517 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
518 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
519 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
520 write_h_buffer(input_bits.size() + ff_bits.size());
521 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
522 write_h_buffer(output_bits.size() + ff_bits.size());
523 log_debug("boxNum = %d\n", GetSize(box_list));
524 write_h_buffer(box_list.size());
525
526 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
527 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
528 };
529 std::stringstream i_buffer;
530 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
531 for (auto bit : input_bits)
532 write_i_buffer(arrival_times.at(bit, 0));
533 //std::stringstream o_buffer;
534 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
535 //for (auto bit : output_bits)
536 // write_o_buffer(0);
537
538 if (!box_list.empty() || !ff_bits.empty()) {
539 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
540 log_assert(holes_module);
541
542 dict<IdString, Cell*> cell_cache;
543
544 int box_count = 0;
545 for (auto cell : box_list) {
546 log_assert(cell);
547
548 RTLIL::Module* box_module = module->design->module(cell->type);
549 log_assert(box_module);
550
551 int box_inputs = 0, box_outputs = 0;
552 for (auto port_name : box_module->ports) {
553 RTLIL::Wire *w = box_module->wire(port_name);
554 log_assert(w);
555 if (w->port_input)
556 box_inputs += GetSize(w);
557 if (w->port_output)
558 box_outputs += GetSize(w);
559 }
560
561 // For flops only, create an extra 1-bit input that drives a new wire
562 // called "<cell>.abc9_ff.Q" that is used below
563 if (box_module->get_bool_attribute("\\abc9_flop"))
564 box_inputs++;
565
566 write_h_buffer(box_inputs);
567 write_h_buffer(box_outputs);
568 write_h_buffer(box_module->attributes.at("\\abc9_box_id").as_int());
569 write_h_buffer(box_count++);
570 }
571
572 std::stringstream r_buffer;
573 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
574 log_debug("flopNum = %d\n", GetSize(ff_bits));
575 write_r_buffer(ff_bits.size());
576
577 std::stringstream s_buffer;
578 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
579 write_s_buffer(ff_bits.size());
580
581 for (const auto &i : ff_bits) {
582 const SigBit &d = i.first;
583 const Cell *cell = i.second;
584
585 int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
586 log_assert(mergeability > 0);
587 write_r_buffer(mergeability);
588
589 Const init = cell->attributes.at(ID(abc9_init));
590 log_assert(GetSize(init) == 1);
591 if (init == State::S1)
592 write_s_buffer(1);
593 else if (init == State::S0)
594 write_s_buffer(0);
595 else {
596 log_assert(init == State::Sx);
597 write_s_buffer(0);
598 }
599
600 write_i_buffer(arrival_times.at(d, 0));
601 //write_o_buffer(0);
602 }
603
604 f << "r";
605 std::string buffer_str = r_buffer.str();
606 int32_t buffer_size_be = to_big_endian(buffer_str.size());
607 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
608 f.write(buffer_str.data(), buffer_str.size());
609
610 f << "s";
611 buffer_str = s_buffer.str();
612 buffer_size_be = to_big_endian(buffer_str.size());
613 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
614 f.write(buffer_str.data(), buffer_str.size());
615
616 if (holes_module) {
617 std::stringstream a_buffer;
618 XAigerWriter writer(holes_module, true /* holes_mode */);
619 writer.write_aiger(a_buffer, false /*ascii_mode*/);
620
621 f << "a";
622 std::string buffer_str = a_buffer.str();
623 int32_t buffer_size_be = to_big_endian(buffer_str.size());
624 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
625 f.write(buffer_str.data(), buffer_str.size());
626 }
627 }
628
629 f << "h";
630 std::string buffer_str = h_buffer.str();
631 int32_t buffer_size_be = to_big_endian(buffer_str.size());
632 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
633 f.write(buffer_str.data(), buffer_str.size());
634
635 f << "i";
636 buffer_str = i_buffer.str();
637 buffer_size_be = to_big_endian(buffer_str.size());
638 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
639 f.write(buffer_str.data(), buffer_str.size());
640 //f << "o";
641 //buffer_str = o_buffer.str();
642 //buffer_size_be = to_big_endian(buffer_str.size());
643 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
644 //f.write(buffer_str.data(), buffer_str.size());
645
646 f << stringf("Generated by %s\n", yosys_version_str);
647
648 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
649 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
650 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
651 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
652 }
653
654 void write_map(std::ostream &f)
655 {
656 dict<int, string> input_lines;
657 dict<int, string> output_lines;
658
659 for (auto wire : module->wires())
660 {
661 SigSpec sig = sigmap(wire);
662
663 for (int i = 0; i < GetSize(wire); i++)
664 {
665 RTLIL::SigBit b(wire, i);
666 if (input_bits.count(b)) {
667 int a = aig_map.at(b);
668 log_assert((a & 1) == 0);
669 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
670 }
671
672 if (output_bits.count(b)) {
673 int o = ordered_outputs.at(b);
674 int init = 2;
675 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
676 continue;
677 }
678 }
679 }
680
681 input_lines.sort();
682 for (auto &it : input_lines)
683 f << it.second;
684 log_assert(input_lines.size() == input_bits.size());
685
686 int box_count = 0;
687 for (auto cell : box_list)
688 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
689
690 output_lines.sort();
691 for (auto &it : output_lines)
692 f << it.second;
693 log_assert(output_lines.size() == output_bits.size());
694 }
695 };
696
697 struct XAigerBackend : public Backend {
698 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
699 void help() YS_OVERRIDE
700 {
701 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
702 log("\n");
703 log(" write_xaiger [options] [filename]\n");
704 log("\n");
705 log("Write the top module (according to the (* top *) attribute or if only one module\n");
706 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
707 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
708 log("pseudo-outputs.\n");
709 log("\n");
710 log(" -ascii\n");
711 log(" write ASCII version of AIGER format\n");
712 log("\n");
713 log(" -map <filename>\n");
714 log(" write an extra file with port and box symbols\n");
715 log("\n");
716 }
717 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
718 {
719 bool ascii_mode = false;
720 std::string map_filename;
721
722 log_header(design, "Executing XAIGER backend.\n");
723
724 size_t argidx;
725 for (argidx = 1; argidx < args.size(); argidx++)
726 {
727 if (args[argidx] == "-ascii") {
728 ascii_mode = true;
729 continue;
730 }
731 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
732 map_filename = args[++argidx];
733 continue;
734 }
735 break;
736 }
737 extra_args(f, filename, args, argidx, !ascii_mode);
738
739 Module *top_module = design->top_module();
740
741 if (top_module == nullptr)
742 log_error("Can't find top module in current design!\n");
743
744 if (!design->selected_whole_module(top_module))
745 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
746
747 if (!top_module->processes.empty())
748 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
749 if (!top_module->memories.empty())
750 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
751
752 XAigerWriter writer(top_module);
753 writer.write_aiger(*f, ascii_mode);
754
755 if (!map_filename.empty()) {
756 std::ofstream mapf;
757 mapf.open(map_filename.c_str(), std::ofstream::trunc);
758 if (mapf.fail())
759 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
760 writer.write_map(mapf);
761 }
762 }
763 } XAigerBackend;
764
765 PRIVATE_NAMESPACE_END