2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 // https://stackoverflow.com/a/46137633
24 #define __builtin_bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define __builtin_bswap32 OSSwapInt32
30 #include "kernel/yosys.h"
31 #include "kernel/sigtools.h"
32 #include "kernel/utils.h"
35 PRIVATE_NAMESPACE_BEGIN
37 inline int32_t to_big_endian(int32_t i32
) {
38 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
39 return __builtin_bswap32(i32
);
40 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
43 #error "Unknown endianness"
47 void aiger_encode(std::ostream
&f
, int x
)
52 f
.put((x
& 0x7f) | 0x80);
64 pool
<SigBit
> input_bits
, output_bits
;
65 dict
<SigBit
, SigBit
> not_map
, alias_map
;
66 dict
<SigBit
, pair
<SigBit
, SigBit
>> and_map
;
67 vector
<std::tuple
<SigBit
,RTLIL::Cell
*,RTLIL::IdString
,int>> ci_bits
;
68 vector
<std::tuple
<SigBit
,RTLIL::Cell
*,RTLIL::IdString
,int,int>> co_bits
;
70 vector
<pair
<int, int>> aig_gates
;
71 vector
<int> aig_outputs
;
72 int aig_m
= 0, aig_i
= 0, aig_l
= 0, aig_o
= 0, aig_a
= 0;
74 dict
<SigBit
, int> aig_map
;
75 dict
<SigBit
, int> ordered_outputs
;
77 vector
<Cell
*> box_list
;
80 int mkgate(int a0
, int a1
)
83 aig_gates
.push_back(a0
> a1
? make_pair(a0
, a1
) : make_pair(a1
, a0
));
87 int bit2aig(SigBit bit
)
89 auto it
= aig_map
.find(bit
);
90 if (it
!= aig_map
.end()) {
91 log_assert(it
->second
>= 0);
95 // NB: Cannot use iterator returned from aig_map.insert()
96 // since this function is called recursively
99 if (not_map
.count(bit
)) {
100 a
= bit2aig(not_map
.at(bit
)) ^ 1;
102 if (and_map
.count(bit
)) {
103 auto args
= and_map
.at(bit
);
104 int a0
= bit2aig(args
.first
);
105 int a1
= bit2aig(args
.second
);
108 if (alias_map
.count(bit
)) {
109 a
= bit2aig(alias_map
.at(bit
));
112 if (bit
== State::Sx
|| bit
== State::Sz
) {
113 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
114 a
= aig_map
.at(State::S0
);
122 XAigerWriter(Module
*module
, bool holes_mode
=false) : module(module
), sigmap(module
)
124 pool
<SigBit
> undriven_bits
;
125 pool
<SigBit
> unused_bits
;
127 // promote public wires
128 for (auto wire
: module
->wires())
129 if (wire
->name
[0] == '\\')
132 // promote input wires
133 for (auto wire
: module
->wires())
134 if (wire
->port_input
)
137 // promote output wires
138 for (auto wire
: module
->wires())
139 if (wire
->port_output
)
142 for (auto wire
: module
->wires())
144 bool keep
= wire
->attributes
.count("\\keep");
146 for (int i
= 0; i
< GetSize(wire
); i
++)
148 SigBit
wirebit(wire
, i
);
149 SigBit bit
= sigmap(wirebit
);
152 undriven_bits
.insert(bit
);
153 unused_bits
.insert(bit
);
156 if (wire
->port_input
|| keep
) {
158 alias_map
[bit
] = wirebit
;
159 input_bits
.insert(wirebit
);
162 if (wire
->port_output
|| keep
) {
163 if (bit
!= RTLIL::Sx
) {
165 alias_map
[wirebit
] = bit
;
166 output_bits
.insert(wirebit
);
169 log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit
));
174 for (auto bit
: input_bits
)
175 undriven_bits
.erase(sigmap(bit
));
176 for (auto bit
: output_bits
)
177 if (!bit
.wire
->port_input
)
178 unused_bits
.erase(bit
);
180 // TODO: Speed up toposort -- ultimately we care about
181 // box ordering, but not individual AIG cells
182 dict
<SigBit
, pool
<IdString
>> bit_drivers
, bit_users
;
183 TopoSort
<IdString
, RTLIL::sort_by_id_str
> toposort
;
184 bool abc_box_seen
= false;
186 for (auto cell
: module
->selected_cells()) {
187 if (cell
->type
== "$_NOT_")
189 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
190 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
191 unused_bits
.erase(A
);
192 undriven_bits
.erase(Y
);
195 toposort
.node(cell
->name
);
196 bit_users
[A
].insert(cell
->name
);
197 bit_drivers
[Y
].insert(cell
->name
);
202 if (cell
->type
== "$_AND_")
204 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
205 SigBit B
= sigmap(cell
->getPort("\\B").as_bit());
206 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
207 unused_bits
.erase(A
);
208 unused_bits
.erase(B
);
209 undriven_bits
.erase(Y
);
210 and_map
[Y
] = make_pair(A
, B
);
212 toposort
.node(cell
->name
);
213 bit_users
[A
].insert(cell
->name
);
214 bit_users
[B
].insert(cell
->name
);
215 bit_drivers
[Y
].insert(cell
->name
);
220 log_assert(!holes_mode
);
222 RTLIL::Module
* inst_module
= module
->design
->module(cell
->type
);
223 if (inst_module
&& inst_module
->attributes
.count("\\abc_box_id")) {
227 toposort
.node(cell
->name
);
228 for (const auto &conn
: cell
->connections()) {
229 if (cell
->input(conn
.first
)) {
230 // Ignore inout for the sake of topographical ordering
231 if (cell
->output(conn
.first
)) continue;
232 for (auto bit
: sigmap(conn
.second
))
233 bit_users
[bit
].insert(cell
->name
);
236 if (cell
->output(conn
.first
))
237 for (auto bit
: sigmap(conn
.second
))
238 bit_drivers
[bit
].insert(cell
->name
);
243 for (const auto &c
: cell
->connections()) {
244 if (c
.second
.is_fully_const()) continue;
245 auto is_input
= cell
->input(c
.first
);
246 auto is_output
= cell
->output(c
.first
);
247 if (!is_input
&& !is_output
)
248 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c
.first
), log_id(cell
), log_id(cell
->type
));
251 for (auto b
: c
.second
.bits()) {
254 if (!w
->port_output
) {
255 SigBit I
= sigmap(b
);
258 output_bits
.insert(b
);
259 unused_bits
.erase(b
);
264 for (auto b
: c
.second
.bits()) {
267 input_bits
.insert(b
);
268 SigBit O
= sigmap(b
);
271 undriven_bits
.erase(O
);
277 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
281 for (auto &it
: bit_users
)
282 if (bit_drivers
.count(it
.first
))
283 for (auto driver_cell
: bit_drivers
.at(it
.first
))
284 for (auto user_cell
: it
.second
)
285 toposort
.edge(driver_cell
, user_cell
);
287 pool
<RTLIL::Module
*> abc_carry_modules
;
290 toposort
.analyze_loops
= true;
292 bool no_loops
= toposort
.sort();
295 for (auto &it
: toposort
.loops
) {
296 log(" loop %d", i
++);
298 log(" %s", log_id(cell
));
302 log_assert(no_loops
);
304 for (auto cell_name
: toposort
.sorted
) {
305 RTLIL::Cell
*cell
= module
->cell(cell_name
);
306 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
307 if (!box_module
|| !box_module
->attributes
.count("\\abc_box_id"))
310 if (box_module
->attributes
.count("\\abc_carry") && !abc_carry_modules
.count(box_module
)) {
311 RTLIL::Wire
* carry_in
= nullptr, *carry_out
= nullptr;
312 RTLIL::Wire
* last_in
= nullptr, *last_out
= nullptr;
313 for (const auto &port_name
: box_module
->ports
) {
314 RTLIL::Wire
* w
= box_module
->wire(port_name
);
317 if (w
->attributes
.count("\\abc_carry_in")) {
318 log_assert(!carry_in
);
321 log_assert(!last_in
|| last_in
->port_id
< w
->port_id
);
324 if (w
->port_output
) {
325 if (w
->attributes
.count("\\abc_carry_out")) {
326 log_assert(!carry_out
);
329 log_assert(!last_out
|| last_out
->port_id
< w
->port_id
);
336 std::swap(box_module
->ports
[carry_in
->port_id
-1], box_module
->ports
[last_in
->port_id
-1]);
337 std::swap(carry_in
->port_id
, last_in
->port_id
);
340 log_assert(last_out
);
341 std::swap(box_module
->ports
[carry_out
->port_id
-1], box_module
->ports
[last_out
->port_id
-1]);
342 std::swap(carry_out
->port_id
, last_out
->port_id
);
346 // Fully pad all unused input connections of this box cell with S0
347 // Fully pad all undriven output connections of this box cell with anonymous wires
348 // NB: Assume box_module->ports are sorted alphabetically
349 // (as RTLIL::Module::fixup_ports() would do)
350 for (const auto &port_name
: box_module
->ports
) {
351 RTLIL::Wire
* w
= box_module
->wire(port_name
);
353 auto it
= cell
->connections_
.find(port_name
);
356 if (it
!= cell
->connections_
.end()) {
357 if (GetSize(it
->second
) < GetSize(w
))
358 it
->second
.append(RTLIL::SigSpec(RTLIL::S0
, GetSize(w
)-GetSize(it
->second
)));
362 rhs
= RTLIL::SigSpec(RTLIL::S0
, GetSize(w
));
363 cell
->setPort(port_name
, rhs
);
367 for (auto b
: rhs
.bits()) {
368 SigBit I
= sigmap(b
);
373 alias_map
[b
] = RTLIL::S0
;
377 co_bits
.emplace_back(b
, cell
, port_name
, offset
++, 0);
378 unused_bits
.erase(b
);
381 if (w
->port_output
) {
383 auto it
= cell
->connections_
.find(w
->name
);
384 if (it
!= cell
->connections_
.end()) {
385 if (GetSize(it
->second
) < GetSize(w
))
386 it
->second
.append(module
->addWire(NEW_ID
, GetSize(w
)-GetSize(it
->second
)));
390 rhs
= module
->addWire(NEW_ID
, GetSize(w
));
391 cell
->setPort(port_name
, rhs
);
395 for (const auto &b
: rhs
.bits()) {
396 ci_bits
.emplace_back(b
, cell
, port_name
, offset
++);
397 SigBit O
= sigmap(b
);
400 undriven_bits
.erase(O
);
402 auto jt
= input_bits
.find(b
);
403 if (jt
!= input_bits
.end()) {
404 log_assert(b
.wire
->attributes
.count("\\keep"));
410 box_list
.emplace_back(cell
);
413 // TODO: Free memory from toposort, bit_drivers, bit_users
416 for (auto bit
: input_bits
) {
417 if (!output_bits
.count(bit
))
419 RTLIL::Wire
*wire
= bit
.wire
;
420 // If encountering an inout port, or a keep-ed wire, then create a new wire
421 // with $inout.out suffix, make it a PO driven by the existing inout, and
422 // inherit existing inout's drivers
423 if ((wire
->port_input
&& wire
->port_output
&& !undriven_bits
.count(bit
))
424 || wire
->attributes
.count("\\keep")) {
425 RTLIL::IdString wire_name
= wire
->name
.str() + "$inout.out";
426 RTLIL::Wire
*new_wire
= module
->wire(wire_name
);
428 new_wire
= module
->addWire(wire_name
, GetSize(wire
));
429 SigBit
new_bit(new_wire
, bit
.offset
);
430 module
->connect(new_bit
, bit
);
431 if (not_map
.count(bit
))
432 not_map
[new_bit
] = not_map
.at(bit
);
433 else if (and_map
.count(bit
)) {
434 //and_map[new_bit] = and_map.at(bit); // Breaks gcc-4.8
435 and_map
.insert(std::make_pair(new_bit
, and_map
.at(bit
)));
437 else if (alias_map
.count(bit
))
438 alias_map
[new_bit
] = alias_map
.at(bit
);
440 alias_map
[new_bit
] = bit
;
441 output_bits
.erase(bit
);
442 output_bits
.insert(new_bit
);
446 for (auto bit
: unused_bits
)
447 undriven_bits
.erase(bit
);
449 if (!undriven_bits
.empty() && !holes_mode
) {
450 undriven_bits
.sort();
451 for (auto bit
: undriven_bits
) {
452 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module
), log_signal(bit
));
453 input_bits
.insert(bit
);
455 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits
), log_id(module
));
459 struct sort_by_port_id
{
460 bool operator()(const RTLIL::SigBit
& a
, const RTLIL::SigBit
& b
) const {
461 return a
.wire
->port_id
< b
.wire
->port_id
;
464 input_bits
.sort(sort_by_port_id());
465 output_bits
.sort(sort_by_port_id());
475 aig_map
[State::S0
] = 0;
476 aig_map
[State::S1
] = 1;
478 for (auto bit
: input_bits
) {
480 log_assert(!aig_map
.count(bit
));
481 aig_map
[bit
] = 2*aig_m
;
484 for (auto &c
: ci_bits
) {
485 RTLIL::SigBit bit
= std::get
<0>(c
);
487 aig_map
[bit
] = 2*aig_m
;
490 for (auto &c
: co_bits
) {
491 RTLIL::SigBit bit
= std::get
<0>(c
);
492 std::get
<4>(c
) = ordered_outputs
[bit
] = aig_o
++;
493 aig_outputs
.push_back(bit2aig(bit
));
496 for (auto bit
: output_bits
) {
497 ordered_outputs
[bit
] = aig_o
++;
498 aig_outputs
.push_back(bit2aig(bit
));
501 if (output_bits
.empty()) {
503 aig_outputs
.push_back(0);
508 void write_aiger(std::ostream
&f
, bool ascii_mode
)
511 int aig_obcj
= aig_obc
;
512 int aig_obcjf
= aig_obcj
;
514 log_assert(aig_m
== aig_i
+ aig_l
+ aig_a
);
515 log_assert(aig_obcjf
== GetSize(aig_outputs
));
517 f
<< stringf("%s %d %d %d %d %d", ascii_mode
? "aag" : "aig", aig_m
, aig_i
, aig_l
, aig_o
, aig_a
);
522 for (int i
= 0; i
< aig_i
; i
++)
523 f
<< stringf("%d\n", 2*i
+2);
525 for (int i
= 0; i
< aig_obc
; i
++)
526 f
<< stringf("%d\n", aig_outputs
.at(i
));
528 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
531 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
532 f
<< stringf("%d\n", aig_outputs
.at(i
));
534 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
535 f
<< stringf("%d\n", aig_outputs
.at(i
));
537 for (int i
= 0; i
< aig_a
; i
++)
538 f
<< stringf("%d %d %d\n", 2*(aig_i
+aig_l
+i
)+2, aig_gates
.at(i
).first
, aig_gates
.at(i
).second
);
542 for (int i
= 0; i
< aig_obc
; i
++)
543 f
<< stringf("%d\n", aig_outputs
.at(i
));
545 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
548 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
549 f
<< stringf("%d\n", aig_outputs
.at(i
));
551 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
552 f
<< stringf("%d\n", aig_outputs
.at(i
));
554 for (int i
= 0; i
< aig_a
; i
++) {
555 int lhs
= 2*(aig_i
+aig_l
+i
)+2;
556 int rhs0
= aig_gates
.at(i
).first
;
557 int rhs1
= aig_gates
.at(i
).second
;
558 int delta0
= lhs
- rhs0
;
559 int delta1
= rhs0
- rhs1
;
560 aiger_encode(f
, delta0
);
561 aiger_encode(f
, delta1
);
567 if (!box_list
.empty()) {
568 auto write_buffer
= [](std::stringstream
&buffer
, int i32
) {
569 int32_t i32_be
= to_big_endian(i32
);
570 buffer
.write(reinterpret_cast<const char*>(&i32_be
), sizeof(i32_be
));
573 std::stringstream h_buffer
;
574 auto write_h_buffer
= std::bind(write_buffer
, std::ref(h_buffer
), std::placeholders::_1
);
576 log_debug("ciNum = %zu\n", input_bits
.size() + ci_bits
.size());
577 write_h_buffer(input_bits
.size() + ci_bits
.size());
578 log_debug("coNum = %zu\n", output_bits
.size() + co_bits
.size());
579 write_h_buffer(output_bits
.size() + co_bits
.size());
580 log_debug("piNum = %zu\n", input_bits
.size());
581 write_h_buffer(input_bits
.size());
582 log_debug("poNum = %zu\n", output_bits
.size());
583 write_h_buffer(output_bits
.size());
584 log_debug("boxNum = %zu\n", box_list
.size());
585 write_h_buffer(box_list
.size());
587 RTLIL::Module
*holes_module
= nullptr;
588 holes_module
= module
->design
->addModule("$__holes__");
589 log_assert(holes_module
);
593 for (auto cell
: box_list
) {
594 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
595 int box_inputs
= 0, box_outputs
= 0;
596 Cell
*holes_cell
= nullptr;
597 if (box_module
->get_bool_attribute("\\whitebox")) {
598 holes_cell
= holes_module
->addCell(cell
->name
, cell
->type
);
599 holes_cell
->parameters
= cell
->parameters
;
602 // NB: Assume box_module->ports are sorted alphabetically
603 // (as RTLIL::Module::fixup_ports() would do)
604 for (const auto &port_name
: box_module
->ports
) {
605 RTLIL::Wire
*w
= box_module
->wire(port_name
);
607 RTLIL::Wire
*holes_wire
;
608 RTLIL::SigSpec port_wire
;
610 for (int i
= 0; i
< GetSize(w
); i
++) {
612 holes_wire
= holes_module
->wire(stringf("\\i%d", box_inputs
));
614 holes_wire
= holes_module
->addWire(stringf("\\i%d", box_inputs
));
615 holes_wire
->port_input
= true;
616 holes_wire
->port_id
= port_id
++;
617 holes_module
->ports
.push_back(holes_wire
->name
);
620 port_wire
.append(holes_wire
);
622 if (!port_wire
.empty())
623 holes_cell
->setPort(w
->name
, port_wire
);
625 if (w
->port_output
) {
626 box_outputs
+= GetSize(w
);
627 for (int i
= 0; i
< GetSize(w
); i
++) {
629 holes_wire
= holes_module
->addWire(stringf("%s.%s", cell
->name
.c_str(), w
->name
.c_str()));
631 holes_wire
= holes_module
->addWire(stringf("%s.%s[%d]", cell
->name
.c_str(), w
->name
.c_str(), i
));
632 holes_wire
->port_output
= true;
633 holes_wire
->port_id
= port_id
++;
634 holes_module
->ports
.push_back(holes_wire
->name
);
636 port_wire
.append(holes_wire
);
638 holes_module
->connect(holes_wire
, RTLIL::S0
);
640 if (!port_wire
.empty())
641 holes_cell
->setPort(w
->name
, port_wire
);
645 write_h_buffer(box_inputs
);
646 write_h_buffer(box_outputs
);
647 write_h_buffer(box_module
->attributes
.at("\\abc_box_id").as_int());
648 write_h_buffer(box_count
++);
652 std::string buffer_str
= h_buffer
.str();
653 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
654 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
655 f
.write(buffer_str
.data(), buffer_str
.size());
657 std::stringstream r_buffer
;
658 auto write_r_buffer
= std::bind(write_buffer
, std::ref(r_buffer
), std::placeholders::_1
);
662 buffer_str
= r_buffer
.str();
663 buffer_size_be
= to_big_endian(buffer_str
.size());
664 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
665 f
.write(buffer_str
.data(), buffer_str
.size());
670 // NB: fixup_ports() will sort ports by name
671 //holes_module->fixup_ports();
672 holes_module
->check();
674 holes_module
->design
->selection_stack
.emplace_back(false);
675 RTLIL::Selection
& sel
= holes_module
->design
->selection_stack
.back();
676 sel
.select(holes_module
);
678 // TODO: Should not need to opt_merge if we only instantiate
679 // each box type once...
680 Pass::call(holes_module
->design
, "opt_merge -share_all");
682 Pass::call(holes_module
->design
, "flatten -wb");
684 // TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
685 // instead of per write_xaiger call
686 Pass::call(holes_module
->design
, "techmap");
687 Pass::call(holes_module
->design
, "aigmap");
688 for (auto cell
: holes_module
->cells())
689 if (!cell
->type
.in("$_NOT_", "$_AND_"))
690 log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
692 Pass::call(holes_module
->design
, "clean -purge");
694 std::stringstream a_buffer
;
695 XAigerWriter
writer(holes_module
, true /* holes_mode */);
696 writer
.write_aiger(a_buffer
, false /*ascii_mode*/);
698 holes_module
->design
->selection_stack
.pop_back();
701 std::string buffer_str
= a_buffer
.str();
702 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
703 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
704 f
.write(buffer_str
.data(), buffer_str
.size());
705 holes_module
->design
->remove(holes_module
);
711 f
<< stringf("Generated by %s\n", yosys_version_str
);
714 void write_map(std::ostream
&f
, bool verbose_map
)
716 dict
<int, string
> input_lines
;
717 dict
<int, string
> output_lines
;
718 dict
<int, string
> wire_lines
;
720 for (auto wire
: module
->wires())
722 //if (!verbose_map && wire->name[0] == '$')
725 SigSpec sig
= sigmap(wire
);
727 for (int i
= 0; i
< GetSize(wire
); i
++)
729 RTLIL::SigBit
b(wire
, i
);
730 if (input_bits
.count(b
)) {
731 int a
= aig_map
.at(b
);
732 log_assert((a
& 1) == 0);
733 input_lines
[a
] += stringf("input %d %d %s\n", (a
>> 1)-1, i
, log_id(wire
));
736 if (output_bits
.count(b
)) {
737 int o
= ordered_outputs
.at(b
);
738 output_lines
[o
] += stringf("output %lu %d %s\n", o
- co_bits
.size(), i
, log_id(wire
));
743 if (aig_map
.count(sig
[i
]) == 0)
746 int a
= aig_map
.at(sig
[i
]);
747 wire_lines
[a
] += stringf("wire %d %d %s\n", a
, i
, log_id(wire
));
753 for (auto &it
: input_lines
)
755 log_assert(input_lines
.size() == input_bits
.size());
758 for (auto cell
: box_list
)
759 f
<< stringf("box %d %d %s\n", box_count
++, 0, log_id(cell
->name
));
762 for (auto &it
: output_lines
)
764 log_assert(output_lines
.size() == output_bits
.size());
765 if (omode
&& output_bits
.empty())
766 f
<< "output " << output_lines
.size() << " 0 $__dummy__\n";
769 for (auto &it
: wire_lines
)
774 struct XAigerBackend
: public Backend
{
775 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
776 void help() YS_OVERRIDE
778 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
780 log(" write_xaiger [options] [filename]\n");
782 log("Write the current design to an XAIGER file. The design must be flattened and\n");
783 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
786 log(" write ASCII version of AIGER format\n");
788 log(" -map <filename>\n");
789 log(" write an extra file with port and latch symbols\n");
791 log(" -vmap <filename>\n");
792 log(" like -map, but more verbose\n");
795 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
797 bool ascii_mode
= false;
798 bool verbose_map
= false;
799 std::string map_filename
;
801 log_header(design
, "Executing XAIGER backend.\n");
804 for (argidx
= 1; argidx
< args
.size(); argidx
++)
806 if (args
[argidx
] == "-ascii") {
810 if (map_filename
.empty() && args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
811 map_filename
= args
[++argidx
];
814 if (map_filename
.empty() && args
[argidx
] == "-vmap" && argidx
+1 < args
.size()) {
815 map_filename
= args
[++argidx
];
821 extra_args(f
, filename
, args
, argidx
);
823 Module
*top_module
= design
->top_module();
825 if (top_module
== nullptr)
826 log_error("Can't find top module in current design!\n");
828 XAigerWriter
writer(top_module
);
829 writer
.write_aiger(*f
, ascii_mode
);
831 if (!map_filename
.empty()) {
833 mapf
.open(map_filename
.c_str(), std::ofstream::trunc
);
835 log_error("Can't open file `%s' for writing: %s\n", map_filename
.c_str(), strerror(errno
));
836 writer
.write_map(mapf
, verbose_map
);
841 PRIVATE_NAMESPACE_END