backends/aiger/xaiger.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // https://stackoverflow.com/a/46137633
  22 #ifdef _MSC_VER
  23 #include <stdlib.h>
  24 #define bswap32 _byteswap_ulong
  25 #elif defined(__APPLE__)
  26 #include <libkern/OSByteOrder.h>
  27 #define bswap32 OSSwapInt32
  28 #elif defined(__GNUC__)
  29 #define bswap32 __builtin_bswap32
  30 #else
  31 #include <cstdint>
  32 inline static uint32_t bswap32(uint32_t x)
  33 {
  34         // https://stackoverflow.com/a/27796212
  35         register uint32_t value = number_to_be_reversed;
  36         uint8_t lolo = (value >> 0) & 0xFF;
  37         uint8_t lohi = (value >> 8) & 0xFF;
  38         uint8_t hilo = (value >> 16) & 0xFF;
  39         uint8_t hihi = (value >> 24) & 0xFF;
  40         return (hihi << 24)
  41                 | (hilo << 16)
  42                 | (lohi << 8)
  43                 | (lolo << 0);
  44 }
  45 #endif
  46
  47 #include "kernel/yosys.h"
  48 #include "kernel/sigtools.h"
  49 #include "kernel/utils.h"
  50
  51 USING_YOSYS_NAMESPACE
  52 PRIVATE_NAMESPACE_BEGIN
  53
  54 inline int32_t to_big_endian(int32_t i32) {
  55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
  56         return bswap32(i32);
  57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  58         return i32;
  59 #else
  60 #error "Unknown endianness"
  61 #endif
  62 }
  63
  64 void aiger_encode(std::ostream &f, int x)
  65 {
  66         log_assert(x >= 0);
  67
  68         while (x & ~0x7f) {
  69                 f.put((x & 0x7f) | 0x80);
  70                 x = x >> 7;
  71         }
  72
  73         f.put(x);
  74 }
  75
  76 struct XAigerWriter
  77 {
  78         Module *module;
  79         SigMap sigmap;
  80
  81         pool<SigBit> input_bits, output_bits;
  82         dict<SigBit, SigBit> not_map, alias_map;
  83         dict<SigBit, pair<SigBit, SigBit>> and_map;
  84         vector<SigBit> ci_bits, co_bits;
  85         dict<SigBit, Cell*> ff_bits;
  86         dict<SigBit, float> arrival_times;
  87
  88         vector<pair<int, int>> aig_gates;
  89         vector<int> aig_outputs;
  90         int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
  91
  92         dict<SigBit, int> aig_map;
  93         dict<SigBit, int> ordered_outputs;
  94
  95         vector<Cell*> box_list;
  96
  97         int mkgate(int a0, int a1)
  98         {
  99                 aig_m++, aig_a++;
 100                 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
 101                 return 2*aig_m;
 102         }
 103
 104         int bit2aig(SigBit bit)
 105         {
 106                 auto it = aig_map.find(bit);
 107                 if (it != aig_map.end()) {
 108                         log_assert(it->second >= 0);
 109                         return it->second;
 110                 }
 111
 112                 // NB: Cannot use iterator returned from aig_map.insert()
 113                 //     since this function is called recursively
 114
 115                 int a = -1;
 116                 if (not_map.count(bit)) {
 117                         a = bit2aig(not_map.at(bit)) ^ 1;
 118                 } else
 119                 if (and_map.count(bit)) {
 120                         auto args = and_map.at(bit);
 121                         int a0 = bit2aig(args.first);
 122                         int a1 = bit2aig(args.second);
 123                         a = mkgate(a0, a1);
 124                 } else
 125                 if (alias_map.count(bit)) {
 126                         a = bit2aig(alias_map.at(bit));
 127                 }
 128
 129                 if (bit == State::Sx || bit == State::Sz) {
 130                         log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
 131                         a = aig_map.at(State::S0);
 132                 }
 133
 134                 log_assert(a >= 0);
 135                 aig_map[bit] = a;
 136                 return a;
 137         }
 138
 139         XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
 140         {
 141                 pool<SigBit> undriven_bits;
 142                 pool<SigBit> unused_bits;
 143
 144                 // promote public wires
 145                 for (auto wire : module->wires())
 146                         if (wire->name[0] == '\\')
 147                                 sigmap.add(wire);
 148
 149                 // promote input wires
 150                 for (auto wire : module->wires())
 151                         if (wire->port_input)
 152                                 sigmap.add(wire);
 153
 154                 // promote keep wires
 155                 for (auto wire : module->wires())
 156                         if (wire->get_bool_attribute(ID::keep))
 157                                 sigmap.add(wire);
 158
 159                 for (auto wire : module->wires())
 160                         for (int i = 0; i < GetSize(wire); i++)
 161                         {
 162                                 SigBit wirebit(wire, i);
 163                                 SigBit bit = sigmap(wirebit);
 164
 165                                 if (bit.wire == nullptr) {
 166                                         if (wire->port_output) {
 167                                                 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
 168                                                 output_bits.insert(wirebit);
 169                                         }
 170                                         continue;
 171                                 }
 172
 173                                 undriven_bits.insert(bit);
 174                                 unused_bits.insert(bit);
 175
 176                                 bool keep = wire->get_bool_attribute(ID::keep);
 177                                 if (wire->port_input || keep)
 178                                         input_bits.insert(bit);
 179
 180                                 if (wire->port_output || keep) {
 181                                         if (bit != wirebit)
 182                                                 alias_map[wirebit] = bit;
 183                                         output_bits.insert(wirebit);
 184                                 }
 185                         }
 186
 187                 dict<IdString,dict<IdString,int>> arrival_cache;
 188                 for (auto cell : module->cells()) {
 189                         if (cell->type == "$_NOT_")
 190                         {
 191                                 SigBit A = sigmap(cell->getPort("\\A").as_bit());
 192                                 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
 193                                 unused_bits.erase(A);
 194                                 undriven_bits.erase(Y);
 195                                 not_map[Y] = A;
 196                                 continue;
 197                         }
 198
 199                         if (cell->type == "$_AND_")
 200                         {
 201                                 SigBit A = sigmap(cell->getPort("\\A").as_bit());
 202                                 SigBit B = sigmap(cell->getPort("\\B").as_bit());
 203                                 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
 204                                 unused_bits.erase(A);
 205                                 unused_bits.erase(B);
 206                                 undriven_bits.erase(Y);
 207                                 and_map[Y] = make_pair(A, B);
 208                                 continue;
 209                         }
 210
 211                         if (cell->type == "$__ABC9_FF_" &&
 212                                         // The presence of an abc9_mergeability attribute indicates
 213                                         //   that we do want to pass this flop to ABC
 214                                         cell->attributes.count("\\abc9_mergeability"))
 215                         {
 216                                 SigBit D = sigmap(cell->getPort("\\D").as_bit());
 217                                 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
 218                                 unused_bits.erase(D);
 219                                 undriven_bits.erase(Q);
 220                                 alias_map[Q] = D;
 221                                 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
 222                                 log_assert(r.second);
 223                                 continue;
 224                         }
 225
 226                         RTLIL::Module* inst_module = module->design->module(cell->type);
 227                         if (inst_module) {
 228                                 auto it = cell->attributes.find("\\abc9_box_seq");
 229                                 if (it != cell->attributes.end()) {
 230                                         int abc9_box_seq = it->second.as_int();
 231                                         if (GetSize(box_list) <= abc9_box_seq)
 232                                                 box_list.resize(abc9_box_seq+1);
 233                                         box_list[abc9_box_seq] = cell;
 234                                         // Only flop boxes may have arrival times
 235                                         if (!inst_module->get_bool_attribute("\\abc9_flop"))
 236                                                 continue;
 237                                 }
 238
 239                                 auto &cell_arrivals = arrival_cache[cell->type];
 240                                 for (const auto &conn : cell->connections()) {
 241                                         auto r = cell_arrivals.insert(conn.first);
 242                                         auto &arrival = r.first->second;
 243                                         if (r.second) {
 244                                                 auto port_wire = inst_module->wire(conn.first);
 245                                                 if (port_wire->port_output) {
 246                                                         auto it = port_wire->attributes.find("\\abc9_arrival");
 247                                                         if (it != port_wire->attributes.end()) {
 248                                                                 if (it->second.flags != 0)
 249                                                                         log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
 250                                                                 arrival = it->second.as_int();
 251                                                         }
 252                                                 }
 253                                         }
 254                                         if (arrival)
 255                                                 for (auto bit : sigmap(conn.second))
 256                                                         arrival_times[bit] = arrival;
 257                                 }
 258                         }
 259
 260                         bool cell_known = inst_module || cell->known();
 261                         for (const auto &c : cell->connections()) {
 262                                 if (c.second.is_fully_const()) continue;
 263                                 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
 264                                 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
 265                                 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
 266                                 if (!is_input && !is_output)
 267                                         log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
 268
 269                                 if (is_input)
 270                                         for (auto b : c.second) {
 271                                                 Wire *w = b.wire;
 272                                                 if (!w) continue;
 273                                                 if (!w->port_output || !cell_known) {
 274                                                         SigBit I = sigmap(b);
 275                                                         if (I != b)
 276                                                                 alias_map[b] = I;
 277                                                         output_bits.insert(b);
 278                                                 }
 279                                         }
 280                         }
 281
 282                         //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
 283                 }
 284
 285                 dict<IdString, std::vector<IdString>> box_ports;
 286                 for (auto cell : box_list) {
 287                         log_assert(cell);
 288
 289                         RTLIL::Module* box_module = module->design->module(cell->type);
 290                         log_assert(box_module);
 291                         log_assert(box_module->attributes.count("\\abc9_box_id"));
 292
 293                         auto r = box_ports.insert(cell->type);
 294                         if (r.second) {
 295                                 // Make carry in the last PI, and carry out the last PO
 296                                 //   since ABC requires it this way
 297                                 IdString carry_in, carry_out;
 298                                 for (const auto &port_name : box_module->ports) {
 299                                         auto w = box_module->wire(port_name);
 300                                         log_assert(w);
 301                                         if (w->get_bool_attribute("\\abc9_carry")) {
 302                                                 if (w->port_input) {
 303                                                         if (carry_in != IdString())
 304                                                                 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
 305                                                         carry_in = port_name;
 306                                                 }
 307                                                 if (w->port_output) {
 308                                                         if (carry_out != IdString())
 309                                                                 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
 310                                                         carry_out = port_name;
 311                                                 }
 312                                         }
 313                                         else
 314                                                 r.first->second.push_back(port_name);
 315                                 }
 316
 317                                 if (carry_in != IdString() && carry_out == IdString())
 318                                         log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
 319                                 if (carry_in == IdString() && carry_out != IdString())
 320                                         log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
 321                                 if (carry_in != IdString()) {
 322                                         r.first->second.push_back(carry_in);
 323                                         r.first->second.push_back(carry_out);
 324                                 }
 325                         }
 326
 327                         // Fully pad all unused input connections of this box cell with S0
 328                         // Fully pad all undriven output connections of this box cell with anonymous wires
 329                         for (auto port_name : r.first->second) {
 330                                 auto w = box_module->wire(port_name);
 331                                 log_assert(w);
 332                                 auto rhs = cell->getPort(port_name);
 333                                 if (w->port_input)
 334                                         for (auto b : rhs) {
 335                                                 SigBit I = sigmap(b);
 336                                                 if (b == RTLIL::Sx)
 337                                                         b = State::S0;
 338                                                 else if (I != b) {
 339                                                         if (I == RTLIL::Sx)
 340                                                                 alias_map[b] = State::S0;
 341                                                         else
 342                                                                 alias_map[b] = I;
 343                                                 }
 344                                                 co_bits.emplace_back(b);
 345                                                 unused_bits.erase(I);
 346                                         }
 347                                 if (w->port_output)
 348                                         for (const auto &b : rhs.bits()) {
 349                                                 SigBit O = sigmap(b);
 350                                                 if (O != b)
 351                                                         alias_map[O] = b;
 352                                                 ci_bits.emplace_back(b);
 353                                                 undriven_bits.erase(O);
 354                                         }
 355                         }
 356
 357                         // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
 358                         if (box_module->get_bool_attribute("\\abc9_flop")) {
 359                                 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
 360                                 if (rhs.empty())
 361                                         log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
 362
 363                                 for (auto b : rhs) {
 364                                         SigBit I = sigmap(b);
 365                                         if (b == RTLIL::Sx)
 366                                                 b = State::S0;
 367                                         else if (I != b) {
 368                                                 if (I == RTLIL::Sx)
 369                                                         alias_map[b] = State::S0;
 370                                                 else
 371                                                         alias_map[b] = I;
 372                                         }
 373                                         co_bits.emplace_back(b);
 374                                         unused_bits.erase(I);
 375                                 }
 376                         }
 377                 }
 378
 379                 for (auto bit : input_bits)
 380                         undriven_bits.erase(bit);
 381                 for (auto bit : output_bits)
 382                         unused_bits.erase(sigmap(bit));
 383                 for (auto bit : unused_bits)
 384                         undriven_bits.erase(bit);
 385
 386                 // Make all undriven bits a primary input
 387                 for (auto bit : undriven_bits) {
 388                         input_bits.insert(bit);
 389                         undriven_bits.erase(bit);
 390                 }
 391
 392                 if (holes_mode) {
 393                         struct sort_by_port_id {
 394                                 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
 395                                         return a.wire->port_id < b.wire->port_id ||
 396                                             (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
 397                                 }
 398                         };
 399                         input_bits.sort(sort_by_port_id());
 400                         output_bits.sort(sort_by_port_id());
 401                 }
 402
 403                 aig_map[State::S0] = 0;
 404                 aig_map[State::S1] = 1;
 405
 406                 for (const auto &bit : input_bits) {
 407                         aig_m++, aig_i++;
 408                         log_assert(!aig_map.count(bit));
 409                         aig_map[bit] = 2*aig_m;
 410                 }
 411
 412                 for (const auto &i : ff_bits) {
 413                         const Cell *cell = i.second;
 414                         const SigBit &q = sigmap(cell->getPort("\\Q"));
 415                         aig_m++, aig_i++;
 416                         log_assert(!aig_map.count(q));
 417                         aig_map[q] = 2*aig_m;
 418                 }
 419
 420                 for (auto &bit : ci_bits) {
 421                         aig_m++, aig_i++;
 422                         log_assert(!aig_map.count(bit));
 423                         aig_map[bit] = 2*aig_m;
 424                 }
 425
 426                 for (auto bit : co_bits) {
 427                         ordered_outputs[bit] = aig_o++;
 428                         aig_outputs.push_back(bit2aig(bit));
 429                 }
 430
 431                 for (const auto &bit : output_bits) {
 432                         ordered_outputs[bit] = aig_o++;
 433                         int aig;
 434                         if (input_bits.count(bit)) {
 435                                 auto it = aig_map.find(bit);
 436                                 int input_aig = it->second;
 437                                 aig_map.erase(it);
 438                                 aig = bit2aig(bit);
 439                                 aig_map.at(bit) = input_aig;
 440                         }
 441                         else
 442                                 aig = bit2aig(bit);
 443                         aig_outputs.push_back(aig);
 444                 }
 445
 446                 for (auto &i : ff_bits) {
 447                         const SigBit &d = i.first;
 448                         aig_o++;
 449                         aig_outputs.push_back(aig_map.at(d));
 450                 }
 451         }
 452
 453         void write_aiger(std::ostream &f, bool ascii_mode)
 454         {
 455                 int aig_obc = aig_o;
 456                 int aig_obcj = aig_obc;
 457                 int aig_obcjf = aig_obcj;
 458
 459                 log_assert(aig_m == aig_i + aig_l + aig_a);
 460                 log_assert(aig_obcjf == GetSize(aig_outputs));
 461
 462                 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
 463                 f << stringf("\n");
 464
 465                 if (ascii_mode)
 466                 {
 467                         for (int i = 0; i < aig_i; i++)
 468                                 f << stringf("%d\n", 2*i+2);
 469
 470                         for (int i = 0; i < aig_obc; i++)
 471                                 f << stringf("%d\n", aig_outputs.at(i));
 472
 473                         for (int i = aig_obc; i < aig_obcj; i++)
 474                                 f << stringf("1\n");
 475
 476                         for (int i = aig_obc; i < aig_obcj; i++)
 477                                 f << stringf("%d\n", aig_outputs.at(i));
 478
 479                         for (int i = aig_obcj; i < aig_obcjf; i++)
 480                                 f << stringf("%d\n", aig_outputs.at(i));
 481
 482                         for (int i = 0; i < aig_a; i++)
 483                                 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
 484                 }
 485                 else
 486                 {
 487                         for (int i = 0; i < aig_obc; i++)
 488                                 f << stringf("%d\n", aig_outputs.at(i));
 489
 490                         for (int i = aig_obc; i < aig_obcj; i++)
 491                                 f << stringf("1\n");
 492
 493                         for (int i = aig_obc; i < aig_obcj; i++)
 494                                 f << stringf("%d\n", aig_outputs.at(i));
 495
 496                         for (int i = aig_obcj; i < aig_obcjf; i++)
 497                                 f << stringf("%d\n", aig_outputs.at(i));
 498
 499                         for (int i = 0; i < aig_a; i++) {
 500                                 int lhs = 2*(aig_i+aig_l+i)+2;
 501                                 int rhs0 = aig_gates.at(i).first;
 502                                 int rhs1 = aig_gates.at(i).second;
 503                                 int delta0 = lhs - rhs0;
 504                                 int delta1 = rhs0 - rhs1;
 505                                 aiger_encode(f, delta0);
 506                                 aiger_encode(f, delta1);
 507                         }
 508                 }
 509
 510                 f << "c";
 511
 512                 auto write_buffer = [](std::stringstream &buffer, int i32) {
 513                         int32_t i32_be = to_big_endian(i32);
 514                         buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
 515                 };
 516                 std::stringstream h_buffer;
 517                 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
 518                 write_h_buffer(1);
 519                 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
 520                 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
 521                 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
 522                 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
 523                 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
 524                 write_h_buffer(input_bits.size() + ff_bits.size());
 525                 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
 526                 write_h_buffer(output_bits.size() + ff_bits.size());
 527                 log_debug("boxNum = %d\n", GetSize(box_list));
 528                 write_h_buffer(box_list.size());
 529
 530                 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
 531                         buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
 532                 };
 533                 std::stringstream i_buffer;
 534                 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
 535                 for (auto bit : input_bits)
 536                         write_i_buffer(arrival_times.at(bit, 0));
 537                 //std::stringstream o_buffer;
 538                 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
 539                 //for (auto bit : output_bits)
 540                 //      write_o_buffer(0);
 541
 542                 if (!box_list.empty() || !ff_bits.empty()) {
 543                         RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
 544                         log_assert(holes_module);
 545
 546                         dict<IdString, std::tuple<int,int,int>> cell_cache;
 547
 548                         int box_count = 0;
 549                         for (auto cell : box_list) {
 550                                 log_assert(cell);
 551
 552                                 RTLIL::Module* box_module = module->design->module(cell->type);
 553                                 log_assert(box_module);
 554
 555                                 auto r = cell_cache.insert(cell->type);
 556                                 auto &v = r.first->second;
 557                                 if (r.second) {
 558                                         int box_inputs = 0, box_outputs = 0;
 559                                         for (auto port_name : box_module->ports) {
 560                                                 RTLIL::Wire *w = box_module->wire(port_name);
 561                                                 log_assert(w);
 562                                                 if (w->port_input)
 563                                                         box_inputs += GetSize(w);
 564                                                 if (w->port_output)
 565                                                         box_outputs += GetSize(w);
 566                                         }
 567
 568                                         // For flops only, create an extra 1-bit input that drives a new wire
 569                                         //   called "<cell>.abc9_ff.Q" that is used below
 570                                         if (box_module->get_bool_attribute("\\abc9_flop"))
 571                                             box_inputs++;
 572
 573                                         std::get<0>(v) = box_inputs;
 574                                         std::get<1>(v) = box_outputs;
 575                                         std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
 576                                 }
 577
 578                                 write_h_buffer(std::get<0>(v));
 579                                 write_h_buffer(std::get<1>(v));
 580                                 write_h_buffer(std::get<2>(v));
 581                                 write_h_buffer(box_count++);
 582                         }
 583
 584                         std::stringstream r_buffer;
 585                         auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
 586                         log_debug("flopNum = %d\n", GetSize(ff_bits));
 587                         write_r_buffer(ff_bits.size());
 588
 589                         std::stringstream s_buffer;
 590                         auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
 591                         write_s_buffer(ff_bits.size());
 592
 593                         for (const auto &i : ff_bits) {
 594                                 const SigBit &d = i.first;
 595                                 const Cell *cell = i.second;
 596
 597                                 int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
 598                                 log_assert(mergeability > 0);
 599                                 write_r_buffer(mergeability);
 600
 601                                 Const init = cell->attributes.at(ID(abc9_init));
 602                                 log_assert(GetSize(init) == 1);
 603                                 if (init == State::S1)
 604                                         write_s_buffer(1);
 605                                 else if (init == State::S0)
 606                                         write_s_buffer(0);
 607                                 else {
 608                                         log_assert(init == State::Sx);
 609                                         write_s_buffer(0);
 610                                 }
 611
 612                                 write_i_buffer(arrival_times.at(d, 0));
 613                                 //write_o_buffer(0);
 614                         }
 615
 616                         f << "r";
 617                         std::string buffer_str = r_buffer.str();
 618                         int32_t buffer_size_be = to_big_endian(buffer_str.size());
 619                         f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 620                         f.write(buffer_str.data(), buffer_str.size());
 621
 622                         f << "s";
 623                         buffer_str = s_buffer.str();
 624                         buffer_size_be = to_big_endian(buffer_str.size());
 625                         f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 626                         f.write(buffer_str.data(), buffer_str.size());
 627
 628                         if (holes_module) {
 629                                 std::stringstream a_buffer;
 630                                 XAigerWriter writer(holes_module, true /* holes_mode */);
 631                                 writer.write_aiger(a_buffer, false /*ascii_mode*/);
 632
 633                                 f << "a";
 634                                 std::string buffer_str = a_buffer.str();
 635                                 int32_t buffer_size_be = to_big_endian(buffer_str.size());
 636                                 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 637                                 f.write(buffer_str.data(), buffer_str.size());
 638                         }
 639                 }
 640
 641                 f << "h";
 642                 std::string buffer_str = h_buffer.str();
 643                 int32_t buffer_size_be = to_big_endian(buffer_str.size());
 644                 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 645                 f.write(buffer_str.data(), buffer_str.size());
 646
 647                 f << "i";
 648                 buffer_str = i_buffer.str();
 649                 buffer_size_be = to_big_endian(buffer_str.size());
 650                 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 651                 f.write(buffer_str.data(), buffer_str.size());
 652                 //f << "o";
 653                 //buffer_str = o_buffer.str();
 654                 //buffer_size_be = to_big_endian(buffer_str.size());
 655                 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 656                 //f.write(buffer_str.data(), buffer_str.size());
 657
 658                 f << stringf("Generated by %s\n", yosys_version_str);
 659
 660                 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
 661                 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
 662                 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
 663                 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
 664         }
 665
 666         void write_map(std::ostream &f)
 667         {
 668                 dict<int, string> input_lines;
 669                 dict<int, string> output_lines;
 670
 671                 for (auto wire : module->wires())
 672                 {
 673                         SigSpec sig = sigmap(wire);
 674
 675                         for (int i = 0; i < GetSize(wire); i++)
 676                         {
 677                                 RTLIL::SigBit b(wire, i);
 678                                 if (input_bits.count(b)) {
 679                                         int a = aig_map.at(b);
 680                                         log_assert((a & 1) == 0);
 681                                         input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
 682                                 }
 683
 684                                 if (output_bits.count(b)) {
 685                                         int o = ordered_outputs.at(b);
 686                                         int init = 2;
 687                                         output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
 688                                         continue;
 689                                 }
 690                         }
 691                 }
 692
 693                 input_lines.sort();
 694                 for (auto &it : input_lines)
 695                         f << it.second;
 696                 log_assert(input_lines.size() == input_bits.size());
 697
 698                 int box_count = 0;
 699                 for (auto cell : box_list)
 700                         f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
 701
 702                 output_lines.sort();
 703                 for (auto &it : output_lines)
 704                         f << it.second;
 705                 log_assert(output_lines.size() == output_bits.size());
 706         }
 707 };
 708
 709 struct XAigerBackend : public Backend {
 710         XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
 711         void help() YS_OVERRIDE
 712         {
 713                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 714                 log("\n");
 715                 log("    write_xaiger [options] [filename]\n");
 716                 log("\n");
 717                 log("Write the top module (according to the (* top *) attribute or if only one module\n");
 718                 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
 719                 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
 720                 log("pseudo-outputs.\n");
 721                 log("\n");
 722                 log("    -ascii\n");
 723                 log("        write ASCII version of AIGER format\n");
 724                 log("\n");
 725                 log("    -map <filename>\n");
 726                 log("        write an extra file with port and box symbols\n");
 727                 log("\n");
 728         }
 729         void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 730         {
 731                 bool ascii_mode = false;
 732                 std::string map_filename;
 733
 734                 log_header(design, "Executing XAIGER backend.\n");
 735
 736                 size_t argidx;
 737                 for (argidx = 1; argidx < args.size(); argidx++)
 738                 {
 739                         if (args[argidx] == "-ascii") {
 740                                 ascii_mode = true;
 741                                 continue;
 742                         }
 743                         if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
 744                                 map_filename = args[++argidx];
 745                                 continue;
 746                         }
 747                         break;
 748                 }
 749                 extra_args(f, filename, args, argidx, !ascii_mode);
 750
 751                 Module *top_module = design->top_module();
 752
 753                 if (top_module == nullptr)
 754                         log_error("Can't find top module in current design!\n");
 755
 756                 if (!design->selected_whole_module(top_module))
 757                         log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
 758
 759                 if (!top_module->processes.empty())
 760                         log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
 761                 if (!top_module->memories.empty())
 762                         log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
 763
 764                 XAigerWriter writer(top_module);
 765                 writer.write_aiger(*f, ascii_mode);
 766
 767                 if (!map_filename.empty()) {
 768                         std::ofstream mapf;
 769                         mapf.open(map_filename.c_str(), std::ofstream::trunc);
 770                         if (mapf.fail())
 771                                 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
 772                         writer.write_map(mapf);
 773                 }
 774         }
 775 } XAigerBackend;
 776
 777 PRIVATE_NAMESPACE_END