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Handle COs driven by 1'bx
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define __builtin_bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define __builtin_bswap32 OSSwapInt32
28 #endif
29
30 #include "kernel/yosys.h"
31 #include "kernel/sigtools.h"
32 #include "kernel/utils.h"
33
34 USING_YOSYS_NAMESPACE
35 PRIVATE_NAMESPACE_BEGIN
36
37 inline int32_t to_big_endian(int32_t i32) {
38 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
39 return __builtin_bswap32(i32);
40 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
41 return i32;
42 #else
43 #error "Unknown endianness"
44 #endif
45 }
46
47 void aiger_encode(std::ostream &f, int x)
48 {
49 log_assert(x >= 0);
50
51 while (x & ~0x7f) {
52 f.put((x & 0x7f) | 0x80);
53 x = x >> 7;
54 }
55
56 f.put(x);
57 }
58
59 struct XAigerWriter
60 {
61 Module *module;
62 SigMap sigmap;
63
64 pool<SigBit> input_bits, output_bits;
65 dict<SigBit, SigBit> not_map, alias_map;
66 dict<SigBit, pair<SigBit, SigBit>> and_map;
67 vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
68 vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
69
70 vector<pair<int, int>> aig_gates;
71 vector<int> aig_outputs;
72 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
73
74 dict<SigBit, int> aig_map;
75 dict<SigBit, int> ordered_outputs;
76
77 vector<Cell*> box_list;
78
79 int mkgate(int a0, int a1)
80 {
81 aig_m++, aig_a++;
82 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
83 return 2*aig_m;
84 }
85
86 int bit2aig(SigBit bit)
87 {
88 if (aig_map.count(bit) == 0)
89 {
90 aig_map[bit] = -1;
91
92 if (not_map.count(bit)) {
93 int a = bit2aig(not_map.at(bit)) ^ 1;
94 aig_map[bit] = a;
95 } else
96 if (and_map.count(bit)) {
97 auto args = and_map.at(bit);
98 int a0 = bit2aig(args.first);
99 int a1 = bit2aig(args.second);
100 aig_map[bit] = mkgate(a0, a1);
101 } else
102 if (alias_map.count(bit)) {
103 aig_map[bit] = bit2aig(alias_map.at(bit));
104 }
105
106 if (bit == State::Sx || bit == State::Sz)
107 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
108 }
109
110 log_assert(aig_map.at(bit) >= 0);
111 return aig_map.at(bit);
112 }
113
114 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
115 {
116 pool<SigBit> undriven_bits;
117 pool<SigBit> unused_bits;
118
119 // promote public wires
120 for (auto wire : module->wires())
121 if (wire->name[0] == '\\')
122 sigmap.add(wire);
123
124 // promote input wires
125 for (auto wire : module->wires())
126 if (wire->port_input)
127 sigmap.add(wire);
128
129 // promote output wires
130 for (auto wire : module->wires())
131 if (wire->port_output)
132 sigmap.add(wire);
133
134 for (auto wire : module->wires())
135 {
136 bool keep = wire->attributes.count("\\keep");
137
138 for (int i = 0; i < GetSize(wire); i++)
139 {
140 SigBit wirebit(wire, i);
141 SigBit bit = sigmap(wirebit);
142
143 if (bit.wire) {
144 undriven_bits.insert(bit);
145 unused_bits.insert(bit);
146 }
147
148 if (wire->port_input || keep) {
149 if (bit != wirebit)
150 alias_map[bit] = wirebit;
151 input_bits.insert(wirebit);
152 }
153
154 if (wire->port_output || keep) {
155 if (bit != RTLIL::Sx) {
156 if (bit != wirebit)
157 alias_map[wirebit] = bit;
158 output_bits.insert(wirebit);
159 }
160 else
161 log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
162 }
163 }
164 }
165
166 for (auto bit : input_bits)
167 undriven_bits.erase(sigmap(bit));
168 for (auto bit : output_bits)
169 if (!bit.wire->port_input)
170 unused_bits.erase(bit);
171
172 // TODO: Speed up toposort -- ultimately we care about
173 // box ordering, but not individual AIG cells
174 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
175 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
176 bool abc_box_seen = false;
177
178 for (auto cell : module->selected_cells()) {
179 if (cell->type == "$_NOT_")
180 {
181 SigBit A = sigmap(cell->getPort("\\A").as_bit());
182 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
183 unused_bits.erase(A);
184 undriven_bits.erase(Y);
185 not_map[Y] = A;
186 if (!holes_mode) {
187 toposort.node(cell->name);
188 bit_users[A].insert(cell->name);
189 bit_drivers[Y].insert(cell->name);
190 }
191 continue;
192 }
193
194 if (cell->type == "$_AND_")
195 {
196 SigBit A = sigmap(cell->getPort("\\A").as_bit());
197 SigBit B = sigmap(cell->getPort("\\B").as_bit());
198 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
199 unused_bits.erase(A);
200 unused_bits.erase(B);
201 undriven_bits.erase(Y);
202 and_map[Y] = make_pair(A, B);
203 if (!holes_mode) {
204 toposort.node(cell->name);
205 bit_users[A].insert(cell->name);
206 bit_users[B].insert(cell->name);
207 bit_drivers[Y].insert(cell->name);
208 }
209 continue;
210 }
211
212 log_assert(!holes_mode);
213
214 RTLIL::Module* inst_module = module->design->module(cell->type);
215 if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
216 abc_box_seen = true;
217
218 if (!holes_mode) {
219 toposort.node(cell->name);
220 for (const auto &conn : cell->connections()) {
221 if (cell->input(conn.first)) {
222 // Ignore inout for the sake of topographical ordering
223 if (cell->output(conn.first)) continue;
224 for (auto bit : sigmap(conn.second))
225 bit_users[bit].insert(cell->name);
226 }
227
228 if (cell->output(conn.first))
229 for (auto bit : sigmap(conn.second))
230 bit_drivers[bit].insert(cell->name);
231 }
232 }
233 }
234 else {
235 for (const auto &c : cell->connections()) {
236 if (c.second.is_fully_const()) continue;
237 auto is_input = cell->input(c.first);
238 auto is_output = cell->output(c.first);
239 log_assert(is_input || is_output);
240
241 if (is_input) {
242 for (auto b : c.second.bits()) {
243 Wire *w = b.wire;
244 if (!w) continue;
245 if (!w->port_output) {
246 SigBit I = sigmap(b);
247 if (I != b)
248 alias_map[b] = I;
249 output_bits.insert(b);
250 unused_bits.erase(b);
251 }
252 }
253 }
254 if (is_output) {
255 for (auto b : c.second.bits()) {
256 Wire *w = b.wire;
257 if (!w) continue;
258 input_bits.insert(b);
259 SigBit O = sigmap(b);
260 if (O != b)
261 alias_map[O] = b;
262 undriven_bits.erase(O);
263 }
264 }
265 }
266 }
267
268 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
269 }
270
271 if (abc_box_seen) {
272 for (auto &it : bit_users)
273 if (bit_drivers.count(it.first))
274 for (auto driver_cell : bit_drivers.at(it.first))
275 for (auto user_cell : it.second)
276 toposort.edge(driver_cell, user_cell);
277
278 pool<RTLIL::Module*> abc_carry_modules;
279
280 #if 0
281 toposort.analyze_loops = true;
282 #endif
283 bool no_loops = toposort.sort();
284 #if 0
285 unsigned i = 0;
286 for (auto &it : toposort.loops) {
287 log(" loop %d", i++);
288 for (auto cell : it)
289 log(" %s", log_id(cell));
290 log("\n");
291 }
292 #endif
293 log_assert(no_loops);
294
295 for (auto cell_name : toposort.sorted) {
296 RTLIL::Cell *cell = module->cell(cell_name);
297 RTLIL::Module* box_module = module->design->module(cell->type);
298 if (!box_module || !box_module->attributes.count("\\abc_box_id"))
299 continue;
300
301 if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
302 RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
303 RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
304 for (const auto &port_name : box_module->ports) {
305 RTLIL::Wire* w = box_module->wire(port_name);
306 log_assert(w);
307 if (w->port_input) {
308 if (w->attributes.count("\\abc_carry_in")) {
309 log_assert(!carry_in);
310 carry_in = w;
311 }
312 log_assert(!last_in || last_in->port_id < w->port_id);
313 last_in = w;
314 }
315 if (w->port_output) {
316 if (w->attributes.count("\\abc_carry_out")) {
317 log_assert(!carry_out);
318 carry_out = w;
319 }
320 log_assert(!last_out || last_out->port_id < w->port_id);
321 last_out = w;
322 }
323 }
324
325 if (carry_in) {
326 log_assert(last_in);
327 std::swap(box_module->ports[carry_in->port_id-1], box_module->ports[last_in->port_id-1]);
328 std::swap(carry_in->port_id, last_in->port_id);
329 }
330 if (carry_out) {
331 log_assert(last_out);
332 std::swap(box_module->ports[carry_out->port_id-1], box_module->ports[last_out->port_id-1]);
333 std::swap(carry_out->port_id, last_out->port_id);
334 }
335 }
336
337 // Fully pad all unused input connections of this box cell with S0
338 // Fully pad all undriven output connections of this box cell with anonymous wires
339 // NB: Assume box_module->ports are sorted alphabetically
340 // (as RTLIL::Module::fixup_ports() would do)
341 for (const auto &port_name : box_module->ports) {
342 RTLIL::Wire* w = box_module->wire(port_name);
343 log_assert(w);
344 auto it = cell->connections_.find(port_name);
345 if (w->port_input) {
346 RTLIL::SigSpec rhs;
347 if (it != cell->connections_.end()) {
348 if (GetSize(it->second) < GetSize(w))
349 it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second)));
350 rhs = it->second;
351 }
352 else {
353 rhs = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
354 cell->setPort(port_name, rhs);
355 }
356
357 int offset = 0;
358 for (auto b : rhs.bits()) {
359 SigBit I = sigmap(b);
360 if (b == RTLIL::Sx)
361 b = RTLIL::S0;
362 else if (I != b) {
363 if (I == RTLIL::Sx)
364 alias_map[b] = RTLIL::S0;
365 else
366 alias_map[b] = I;
367 }
368 co_bits.emplace_back(b, cell, port_name, offset++, 0);
369 unused_bits.erase(b);
370 }
371 }
372 if (w->port_output) {
373 RTLIL::SigSpec rhs;
374 auto it = cell->connections_.find(w->name);
375 if (it != cell->connections_.end()) {
376 if (GetSize(it->second) < GetSize(w))
377 it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
378 rhs = it->second;
379 }
380 else {
381 rhs = module->addWire(NEW_ID, GetSize(w));
382 cell->setPort(port_name, rhs);
383 }
384
385 int offset = 0;
386 for (const auto &b : rhs.bits()) {
387 ci_bits.emplace_back(b, cell, port_name, offset++);
388 SigBit O = sigmap(b);
389 if (O != b)
390 alias_map[O] = b;
391 undriven_bits.erase(O);
392
393 auto jt = input_bits.find(b);
394 if (jt != input_bits.end()) {
395 log_assert(b.wire->attributes.count("\\keep"));
396 input_bits.erase(b);
397 }
398 }
399 }
400 }
401 box_list.emplace_back(cell);
402 }
403
404 // TODO: Free memory from toposort, bit_drivers, bit_users
405 }
406
407 for (auto bit : input_bits) {
408 RTLIL::Wire *wire = bit.wire;
409 // If encountering an inout port, or a keep-ed wire, then create a new wire
410 // with $inout.out suffix, make it a PO driven by the existing inout, and
411 // inherit existing inout's drivers
412 if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
413 || wire->attributes.count("\\keep")) {
414 log_assert(input_bits.count(bit) && output_bits.count(bit));
415 RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
416 RTLIL::Wire *new_wire = module->wire(wire_name);
417 if (!new_wire)
418 new_wire = module->addWire(wire_name, GetSize(wire));
419 SigBit new_bit(new_wire, bit.offset);
420 module->connect(new_bit, bit);
421 if (not_map.count(bit))
422 not_map[new_bit] = not_map.at(bit);
423 else if (and_map.count(bit))
424 and_map[new_bit] = and_map.at(bit);
425 else if (alias_map.count(bit))
426 alias_map[new_bit] = alias_map.at(bit);
427 else
428 //log_abort();
429 alias_map[new_bit] = bit;
430 output_bits.erase(bit);
431 output_bits.insert(new_bit);
432 }
433 }
434
435 for (auto bit : unused_bits)
436 undriven_bits.erase(bit);
437
438 if (!undriven_bits.empty() && !holes_mode) {
439 undriven_bits.sort();
440 for (auto bit : undriven_bits) {
441 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
442 input_bits.insert(bit);
443 }
444 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
445 }
446
447 if (holes_mode) {
448 struct sort_by_port_id {
449 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
450 return a.wire->port_id < b.wire->port_id;
451 }
452 };
453 input_bits.sort(sort_by_port_id());
454 output_bits.sort(sort_by_port_id());
455 }
456 else {
457 input_bits.sort();
458 output_bits.sort();
459 }
460
461 not_map.sort();
462 and_map.sort();
463
464 aig_map[State::S0] = 0;
465 aig_map[State::S1] = 1;
466
467 for (auto bit : input_bits) {
468 aig_m++, aig_i++;
469 log_assert(!aig_map.count(bit));
470 aig_map[bit] = 2*aig_m;
471 }
472
473 for (auto &c : ci_bits) {
474 RTLIL::SigBit bit = std::get<0>(c);
475 aig_m++, aig_i++;
476 aig_map[bit] = 2*aig_m;
477 }
478
479 for (auto &c : co_bits) {
480 RTLIL::SigBit bit = std::get<0>(c);
481 std::get<4>(c) = ordered_outputs[bit] = aig_o++;
482 aig_outputs.push_back(bit2aig(bit));
483 }
484
485 for (auto bit : output_bits) {
486 ordered_outputs[bit] = aig_o++;
487 aig_outputs.push_back(bit2aig(bit));
488 }
489 }
490
491 void write_aiger(std::ostream &f, bool ascii_mode)
492 {
493 int aig_obc = aig_o;
494 int aig_obcj = aig_obc;
495 int aig_obcjf = aig_obcj;
496
497 log_assert(aig_m == aig_i + aig_l + aig_a);
498 log_assert(aig_obcjf == GetSize(aig_outputs));
499
500 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
501 f << stringf("\n");
502
503 if (ascii_mode)
504 {
505 for (int i = 0; i < aig_i; i++)
506 f << stringf("%d\n", 2*i+2);
507
508 for (int i = 0; i < aig_obc; i++)
509 f << stringf("%d\n", aig_outputs.at(i));
510
511 for (int i = aig_obc; i < aig_obcj; i++)
512 f << stringf("1\n");
513
514 for (int i = aig_obc; i < aig_obcj; i++)
515 f << stringf("%d\n", aig_outputs.at(i));
516
517 for (int i = aig_obcj; i < aig_obcjf; i++)
518 f << stringf("%d\n", aig_outputs.at(i));
519
520 for (int i = 0; i < aig_a; i++)
521 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
522 }
523 else
524 {
525 for (int i = 0; i < aig_obc; i++)
526 f << stringf("%d\n", aig_outputs.at(i));
527
528 for (int i = aig_obc; i < aig_obcj; i++)
529 f << stringf("1\n");
530
531 for (int i = aig_obc; i < aig_obcj; i++)
532 f << stringf("%d\n", aig_outputs.at(i));
533
534 for (int i = aig_obcj; i < aig_obcjf; i++)
535 f << stringf("%d\n", aig_outputs.at(i));
536
537 for (int i = 0; i < aig_a; i++) {
538 int lhs = 2*(aig_i+aig_l+i)+2;
539 int rhs0 = aig_gates.at(i).first;
540 int rhs1 = aig_gates.at(i).second;
541 int delta0 = lhs - rhs0;
542 int delta1 = rhs0 - rhs1;
543 aiger_encode(f, delta0);
544 aiger_encode(f, delta1);
545 }
546 }
547
548 f << "c";
549
550 if (!box_list.empty()) {
551 auto write_buffer = [](std::stringstream &buffer, int i32) {
552 int32_t i32_be = to_big_endian(i32);
553 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
554 };
555
556 std::stringstream h_buffer;
557 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
558 write_h_buffer(1);
559 log_debug("ciNum = %zu\n", input_bits.size() + ci_bits.size());
560 write_h_buffer(input_bits.size() + ci_bits.size());
561 log_debug("coNum = %zu\n", output_bits.size() + co_bits.size());
562 write_h_buffer(output_bits.size() + co_bits.size());
563 log_debug("piNum = %zu\n", input_bits.size());
564 write_h_buffer(input_bits.size());
565 log_debug("poNum = %zu\n", output_bits.size());
566 write_h_buffer(output_bits.size());
567 log_debug("boxNum = %zu\n", box_list.size());
568 write_h_buffer(box_list.size());
569
570 RTLIL::Module *holes_module = nullptr;
571 holes_module = module->design->addModule("$__holes__");
572 log_assert(holes_module);
573
574 int port_id = 1;
575 int box_count = 0;
576 for (auto cell : box_list) {
577 RTLIL::Module* box_module = module->design->module(cell->type);
578 int box_inputs = 0, box_outputs = 0;
579 Cell *holes_cell = nullptr;
580 if (box_module->get_bool_attribute("\\whitebox")) {
581 holes_cell = holes_module->addCell(cell->name, cell->type);
582 holes_cell->parameters = cell->parameters;
583 }
584
585 // NB: Assume box_module->ports are sorted alphabetically
586 // (as RTLIL::Module::fixup_ports() would do)
587 for (const auto &port_name : box_module->ports) {
588 RTLIL::Wire *w = box_module->wire(port_name);
589 log_assert(w);
590 RTLIL::Wire *holes_wire;
591 RTLIL::SigSpec port_wire;
592 if (w->port_input) {
593 for (int i = 0; i < GetSize(w); i++) {
594 box_inputs++;
595 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
596 if (!holes_wire) {
597 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
598 holes_wire->port_input = true;
599 holes_wire->port_id = port_id++;
600 holes_module->ports.push_back(holes_wire->name);
601 }
602 if (holes_cell)
603 port_wire.append(holes_wire);
604 }
605 if (!port_wire.empty())
606 holes_cell->setPort(w->name, port_wire);
607 }
608 if (w->port_output) {
609 box_outputs += GetSize(w);
610 for (int i = 0; i < GetSize(w); i++) {
611 if (GetSize(w) == 1)
612 holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
613 else
614 holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
615 holes_wire->port_output = true;
616 holes_wire->port_id = port_id++;
617 holes_module->ports.push_back(holes_wire->name);
618 if (holes_cell)
619 port_wire.append(holes_wire);
620 else
621 holes_module->connect(holes_wire, RTLIL::S0);
622 }
623 if (!port_wire.empty())
624 holes_cell->setPort(w->name, port_wire);
625 }
626 }
627
628 write_h_buffer(box_inputs);
629 write_h_buffer(box_outputs);
630 write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
631 write_h_buffer(box_count++);
632 }
633
634 f << "h";
635 std::string buffer_str = h_buffer.str();
636 int32_t buffer_size_be = to_big_endian(buffer_str.size());
637 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
638 f.write(buffer_str.data(), buffer_str.size());
639
640 std::stringstream r_buffer;
641 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
642 write_r_buffer(0);
643
644 f << "r";
645 buffer_str = r_buffer.str();
646 buffer_size_be = to_big_endian(buffer_str.size());
647 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
648 f.write(buffer_str.data(), buffer_str.size());
649
650 if (holes_module) {
651 // NB: fixup_ports() will sort ports by name
652 //holes_module->fixup_ports();
653 holes_module->check();
654
655 holes_module->design->selection_stack.emplace_back(false);
656 RTLIL::Selection& sel = holes_module->design->selection_stack.back();
657 sel.select(holes_module);
658
659 // TODO: Should not need to opt_merge if we only instantiate
660 // each box type once...
661 Pass::call(holes_module->design, "opt_merge -share_all");
662
663 Pass::call(holes_module->design, "flatten -wb");
664
665 // TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
666 // instead of per write_xaiger call
667 Pass::call(holes_module->design, "techmap");
668 Pass::call(holes_module->design, "aigmap");
669 for (auto cell : holes_module->cells())
670 if (!cell->type.in("$_NOT_", "$_AND_"))
671 log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
672
673 Pass::call(holes_module->design, "clean -purge");
674
675 std::stringstream a_buffer;
676 XAigerWriter writer(holes_module, true /* holes_mode */);
677 writer.write_aiger(a_buffer, false /*ascii_mode*/);
678
679 holes_module->design->selection_stack.pop_back();
680
681 f << "a";
682 std::string buffer_str = a_buffer.str();
683 int32_t buffer_size_be = to_big_endian(buffer_str.size());
684 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
685 f.write(buffer_str.data(), buffer_str.size());
686 holes_module->design->remove(holes_module);
687 }
688 }
689
690 f << stringf("Generated by %s\n", yosys_version_str);
691 }
692
693 void write_map(std::ostream &f, bool verbose_map)
694 {
695 dict<int, string> input_lines;
696 dict<int, string> output_lines;
697 dict<int, string> wire_lines;
698
699 for (auto wire : module->wires())
700 {
701 //if (!verbose_map && wire->name[0] == '$')
702 // continue;
703
704 SigSpec sig = sigmap(wire);
705
706 for (int i = 0; i < GetSize(wire); i++)
707 {
708 RTLIL::SigBit b(wire, i);
709 if (input_bits.count(b)) {
710 int a = aig_map.at(b);
711 log_assert((a & 1) == 0);
712 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
713 }
714
715 if (output_bits.count(b)) {
716 int o = ordered_outputs.at(b);
717 output_lines[o] += stringf("output %lu %d %s\n", o - co_bits.size(), i, log_id(wire));
718 continue;
719 }
720
721 if (verbose_map) {
722 if (aig_map.count(sig[i]) == 0)
723 continue;
724
725 int a = aig_map.at(sig[i]);
726 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
727 }
728 }
729 }
730
731 input_lines.sort();
732 for (auto &it : input_lines)
733 f << it.second;
734 log_assert(input_lines.size() == input_bits.size());
735
736 int box_count = 0;
737 for (auto cell : box_list)
738 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
739
740 output_lines.sort();
741 for (auto &it : output_lines)
742 f << it.second;
743 log_assert(output_lines.size() == output_bits.size());
744
745 wire_lines.sort();
746 for (auto &it : wire_lines)
747 f << it.second;
748 }
749 };
750
751 struct XAigerBackend : public Backend {
752 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
753 void help() YS_OVERRIDE
754 {
755 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
756 log("\n");
757 log(" write_xaiger [options] [filename]\n");
758 log("\n");
759 log("Write the current design to an XAIGER file. The design must be flattened and\n");
760 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
761 log("\n");
762 log(" -ascii\n");
763 log(" write ASCII version of AIGER format\n");
764 log("\n");
765 log(" -map <filename>\n");
766 log(" write an extra file with port and latch symbols\n");
767 log("\n");
768 log(" -vmap <filename>\n");
769 log(" like -map, but more verbose\n");
770 log("\n");
771 }
772 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
773 {
774 bool ascii_mode = false;
775 bool verbose_map = false;
776 std::string map_filename;
777
778 log_header(design, "Executing XAIGER backend.\n");
779
780 size_t argidx;
781 for (argidx = 1; argidx < args.size(); argidx++)
782 {
783 if (args[argidx] == "-ascii") {
784 ascii_mode = true;
785 continue;
786 }
787 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
788 map_filename = args[++argidx];
789 continue;
790 }
791 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
792 map_filename = args[++argidx];
793 verbose_map = true;
794 continue;
795 }
796 break;
797 }
798 extra_args(f, filename, args, argidx);
799
800 Module *top_module = design->top_module();
801
802 if (top_module == nullptr)
803 log_error("Can't find top module in current design!\n");
804
805 XAigerWriter writer(top_module);
806 writer.write_aiger(*f, ascii_mode);
807
808 if (!map_filename.empty()) {
809 std::ofstream mapf;
810 mapf.open(map_filename.c_str(), std::ofstream::trunc);
811 if (mapf.fail())
812 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
813 writer.write_map(mapf, verbose_map);
814 }
815 }
816 } XAigerBackend;
817
818 PRIVATE_NAMESPACE_END