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Fix different abc9 test
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define __builtin_bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define __builtin_bswap32 OSSwapInt32
28 #endif
29
30 #include "kernel/yosys.h"
31 #include "kernel/sigtools.h"
32 #include "kernel/utils.h"
33
34 USING_YOSYS_NAMESPACE
35 PRIVATE_NAMESPACE_BEGIN
36
37 inline int32_t to_big_endian(int32_t i32) {
38 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
39 return __builtin_bswap32(i32);
40 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
41 return i32;
42 #else
43 #error "Unknown endianness"
44 #endif
45 }
46
47 void aiger_encode(std::ostream &f, int x)
48 {
49 log_assert(x >= 0);
50
51 while (x & ~0x7f) {
52 f.put((x & 0x7f) | 0x80);
53 x = x >> 7;
54 }
55
56 f.put(x);
57 }
58
59 struct XAigerWriter
60 {
61 Module *module;
62 SigMap sigmap;
63
64 pool<SigBit> input_bits, output_bits;
65 dict<SigBit, SigBit> not_map, alias_map;
66 dict<SigBit, pair<SigBit, SigBit>> and_map;
67 vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
68 vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
69
70 vector<pair<int, int>> aig_gates;
71 vector<int> aig_outputs;
72 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
73
74 dict<SigBit, int> aig_map;
75 dict<SigBit, int> ordered_outputs;
76
77 vector<Cell*> box_list;
78 bool omode = false;
79
80 int mkgate(int a0, int a1)
81 {
82 aig_m++, aig_a++;
83 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
84 return 2*aig_m;
85 }
86
87 int bit2aig(SigBit bit)
88 {
89 if (aig_map.count(bit) == 0)
90 {
91 aig_map[bit] = -1;
92
93 if (not_map.count(bit)) {
94 int a = bit2aig(not_map.at(bit)) ^ 1;
95 aig_map[bit] = a;
96 } else
97 if (and_map.count(bit)) {
98 auto args = and_map.at(bit);
99 int a0 = bit2aig(args.first);
100 int a1 = bit2aig(args.second);
101 aig_map[bit] = mkgate(a0, a1);
102 } else
103 if (alias_map.count(bit)) {
104 aig_map[bit] = bit2aig(alias_map.at(bit));
105 }
106
107 if (bit == State::Sx || bit == State::Sz)
108 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
109 }
110
111 log_assert(aig_map.at(bit) >= 0);
112 return aig_map.at(bit);
113 }
114
115 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
116 {
117 pool<SigBit> undriven_bits;
118 pool<SigBit> unused_bits;
119
120 // promote public wires
121 for (auto wire : module->wires())
122 if (wire->name[0] == '\\')
123 sigmap.add(wire);
124
125 // promote input wires
126 for (auto wire : module->wires())
127 if (wire->port_input)
128 sigmap.add(wire);
129
130 // promote output wires
131 for (auto wire : module->wires())
132 if (wire->port_output)
133 sigmap.add(wire);
134
135 for (auto wire : module->wires())
136 {
137 bool keep = wire->attributes.count("\\keep");
138
139 for (int i = 0; i < GetSize(wire); i++)
140 {
141 SigBit wirebit(wire, i);
142 SigBit bit = sigmap(wirebit);
143
144 if (bit.wire) {
145 undriven_bits.insert(bit);
146 unused_bits.insert(bit);
147 }
148
149 if (wire->port_input || keep) {
150 if (bit != wirebit)
151 alias_map[bit] = wirebit;
152 input_bits.insert(wirebit);
153 }
154
155 if (wire->port_output || keep) {
156 if (bit != RTLIL::Sx) {
157 if (bit != wirebit)
158 alias_map[wirebit] = bit;
159 output_bits.insert(wirebit);
160 }
161 else
162 log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
163 }
164 }
165 }
166
167 for (auto bit : input_bits)
168 undriven_bits.erase(sigmap(bit));
169 for (auto bit : output_bits)
170 if (!bit.wire->port_input)
171 unused_bits.erase(bit);
172
173 // TODO: Speed up toposort -- ultimately we care about
174 // box ordering, but not individual AIG cells
175 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
176 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
177 bool abc_box_seen = false;
178
179 for (auto cell : module->selected_cells()) {
180 if (cell->type == "$_NOT_")
181 {
182 SigBit A = sigmap(cell->getPort("\\A").as_bit());
183 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
184 unused_bits.erase(A);
185 undriven_bits.erase(Y);
186 not_map[Y] = A;
187 if (!holes_mode) {
188 toposort.node(cell->name);
189 bit_users[A].insert(cell->name);
190 bit_drivers[Y].insert(cell->name);
191 }
192 continue;
193 }
194
195 if (cell->type == "$_AND_")
196 {
197 SigBit A = sigmap(cell->getPort("\\A").as_bit());
198 SigBit B = sigmap(cell->getPort("\\B").as_bit());
199 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
200 unused_bits.erase(A);
201 unused_bits.erase(B);
202 undriven_bits.erase(Y);
203 and_map[Y] = make_pair(A, B);
204 if (!holes_mode) {
205 toposort.node(cell->name);
206 bit_users[A].insert(cell->name);
207 bit_users[B].insert(cell->name);
208 bit_drivers[Y].insert(cell->name);
209 }
210 continue;
211 }
212
213 log_assert(!holes_mode);
214
215 RTLIL::Module* inst_module = module->design->module(cell->type);
216 if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
217 abc_box_seen = true;
218
219 if (!holes_mode) {
220 toposort.node(cell->name);
221 for (const auto &conn : cell->connections()) {
222 if (cell->input(conn.first)) {
223 // Ignore inout for the sake of topographical ordering
224 if (cell->output(conn.first)) continue;
225 for (auto bit : sigmap(conn.second))
226 bit_users[bit].insert(cell->name);
227 }
228
229 if (cell->output(conn.first))
230 for (auto bit : sigmap(conn.second))
231 bit_drivers[bit].insert(cell->name);
232 }
233 }
234 }
235 else {
236 for (const auto &c : cell->connections()) {
237 if (c.second.is_fully_const()) continue;
238 auto is_input = cell->input(c.first);
239 auto is_output = cell->output(c.first);
240 log_assert(is_input || is_output);
241
242 if (is_input) {
243 for (auto b : c.second.bits()) {
244 Wire *w = b.wire;
245 if (!w) continue;
246 if (!w->port_output) {
247 SigBit I = sigmap(b);
248 if (I != b)
249 alias_map[b] = I;
250 output_bits.insert(b);
251 unused_bits.erase(b);
252 }
253 }
254 }
255 if (is_output) {
256 for (auto b : c.second.bits()) {
257 Wire *w = b.wire;
258 if (!w) continue;
259 input_bits.insert(b);
260 SigBit O = sigmap(b);
261 if (O != b)
262 alias_map[O] = b;
263 undriven_bits.erase(O);
264 }
265 }
266 }
267 }
268
269 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
270 }
271
272 if (abc_box_seen) {
273 for (auto &it : bit_users)
274 if (bit_drivers.count(it.first))
275 for (auto driver_cell : bit_drivers.at(it.first))
276 for (auto user_cell : it.second)
277 toposort.edge(driver_cell, user_cell);
278
279 pool<RTLIL::Module*> abc_carry_modules;
280
281 #if 0
282 toposort.analyze_loops = true;
283 #endif
284 bool no_loops = toposort.sort();
285 #if 0
286 unsigned i = 0;
287 for (auto &it : toposort.loops) {
288 log(" loop %d", i++);
289 for (auto cell : it)
290 log(" %s", log_id(cell));
291 log("\n");
292 }
293 #endif
294 log_assert(no_loops);
295
296 for (auto cell_name : toposort.sorted) {
297 RTLIL::Cell *cell = module->cell(cell_name);
298 RTLIL::Module* box_module = module->design->module(cell->type);
299 if (!box_module || !box_module->attributes.count("\\abc_box_id"))
300 continue;
301
302 if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
303 RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
304 RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
305 for (const auto &port_name : box_module->ports) {
306 RTLIL::Wire* w = box_module->wire(port_name);
307 log_assert(w);
308 if (w->port_input) {
309 if (w->attributes.count("\\abc_carry_in")) {
310 log_assert(!carry_in);
311 carry_in = w;
312 }
313 log_assert(!last_in || last_in->port_id < w->port_id);
314 last_in = w;
315 }
316 if (w->port_output) {
317 if (w->attributes.count("\\abc_carry_out")) {
318 log_assert(!carry_out);
319 carry_out = w;
320 }
321 log_assert(!last_out || last_out->port_id < w->port_id);
322 last_out = w;
323 }
324 }
325
326 if (carry_in) {
327 log_assert(last_in);
328 std::swap(box_module->ports[carry_in->port_id-1], box_module->ports[last_in->port_id-1]);
329 std::swap(carry_in->port_id, last_in->port_id);
330 }
331 if (carry_out) {
332 log_assert(last_out);
333 std::swap(box_module->ports[carry_out->port_id-1], box_module->ports[last_out->port_id-1]);
334 std::swap(carry_out->port_id, last_out->port_id);
335 }
336 }
337
338 // Fully pad all unused input connections of this box cell with S0
339 // Fully pad all undriven output connections of this box cell with anonymous wires
340 // NB: Assume box_module->ports are sorted alphabetically
341 // (as RTLIL::Module::fixup_ports() would do)
342 for (const auto &port_name : box_module->ports) {
343 RTLIL::Wire* w = box_module->wire(port_name);
344 log_assert(w);
345 auto it = cell->connections_.find(port_name);
346 if (w->port_input) {
347 RTLIL::SigSpec rhs;
348 if (it != cell->connections_.end()) {
349 if (GetSize(it->second) < GetSize(w))
350 it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second)));
351 rhs = it->second;
352 }
353 else {
354 rhs = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
355 cell->setPort(port_name, rhs);
356 }
357
358 int offset = 0;
359 for (auto b : rhs.bits()) {
360 SigBit I = sigmap(b);
361 if (b == RTLIL::Sx)
362 b = RTLIL::S0;
363 else if (I != b) {
364 if (I == RTLIL::Sx)
365 alias_map[b] = RTLIL::S0;
366 else
367 alias_map[b] = I;
368 }
369 co_bits.emplace_back(b, cell, port_name, offset++, 0);
370 unused_bits.erase(b);
371 }
372 }
373 if (w->port_output) {
374 RTLIL::SigSpec rhs;
375 auto it = cell->connections_.find(w->name);
376 if (it != cell->connections_.end()) {
377 if (GetSize(it->second) < GetSize(w))
378 it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
379 rhs = it->second;
380 }
381 else {
382 rhs = module->addWire(NEW_ID, GetSize(w));
383 cell->setPort(port_name, rhs);
384 }
385
386 int offset = 0;
387 for (const auto &b : rhs.bits()) {
388 ci_bits.emplace_back(b, cell, port_name, offset++);
389 SigBit O = sigmap(b);
390 if (O != b)
391 alias_map[O] = b;
392 undriven_bits.erase(O);
393
394 auto jt = input_bits.find(b);
395 if (jt != input_bits.end()) {
396 log_assert(b.wire->attributes.count("\\keep"));
397 input_bits.erase(b);
398 }
399 }
400 }
401 }
402 box_list.emplace_back(cell);
403 }
404
405 // TODO: Free memory from toposort, bit_drivers, bit_users
406 }
407
408 for (auto bit : input_bits) {
409 if (!output_bits.count(bit))
410 continue;
411 RTLIL::Wire *wire = bit.wire;
412 // If encountering an inout port, or a keep-ed wire, then create a new wire
413 // with $inout.out suffix, make it a PO driven by the existing inout, and
414 // inherit existing inout's drivers
415 if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
416 || wire->attributes.count("\\keep")) {
417 RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
418 RTLIL::Wire *new_wire = module->wire(wire_name);
419 if (!new_wire)
420 new_wire = module->addWire(wire_name, GetSize(wire));
421 SigBit new_bit(new_wire, bit.offset);
422 module->connect(new_bit, bit);
423 if (not_map.count(bit))
424 not_map[new_bit] = not_map.at(bit);
425 else if (and_map.count(bit))
426 and_map[new_bit] = and_map.at(bit);
427 else if (alias_map.count(bit))
428 alias_map[new_bit] = alias_map.at(bit);
429 else
430 //log_abort();
431 alias_map[new_bit] = bit;
432 output_bits.erase(bit);
433 output_bits.insert(new_bit);
434 }
435 }
436
437 for (auto bit : unused_bits)
438 undriven_bits.erase(bit);
439
440 if (!undriven_bits.empty() && !holes_mode) {
441 undriven_bits.sort();
442 for (auto bit : undriven_bits) {
443 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
444 input_bits.insert(bit);
445 }
446 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
447 }
448
449 if (holes_mode) {
450 struct sort_by_port_id {
451 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
452 return a.wire->port_id < b.wire->port_id;
453 }
454 };
455 input_bits.sort(sort_by_port_id());
456 output_bits.sort(sort_by_port_id());
457 }
458 else {
459 input_bits.sort();
460 output_bits.sort();
461 }
462
463 not_map.sort();
464 and_map.sort();
465
466 aig_map[State::S0] = 0;
467 aig_map[State::S1] = 1;
468
469 for (auto bit : input_bits) {
470 aig_m++, aig_i++;
471 log_assert(!aig_map.count(bit));
472 aig_map[bit] = 2*aig_m;
473 }
474
475 for (auto &c : ci_bits) {
476 RTLIL::SigBit bit = std::get<0>(c);
477 aig_m++, aig_i++;
478 aig_map[bit] = 2*aig_m;
479 }
480
481 for (auto &c : co_bits) {
482 RTLIL::SigBit bit = std::get<0>(c);
483 std::get<4>(c) = ordered_outputs[bit] = aig_o++;
484 aig_outputs.push_back(bit2aig(bit));
485 }
486
487 for (auto bit : output_bits) {
488 ordered_outputs[bit] = aig_o++;
489 aig_outputs.push_back(bit2aig(bit));
490 }
491
492 if (output_bits.empty()) {
493 aig_o++;
494 aig_outputs.push_back(0);
495 omode = true;
496 }
497 }
498
499 void write_aiger(std::ostream &f, bool ascii_mode)
500 {
501 int aig_obc = aig_o;
502 int aig_obcj = aig_obc;
503 int aig_obcjf = aig_obcj;
504
505 log_assert(aig_m == aig_i + aig_l + aig_a);
506 log_assert(aig_obcjf == GetSize(aig_outputs));
507
508 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
509 f << stringf("\n");
510
511 if (ascii_mode)
512 {
513 for (int i = 0; i < aig_i; i++)
514 f << stringf("%d\n", 2*i+2);
515
516 for (int i = 0; i < aig_obc; i++)
517 f << stringf("%d\n", aig_outputs.at(i));
518
519 for (int i = aig_obc; i < aig_obcj; i++)
520 f << stringf("1\n");
521
522 for (int i = aig_obc; i < aig_obcj; i++)
523 f << stringf("%d\n", aig_outputs.at(i));
524
525 for (int i = aig_obcj; i < aig_obcjf; i++)
526 f << stringf("%d\n", aig_outputs.at(i));
527
528 for (int i = 0; i < aig_a; i++)
529 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
530 }
531 else
532 {
533 for (int i = 0; i < aig_obc; i++)
534 f << stringf("%d\n", aig_outputs.at(i));
535
536 for (int i = aig_obc; i < aig_obcj; i++)
537 f << stringf("1\n");
538
539 for (int i = aig_obc; i < aig_obcj; i++)
540 f << stringf("%d\n", aig_outputs.at(i));
541
542 for (int i = aig_obcj; i < aig_obcjf; i++)
543 f << stringf("%d\n", aig_outputs.at(i));
544
545 for (int i = 0; i < aig_a; i++) {
546 int lhs = 2*(aig_i+aig_l+i)+2;
547 int rhs0 = aig_gates.at(i).first;
548 int rhs1 = aig_gates.at(i).second;
549 int delta0 = lhs - rhs0;
550 int delta1 = rhs0 - rhs1;
551 aiger_encode(f, delta0);
552 aiger_encode(f, delta1);
553 }
554 }
555
556 f << "c";
557
558 if (!box_list.empty()) {
559 auto write_buffer = [](std::stringstream &buffer, int i32) {
560 int32_t i32_be = to_big_endian(i32);
561 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
562 };
563
564 std::stringstream h_buffer;
565 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
566 write_h_buffer(1);
567 log_debug("ciNum = %zu\n", input_bits.size() + ci_bits.size());
568 write_h_buffer(input_bits.size() + ci_bits.size());
569 log_debug("coNum = %zu\n", output_bits.size() + co_bits.size());
570 write_h_buffer(output_bits.size() + co_bits.size());
571 log_debug("piNum = %zu\n", input_bits.size());
572 write_h_buffer(input_bits.size());
573 log_debug("poNum = %zu\n", output_bits.size());
574 write_h_buffer(output_bits.size());
575 log_debug("boxNum = %zu\n", box_list.size());
576 write_h_buffer(box_list.size());
577
578 RTLIL::Module *holes_module = nullptr;
579 holes_module = module->design->addModule("$__holes__");
580 log_assert(holes_module);
581
582 int port_id = 1;
583 int box_count = 0;
584 for (auto cell : box_list) {
585 RTLIL::Module* box_module = module->design->module(cell->type);
586 int box_inputs = 0, box_outputs = 0;
587 Cell *holes_cell = nullptr;
588 if (box_module->get_bool_attribute("\\whitebox")) {
589 holes_cell = holes_module->addCell(cell->name, cell->type);
590 holes_cell->parameters = cell->parameters;
591 }
592
593 // NB: Assume box_module->ports are sorted alphabetically
594 // (as RTLIL::Module::fixup_ports() would do)
595 for (const auto &port_name : box_module->ports) {
596 RTLIL::Wire *w = box_module->wire(port_name);
597 log_assert(w);
598 RTLIL::Wire *holes_wire;
599 RTLIL::SigSpec port_wire;
600 if (w->port_input) {
601 for (int i = 0; i < GetSize(w); i++) {
602 box_inputs++;
603 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
604 if (!holes_wire) {
605 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
606 holes_wire->port_input = true;
607 holes_wire->port_id = port_id++;
608 holes_module->ports.push_back(holes_wire->name);
609 }
610 if (holes_cell)
611 port_wire.append(holes_wire);
612 }
613 if (!port_wire.empty())
614 holes_cell->setPort(w->name, port_wire);
615 }
616 if (w->port_output) {
617 box_outputs += GetSize(w);
618 for (int i = 0; i < GetSize(w); i++) {
619 if (GetSize(w) == 1)
620 holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
621 else
622 holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
623 holes_wire->port_output = true;
624 holes_wire->port_id = port_id++;
625 holes_module->ports.push_back(holes_wire->name);
626 if (holes_cell)
627 port_wire.append(holes_wire);
628 else
629 holes_module->connect(holes_wire, RTLIL::S0);
630 }
631 if (!port_wire.empty())
632 holes_cell->setPort(w->name, port_wire);
633 }
634 }
635
636 write_h_buffer(box_inputs);
637 write_h_buffer(box_outputs);
638 write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
639 write_h_buffer(box_count++);
640 }
641
642 f << "h";
643 std::string buffer_str = h_buffer.str();
644 int32_t buffer_size_be = to_big_endian(buffer_str.size());
645 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
646 f.write(buffer_str.data(), buffer_str.size());
647
648 std::stringstream r_buffer;
649 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
650 write_r_buffer(0);
651
652 f << "r";
653 buffer_str = r_buffer.str();
654 buffer_size_be = to_big_endian(buffer_str.size());
655 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
656 f.write(buffer_str.data(), buffer_str.size());
657
658 if (holes_module) {
659 // NB: fixup_ports() will sort ports by name
660 //holes_module->fixup_ports();
661 holes_module->check();
662
663 holes_module->design->selection_stack.emplace_back(false);
664 RTLIL::Selection& sel = holes_module->design->selection_stack.back();
665 sel.select(holes_module);
666
667 // TODO: Should not need to opt_merge if we only instantiate
668 // each box type once...
669 Pass::call(holes_module->design, "opt_merge -share_all");
670
671 Pass::call(holes_module->design, "flatten -wb");
672
673 // TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
674 // instead of per write_xaiger call
675 Pass::call(holes_module->design, "techmap");
676 Pass::call(holes_module->design, "aigmap");
677 for (auto cell : holes_module->cells())
678 if (!cell->type.in("$_NOT_", "$_AND_"))
679 log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
680
681 Pass::call(holes_module->design, "clean -purge");
682
683 std::stringstream a_buffer;
684 XAigerWriter writer(holes_module, true /* holes_mode */);
685 writer.write_aiger(a_buffer, false /*ascii_mode*/);
686
687 holes_module->design->selection_stack.pop_back();
688
689 f << "a";
690 std::string buffer_str = a_buffer.str();
691 int32_t buffer_size_be = to_big_endian(buffer_str.size());
692 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
693 f.write(buffer_str.data(), buffer_str.size());
694 holes_module->design->remove(holes_module);
695 }
696 }
697
698 f << stringf("Generated by %s\n", yosys_version_str);
699 }
700
701 void write_map(std::ostream &f, bool verbose_map)
702 {
703 dict<int, string> input_lines;
704 dict<int, string> output_lines;
705 dict<int, string> wire_lines;
706
707 for (auto wire : module->wires())
708 {
709 //if (!verbose_map && wire->name[0] == '$')
710 // continue;
711
712 SigSpec sig = sigmap(wire);
713
714 for (int i = 0; i < GetSize(wire); i++)
715 {
716 RTLIL::SigBit b(wire, i);
717 if (input_bits.count(b)) {
718 int a = aig_map.at(b);
719 log_assert((a & 1) == 0);
720 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
721 }
722
723 if (output_bits.count(b)) {
724 int o = ordered_outputs.at(b);
725 output_lines[o] += stringf("output %lu %d %s\n", o - co_bits.size(), i, log_id(wire));
726 continue;
727 }
728
729 if (verbose_map) {
730 if (aig_map.count(sig[i]) == 0)
731 continue;
732
733 int a = aig_map.at(sig[i]);
734 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
735 }
736 }
737 }
738
739 input_lines.sort();
740 for (auto &it : input_lines)
741 f << it.second;
742 log_assert(input_lines.size() == input_bits.size());
743
744 int box_count = 0;
745 for (auto cell : box_list)
746 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
747
748 output_lines.sort();
749 for (auto &it : output_lines)
750 f << it.second;
751 log_assert(output_lines.size() == output_bits.size());
752 if (omode && output_bits.empty())
753 f << "output " << output_lines.size() << " 0 $__dummy__\n";
754
755 wire_lines.sort();
756 for (auto &it : wire_lines)
757 f << it.second;
758 }
759 };
760
761 struct XAigerBackend : public Backend {
762 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
763 void help() YS_OVERRIDE
764 {
765 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
766 log("\n");
767 log(" write_xaiger [options] [filename]\n");
768 log("\n");
769 log("Write the current design to an XAIGER file. The design must be flattened and\n");
770 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
771 log("\n");
772 log(" -ascii\n");
773 log(" write ASCII version of AIGER format\n");
774 log("\n");
775 log(" -map <filename>\n");
776 log(" write an extra file with port and latch symbols\n");
777 log("\n");
778 log(" -vmap <filename>\n");
779 log(" like -map, but more verbose\n");
780 log("\n");
781 }
782 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
783 {
784 bool ascii_mode = false;
785 bool verbose_map = false;
786 std::string map_filename;
787
788 log_header(design, "Executing XAIGER backend.\n");
789
790 size_t argidx;
791 for (argidx = 1; argidx < args.size(); argidx++)
792 {
793 if (args[argidx] == "-ascii") {
794 ascii_mode = true;
795 continue;
796 }
797 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
798 map_filename = args[++argidx];
799 continue;
800 }
801 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
802 map_filename = args[++argidx];
803 verbose_map = true;
804 continue;
805 }
806 break;
807 }
808 extra_args(f, filename, args, argidx);
809
810 Module *top_module = design->top_module();
811
812 if (top_module == nullptr)
813 log_error("Can't find top module in current design!\n");
814
815 XAigerWriter writer(top_module);
816 writer.write_aiger(*f, ascii_mode);
817
818 if (!map_filename.empty()) {
819 std::ofstream mapf;
820 mapf.open(map_filename.c_str(), std::ofstream::trunc);
821 if (mapf.fail())
822 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
823 writer.write_map(mapf, verbose_map);
824 }
825 }
826 } XAigerBackend;
827
828 PRIVATE_NAMESPACE_END