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66ab3878e9f4c9181571c9eb5a5d9858bdf0896f
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/yosys.h"
22 #include "kernel/sigtools.h"
23
24 USING_YOSYS_NAMESPACE
25 PRIVATE_NAMESPACE_BEGIN
26
27 void aiger_encode(std::ostream &f, int x)
28 {
29 log_assert(x >= 0);
30
31 while (x & ~0x7f) {
32 f.put((x & 0x7f) | 0x80);
33 x = x >> 7;
34 }
35
36 f.put(x);
37 }
38
39 struct XAigerWriter
40 {
41 Module *module;
42 bool zinit_mode;
43 SigMap sigmap;
44
45 dict<SigBit, bool> init_map;
46 pool<SigBit> input_bits, output_bits;
47 dict<SigBit, SigBit> not_map, ff_map, alias_map;
48 dict<SigBit, pair<SigBit, SigBit>> and_map;
49 pool<SigBit> initstate_bits;
50 vector<std::pair<SigBit,int>> ci_bits, co_bits;
51 dict<IdString, unsigned> type_map;
52
53 vector<pair<int, int>> aig_gates;
54 vector<int> aig_latchin, aig_latchinit, aig_outputs;
55 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
56
57 dict<SigBit, int> aig_map;
58 dict<SigBit, int> ordered_outputs;
59 dict<SigBit, int> ordered_latches;
60
61 dict<SigBit, int> init_inputs;
62 int initstate_ff = 0;
63
64 vector<Cell*> box_list;
65
66 int mkgate(int a0, int a1)
67 {
68 aig_m++, aig_a++;
69 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
70 return 2*aig_m;
71 }
72
73 int bit2aig(SigBit bit)
74 {
75 if (aig_map.count(bit) == 0)
76 {
77 aig_map[bit] = -1;
78
79 if (initstate_bits.count(bit)) {
80 log_assert(initstate_ff > 0);
81 aig_map[bit] = initstate_ff;
82 } else
83 if (not_map.count(bit)) {
84 int a = bit2aig(not_map.at(bit)) ^ 1;
85 aig_map[bit] = a;
86 } else
87 if (and_map.count(bit)) {
88 auto args = and_map.at(bit);
89 int a0 = bit2aig(args.first);
90 int a1 = bit2aig(args.second);
91 aig_map[bit] = mkgate(a0, a1);
92 } else
93 if (alias_map.count(bit)) {
94 aig_map[bit] = bit2aig(alias_map.at(bit));
95 }
96
97 if (bit == State::Sx || bit == State::Sz)
98 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
99 }
100
101 log_assert(aig_map.at(bit) >= 0);
102 return aig_map.at(bit);
103 }
104
105 XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
106 {
107 pool<SigBit> undriven_bits;
108 pool<SigBit> unused_bits;
109
110 // promote public wires
111 for (auto wire : module->wires())
112 if (wire->name[0] == '\\')
113 sigmap.add(wire);
114
115 // promote input wires
116 for (auto wire : module->wires())
117 if (wire->port_input)
118 sigmap.add(wire);
119
120 // promote output wires
121 for (auto wire : module->wires())
122 if (wire->port_output)
123 sigmap.add(wire);
124
125 for (auto wire : module->wires())
126 {
127 if (wire->attributes.count("\\init")) {
128 SigSpec initsig = sigmap(wire);
129 Const initval = wire->attributes.at("\\init");
130 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
131 if (initval[i] == State::S0 || initval[i] == State::S1)
132 init_map[initsig[i]] = initval[i] == State::S1;
133 }
134
135 for (int i = 0; i < GetSize(wire); i++)
136 {
137 SigBit wirebit(wire, i);
138 SigBit bit = sigmap(wirebit);
139
140 if (bit.wire == nullptr) {
141 if (wire->port_output) {
142 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
143 output_bits.insert(wirebit);
144 }
145 continue;
146 }
147
148 undriven_bits.insert(bit);
149 unused_bits.insert(bit);
150
151 if (wire->port_input)
152 input_bits.insert(bit);
153
154 if (wire->port_output) {
155 if (bit != wirebit)
156 alias_map[wirebit] = bit;
157 output_bits.insert(wirebit);
158 }
159 }
160 }
161
162 for (auto bit : input_bits) {
163 if (!bit.wire->port_output)
164 undriven_bits.erase(bit);
165 // Erase POs that are also PIs
166 output_bits.erase(bit);
167 }
168
169 for (auto bit : output_bits)
170 if (!bit.wire->port_input)
171 unused_bits.erase(bit);
172
173 for (auto cell : module->cells())
174 {
175 if (cell->type == "$_NOT_")
176 {
177 SigBit A = sigmap(cell->getPort("\\A").as_bit());
178 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
179 unused_bits.erase(A);
180 undriven_bits.erase(Y);
181 not_map[Y] = A;
182 continue;
183 }
184
185 //if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
186 //{
187 // SigBit D = sigmap(cell->getPort("\\D").as_bit());
188 // SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
189 // unused_bits.erase(D);
190 // undriven_bits.erase(Q);
191 // ff_map[Q] = D;
192 // continue;
193 //}
194
195 if (cell->type == "$_AND_")
196 {
197 SigBit A = sigmap(cell->getPort("\\A").as_bit());
198 SigBit B = sigmap(cell->getPort("\\B").as_bit());
199 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
200 unused_bits.erase(A);
201 unused_bits.erase(B);
202 undriven_bits.erase(Y);
203 and_map[Y] = make_pair(A, B);
204 continue;
205 }
206
207 if (cell->type == "$initstate")
208 {
209 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
210 undriven_bits.erase(Y);
211 initstate_bits.insert(Y);
212 continue;
213 }
214
215 RTLIL::Module* box_module = module->design->module(cell->type);
216 bool abc_box = box_module && box_module->attributes.count("\\abc_box_id");
217
218 for (const auto &c : cell->connections()) {
219 /*if (c.second.is_fully_const()) continue;*/
220 for (auto b : c.second.bits()) {
221 auto is_input = cell->input(c.first);
222 auto is_output = cell->output(c.first);
223 log_assert(is_input || is_output);
224 if (is_input) {
225 /*if (!w->port_input)*/ {
226 SigBit I = sigmap(b);
227 if (I != b)
228 alias_map[b] = I;
229 /*if (!output_bits.count(b))*/
230 if (abc_box)
231 co_bits.emplace_back(b, 0);
232 else if (b.wire) {
233 output_bits.insert(b);
234 if (!b.wire->port_input)
235 unused_bits.erase(b);
236 }
237 }
238 }
239 if (is_output) {
240 SigBit O = sigmap(b);
241 /*if (!input_bits.count(O))*/
242 if (abc_box)
243 ci_bits.emplace_back(O, 0);
244 else {
245 input_bits.insert(O);
246 if (!O.wire->port_output)
247 undriven_bits.erase(O);
248 }
249 }
250 }
251 if (!type_map.count(cell->type))
252 type_map[cell->type] = type_map.size()+1;
253 }
254
255 if (abc_box)
256 box_list.emplace_back(cell);
257 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
258 }
259
260 for (auto bit : input_bits) {
261 RTLIL::Wire *wire = bit.wire;
262 // If encountering an inout port, then create a new wire with $inout.out
263 // suffix, make it a PO driven by the existing inout, and inherit existing
264 // inout's drivers
265 if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) {
266 RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
267 if (!new_wire)
268 new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
269 SigBit new_bit(new_wire, bit.offset);
270 module->connect(new_bit, bit);
271 if (not_map.count(bit))
272 not_map[new_bit] = not_map.at(bit);
273 else if (and_map.count(bit))
274 and_map[new_bit] = and_map.at(bit);
275 else if (alias_map.count(bit))
276 alias_map[new_bit] = alias_map.at(bit);
277 output_bits.insert(new_bit);
278 }
279 }
280
281 // Do some CI/CO post-processing:
282 // Erase all POs and COs that are undriven
283 for (auto bit : undriven_bits) {
284 //co_bits.erase(bit);
285 output_bits.erase(bit);
286 }
287 // Erase all CIs that are also COs
288 //for (auto bit : co_bits)
289 // ci_bits.erase(bit);
290 // CIs cannot be undriven
291 for (const auto &c : ci_bits)
292 undriven_bits.erase(c.first);
293
294 for (auto bit : unused_bits)
295 undriven_bits.erase(bit);
296
297 if (!undriven_bits.empty()) {
298 undriven_bits.sort();
299 for (auto bit : undriven_bits) {
300 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
301 input_bits.insert(bit);
302 }
303 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
304 }
305
306 init_map.sort();
307 input_bits.sort();
308 output_bits.sort();
309 not_map.sort();
310 ff_map.sort();
311 and_map.sort();
312
313 aig_map[State::S0] = 0;
314 aig_map[State::S1] = 1;
315
316 for (auto &c : ci_bits) {
317 aig_m++, aig_i++;
318 c.second = 2*aig_m;
319 aig_map[c.first] = c.second;
320 }
321
322 for (auto bit : input_bits) {
323 aig_m++, aig_i++;
324 aig_map[bit] = 2*aig_m;
325 }
326
327 if (imode && input_bits.empty()) {
328 aig_m++, aig_i++;
329 }
330
331 if (zinit_mode)
332 {
333 for (auto it : ff_map) {
334 if (init_map.count(it.first))
335 continue;
336 aig_m++, aig_i++;
337 init_inputs[it.first] = 2*aig_m;
338 }
339 }
340
341 for (auto it : ff_map) {
342 aig_m++, aig_l++;
343 aig_map[it.first] = 2*aig_m;
344 ordered_latches[it.first] = aig_l-1;
345 if (init_map.count(it.first) == 0)
346 aig_latchinit.push_back(2);
347 else
348 aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
349 }
350
351 if (!initstate_bits.empty() || !init_inputs.empty()) {
352 aig_m++, aig_l++;
353 initstate_ff = 2*aig_m+1;
354 aig_latchinit.push_back(0);
355 }
356
357 if (zinit_mode)
358 {
359 for (auto it : ff_map)
360 {
361 int l = ordered_latches[it.first];
362
363 if (aig_latchinit.at(l) == 1)
364 aig_map[it.first] ^= 1;
365
366 if (aig_latchinit.at(l) == 2)
367 {
368 int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
369 int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
370 aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
371 }
372 }
373 }
374
375 for (auto it : ff_map) {
376 int a = bit2aig(it.second);
377 int l = ordered_latches[it.first];
378 if (zinit_mode && aig_latchinit.at(l) == 1)
379 aig_latchin.push_back(a ^ 1);
380 else
381 aig_latchin.push_back(a);
382 }
383
384 if (!initstate_bits.empty() || !init_inputs.empty())
385 aig_latchin.push_back(1);
386
387 for (auto &c : co_bits) {
388 RTLIL::SigBit bit = c.first;
389 c.second = aig_o++;
390 ordered_outputs[bit] = c.second;
391 aig_outputs.push_back(bit2aig(bit));
392 }
393
394 for (auto bit : output_bits) {
395 ordered_outputs[bit] = aig_o++;
396 aig_outputs.push_back(bit2aig(bit));
397 }
398
399 if (omode && output_bits.empty()) {
400 aig_o++;
401 aig_outputs.push_back(0);
402 }
403
404 if (bmode) {
405 //aig_b++;
406 aig_outputs.push_back(0);
407 }
408 }
409
410 void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
411 {
412 int aig_obc = aig_o;
413 int aig_obcj = aig_obc;
414 int aig_obcjf = aig_obcj;
415
416 log_assert(aig_m == aig_i + aig_l + aig_a);
417 log_assert(aig_l == GetSize(aig_latchin));
418 log_assert(aig_l == GetSize(aig_latchinit));
419 log_assert(aig_obcjf == GetSize(aig_outputs));
420
421 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
422 f << stringf("\n");
423
424 if (ascii_mode)
425 {
426 for (int i = 0; i < aig_i; i++)
427 f << stringf("%d\n", 2*i+2);
428
429 for (int i = 0; i < aig_l; i++) {
430 if (zinit_mode || aig_latchinit.at(i) == 0)
431 f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
432 else if (aig_latchinit.at(i) == 1)
433 f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
434 else if (aig_latchinit.at(i) == 2)
435 f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
436 }
437
438 for (int i = 0; i < aig_obc; i++)
439 f << stringf("%d\n", aig_outputs.at(i));
440
441 for (int i = aig_obc; i < aig_obcj; i++)
442 f << stringf("1\n");
443
444 for (int i = aig_obc; i < aig_obcj; i++)
445 f << stringf("%d\n", aig_outputs.at(i));
446
447 for (int i = aig_obcj; i < aig_obcjf; i++)
448 f << stringf("%d\n", aig_outputs.at(i));
449
450 for (int i = 0; i < aig_a; i++)
451 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
452 }
453 else
454 {
455 for (int i = 0; i < aig_l; i++) {
456 if (zinit_mode || aig_latchinit.at(i) == 0)
457 f << stringf("%d\n", aig_latchin.at(i));
458 else if (aig_latchinit.at(i) == 1)
459 f << stringf("%d 1\n", aig_latchin.at(i));
460 else if (aig_latchinit.at(i) == 2)
461 f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
462 }
463
464 for (int i = 0; i < aig_obc; i++)
465 f << stringf("%d\n", aig_outputs.at(i));
466
467 for (int i = aig_obc; i < aig_obcj; i++)
468 f << stringf("1\n");
469
470 for (int i = aig_obc; i < aig_obcj; i++)
471 f << stringf("%d\n", aig_outputs.at(i));
472
473 for (int i = aig_obcj; i < aig_obcjf; i++)
474 f << stringf("%d\n", aig_outputs.at(i));
475
476 for (int i = 0; i < aig_a; i++) {
477 int lhs = 2*(aig_i+aig_l+i)+2;
478 int rhs0 = aig_gates.at(i).first;
479 int rhs1 = aig_gates.at(i).second;
480 int delta0 = lhs - rhs0;
481 int delta1 = rhs0 - rhs1;
482 aiger_encode(f, delta0);
483 aiger_encode(f, delta1);
484 }
485 }
486
487 if (symbols_mode)
488 {
489 dict<string, vector<string>> symbols;
490
491 bool output_seen = false;
492 for (auto wire : module->wires())
493 {
494 //if (wire->name[0] == '$')
495 // continue;
496
497 SigSpec sig = sigmap(wire);
498
499 for (int i = 0; i < GetSize(wire); i++)
500 {
501 RTLIL::SigBit b(wire, i);
502 if (input_bits.count(b)) {
503 int a = aig_map.at(sig[i]);
504 log_assert((a & 1) == 0);
505 if (GetSize(wire) != 1)
506 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
507 else
508 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
509 }
510
511 if (output_bits.count(b)) {
512 int o = ordered_outputs.at(b);
513 output_seen = !miter_mode;
514 if (GetSize(wire) != 1)
515 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
516 else
517 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
518 }
519
520 if (init_inputs.count(sig[i])) {
521 int a = init_inputs.at(sig[i]);
522 log_assert((a & 1) == 0);
523 if (GetSize(wire) != 1)
524 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
525 else
526 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
527 }
528
529 if (ordered_latches.count(sig[i])) {
530 int l = ordered_latches.at(sig[i]);
531 const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
532 if (GetSize(wire) != 1)
533 symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
534 else
535 symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
536 }
537 }
538 }
539
540 if (omode && !output_seen)
541 symbols["o0"].push_back("__dummy_o__");
542
543 symbols.sort();
544
545 for (auto &sym : symbols) {
546 f << sym.first;
547 std::sort(sym.second.begin(), sym.second.end());
548 for (auto &s : sym.second)
549 f << " " << s;
550 f << std::endl;
551 }
552 }
553
554 f << "c";
555
556 if (!box_list.empty()) {
557 std::stringstream h_buffer;
558 auto write_h_buffer = [&h_buffer](int i32) {
559 // TODO: Don't assume we're on little endian
560 #ifdef _WIN32
561 int i32_be = _byteswap_ulong(i32);
562 #else
563 int i32_be = __builtin_bswap32(i32);
564 #endif
565 h_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
566 };
567 int num_outputs = output_bits.size();
568 if (omode && num_outputs == 0)
569 num_outputs = 1;
570 write_h_buffer(1);
571 write_h_buffer(input_bits.size() + ci_bits.size());
572 write_h_buffer(num_outputs + co_bits.size());
573 write_h_buffer(input_bits.size());
574 write_h_buffer(num_outputs);
575 write_h_buffer(box_list.size());
576
577 RTLIL::Module *holes_module = nullptr;
578 holes_module = module->design->addModule("\\__holes__");
579
580 for (auto cell : box_list) {
581 int box_inputs = 0, box_outputs = 0;
582 int box_id = module->design->module(cell->type)->attributes.at("\\abc_box_id").as_int();
583 Cell *holes_cell = nullptr;
584 if (holes_module && !holes_module->cell(stringf("\\u%d", box_id)))
585 holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
586 RTLIL::Wire *holes_wire;
587 int num_inputs = 0;
588 for (const auto &c : cell->connections()) {
589 if (cell->input(c.first)) {
590 box_inputs += c.second.size();
591 if (holes_cell) {
592 holes_wire = holes_module->wire(stringf("\\i%d", num_inputs));
593 if (!holes_wire) {
594 holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs));
595 holes_wire->port_input = true;
596 }
597 ++num_inputs;
598 holes_cell->setPort(c.first, holes_wire);
599 }
600 }
601 if (cell->output(c.first)) {
602 box_outputs += c.second.size();
603 if (holes_cell) {
604 holes_wire = holes_module->addWire(stringf("\\%s.%s", cell->type.c_str(), c.first.c_str()));
605 holes_wire->port_output = true;
606 holes_cell->setPort(c.first, holes_wire);
607 }
608 }
609 }
610 write_h_buffer(box_inputs);
611 write_h_buffer(box_outputs);
612 write_h_buffer(box_id);
613 write_h_buffer(0 /* OldBoxNum */);
614 }
615
616 f << "h";
617 std::string buffer_str = h_buffer.str();
618 // TODO: Don't assume we're on little endian
619 #ifdef _WIN32
620 int buffer_size_be = _byteswap_ulong(buffer_str.size());
621 #else
622 int buffer_size_be = __builtin_bswap32(buffer_str.size());
623 #endif
624 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
625 f.write(buffer_str.data(), buffer_str.size());
626
627 if (holes_module) {
628 holes_module->fixup_ports();
629
630 holes_module->design->selection_stack.emplace_back(false);
631 RTLIL::Selection& sel = holes_module->design->selection_stack.back();
632 sel.select(holes_module);
633
634 Pass::call(holes_module->design, "flatten; aigmap");
635
636 holes_module->design->selection_stack.pop_back();
637
638 std::stringstream a_buffer;
639 XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/);
640 writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/);
641
642 f << "a";
643 std::string buffer_str = a_buffer.str();
644 // TODO: Don't assume we're on little endian
645 #ifdef _WIN32
646 int buffer_size_be = _byteswap_ulong(buffer_str.size());
647 #else
648 int buffer_size_be = __builtin_bswap32(buffer_str.size());
649 #endif
650 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
651 f.write(buffer_str.data(), buffer_str.size());
652 holes_module->design->remove(holes_module);
653 }
654 }
655
656 f << stringf("Generated by %s\n", yosys_version_str);
657 }
658
659 void write_map(std::ostream &f, bool verbose_map, bool omode)
660 {
661 dict<int, string> input_lines;
662 dict<int, string> init_lines;
663 dict<int, string> output_lines;
664 dict<int, string> latch_lines;
665 dict<int, string> wire_lines;
666
667 for (auto wire : module->wires())
668 {
669 //if (!verbose_map && wire->name[0] == '$')
670 // continue;
671
672 SigSpec sig = sigmap(wire);
673
674 for (int i = 0; i < GetSize(wire); i++)
675 {
676 RTLIL::SigBit b(wire, i);
677 if (input_bits.count(b)) {
678 int a = aig_map.at(sig[i]);
679 log_assert((a & 1) == 0);
680 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
681 }
682
683 if (output_bits.count(b)) {
684 int o = ordered_outputs.at(b);
685 output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
686 continue;
687 }
688
689 if (init_inputs.count(sig[i])) {
690 int a = init_inputs.at(sig[i]);
691 log_assert((a & 1) == 0);
692 init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
693 continue;
694 }
695
696 if (ordered_latches.count(sig[i])) {
697 int l = ordered_latches.at(sig[i]);
698 if (zinit_mode && (aig_latchinit.at(l) == 1))
699 latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
700 else
701 latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
702 continue;
703 }
704
705 if (verbose_map) {
706 if (aig_map.count(sig[i]) == 0)
707 continue;
708
709 int a = aig_map.at(sig[i]);
710 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
711 }
712 }
713 }
714
715 for (const auto &c : ci_bits) {
716 RTLIL::SigBit b = c.first;
717 RTLIL::Wire *wire = b.wire;
718 int i = b.offset;
719 int a = c.second;
720 log_assert((a & 1) == 0);
721 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
722 }
723
724 for (const auto &c : co_bits) {
725 RTLIL::SigBit b = c.first;
726 RTLIL::Wire *wire = b.wire;
727 int o = c.second;
728 if (wire)
729 output_lines[o] += stringf("output %d %d %s\n", o, b.offset, log_id(wire));
730 else
731 output_lines[o] += stringf("output %d %d __const%d__\n", o, 0, b.data);
732 }
733
734 input_lines.sort();
735 for (auto &it : input_lines)
736 f << it.second;
737 log_assert(input_lines.size() == input_bits.size() + ci_bits.size());
738
739 init_lines.sort();
740 for (auto &it : init_lines)
741 f << it.second;
742
743 output_lines.sort();
744 for (auto &it : output_lines)
745 f << it.second;
746 log_assert(output_lines.size() == output_bits.size() + co_bits.size());
747 if (omode && output_bits.empty())
748 f << "output " << output_lines.size() << " 0 __dummy_o__\n";
749
750 latch_lines.sort();
751 for (auto &it : latch_lines)
752 f << it.second;
753
754 wire_lines.sort();
755 for (auto &it : wire_lines)
756 f << it.second;
757 }
758 };
759
760 struct XAigerBackend : public Backend {
761 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
762 void help() YS_OVERRIDE
763 {
764 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
765 log("\n");
766 log(" write_xaiger [options] [filename]\n");
767 log("\n");
768 log("Write the current design to an XAIGER file. The design must be flattened and\n");
769 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
770 log("\n");
771 log(" -ascii\n");
772 log(" write ASCII version of AGIER format\n");
773 log("\n");
774 log(" -zinit\n");
775 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
776 log(" uninitialized FFs.\n");
777 log("\n");
778 log(" -symbols\n");
779 log(" include a symbol table in the generated AIGER file\n");
780 log("\n");
781 log(" -map <filename>\n");
782 log(" write an extra file with port and latch symbols\n");
783 log("\n");
784 log(" -vmap <filename>\n");
785 log(" like -map, but more verbose\n");
786 log("\n");
787 log(" -I, -O, -B\n");
788 log(" If the design contains no input/output/assert then create one\n");
789 log(" dummy input/output/bad_state pin to make the tools reading the\n");
790 log(" AIGER file happy.\n");
791 log("\n");
792 }
793 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
794 {
795 bool ascii_mode = false;
796 bool zinit_mode = false;
797 bool miter_mode = false;
798 bool symbols_mode = false;
799 bool verbose_map = false;
800 bool imode = false;
801 bool omode = false;
802 bool bmode = false;
803 std::string map_filename;
804
805 log_header(design, "Executing XAIGER backend.\n");
806
807 size_t argidx;
808 for (argidx = 1; argidx < args.size(); argidx++)
809 {
810 if (args[argidx] == "-ascii") {
811 ascii_mode = true;
812 continue;
813 }
814 if (args[argidx] == "-zinit") {
815 zinit_mode = true;
816 continue;
817 }
818 if (args[argidx] == "-symbols") {
819 symbols_mode = true;
820 continue;
821 }
822 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
823 map_filename = args[++argidx];
824 continue;
825 }
826 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
827 map_filename = args[++argidx];
828 verbose_map = true;
829 continue;
830 }
831 if (args[argidx] == "-I") {
832 imode = true;
833 continue;
834 }
835 if (args[argidx] == "-O") {
836 omode = true;
837 continue;
838 }
839 if (args[argidx] == "-B") {
840 bmode = true;
841 continue;
842 }
843 break;
844 }
845 extra_args(f, filename, args, argidx);
846
847 Module *top_module = design->top_module();
848
849 if (top_module == nullptr)
850 log_error("Can't find top module in current design!\n");
851
852 XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
853 writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
854
855 if (!map_filename.empty()) {
856 std::ofstream mapf;
857 mapf.open(map_filename.c_str(), std::ofstream::trunc);
858 if (mapf.fail())
859 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
860 writer.write_map(mapf, verbose_map, omode);
861 }
862 }
863 } XAigerBackend;
864
865 PRIVATE_NAMESPACE_END