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77659b4d8a5a84be0a7c062fc2b724a32c66f5de
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50
51 USING_YOSYS_NAMESPACE
52 PRIVATE_NAMESPACE_BEGIN
53
54 inline int32_t to_big_endian(int32_t i32) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
56 return bswap32(i32);
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
58 return i32;
59 #else
60 #error "Unknown endianness"
61 #endif
62 }
63
64 void aiger_encode(std::ostream &f, int x)
65 {
66 log_assert(x >= 0);
67
68 while (x & ~0x7f) {
69 f.put((x & 0x7f) | 0x80);
70 x = x >> 7;
71 }
72
73 f.put(x);
74 }
75
76 struct XAigerWriter
77 {
78 Module *module;
79 SigMap sigmap;
80
81 pool<SigBit> input_bits, output_bits, external_bits;
82 dict<SigBit, SigBit> not_map, alias_map;
83 dict<SigBit, pair<SigBit, SigBit>> and_map;
84 vector<SigBit> ci_bits, co_bits;
85 dict<SigBit, std::tuple<SigBit,int,int>> ff_bits;
86 dict<SigBit, float> arrival_times;
87
88 vector<pair<int, int>> aig_gates;
89 vector<int> aig_outputs;
90 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
91
92 dict<SigBit, int> aig_map;
93 dict<SigBit, int> ordered_outputs;
94
95 vector<Cell*> box_list;
96 dict<IdString, std::vector<IdString>> box_ports;
97
98 int mkgate(int a0, int a1)
99 {
100 aig_m++, aig_a++;
101 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
102 return 2*aig_m;
103 }
104
105 int bit2aig(SigBit bit)
106 {
107 auto it = aig_map.find(bit);
108 if (it != aig_map.end()) {
109 log_assert(it->second >= 0);
110 return it->second;
111 }
112
113 // NB: Cannot use iterator returned from aig_map.insert()
114 // since this function is called recursively
115
116 int a = -1;
117 if (not_map.count(bit)) {
118 a = bit2aig(not_map.at(bit)) ^ 1;
119 } else
120 if (and_map.count(bit)) {
121 auto args = and_map.at(bit);
122 int a0 = bit2aig(args.first);
123 int a1 = bit2aig(args.second);
124 a = mkgate(a0, a1);
125 } else
126 if (alias_map.count(bit)) {
127 a = bit2aig(alias_map.at(bit));
128 }
129
130 if (bit == State::Sx || bit == State::Sz) {
131 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
132 a = aig_map.at(State::S0);
133 }
134
135 log_assert(a >= 0);
136 aig_map[bit] = a;
137 return a;
138 }
139
140 XAigerWriter(Module *module) : module(module), sigmap(module)
141 {
142 pool<SigBit> undriven_bits;
143 pool<SigBit> unused_bits;
144
145 // promote public wires
146 for (auto wire : module->wires())
147 if (wire->name[0] == '\\')
148 sigmap.add(wire);
149
150 // promote input wires
151 for (auto wire : module->wires())
152 if (wire->port_input)
153 sigmap.add(wire);
154
155 // promote keep wires
156 for (auto wire : module->wires())
157 if (wire->get_bool_attribute(ID::keep))
158 sigmap.add(wire);
159
160 // First, collect all the ports in port_id order
161 // since module->wires() could be sorted
162 // alphabetically
163 for (auto port : module->ports) {
164 auto wire = module->wire(port);
165 log_assert(wire);
166 for (int i = 0; i < GetSize(wire); i++)
167 {
168 SigBit wirebit(wire, i);
169 SigBit bit = sigmap(wirebit);
170
171 if (bit.wire == nullptr) {
172 if (wire->port_output) {
173 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
174 output_bits.insert(wirebit);
175 }
176 continue;
177 }
178
179 if (wire->port_input)
180 input_bits.insert(bit);
181
182 if (wire->port_output) {
183 if (bit != wirebit)
184 alias_map[wirebit] = bit;
185 output_bits.insert(wirebit);
186 }
187 }
188 }
189
190 for (auto wire : module->wires())
191 for (int i = 0; i < GetSize(wire); i++)
192 {
193 SigBit wirebit(wire, i);
194 SigBit bit = sigmap(wirebit);
195
196 if (bit.wire) {
197 undriven_bits.insert(bit);
198 unused_bits.insert(bit);
199 }
200 }
201
202 // TODO: Speed up toposort -- ultimately we care about
203 // box ordering, but not individual AIG cells
204 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
205 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
206 bool abc9_box_seen = false;
207 std::vector<Cell*> flop_boxes;
208
209 for (auto cell : module->selected_cells()) {
210 if (cell->type == "$_NOT_")
211 {
212 SigBit A = sigmap(cell->getPort("\\A").as_bit());
213 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
214 unused_bits.erase(A);
215 undriven_bits.erase(Y);
216 not_map[Y] = A;
217 toposort.node(cell->name);
218 bit_users[A].insert(cell->name);
219 bit_drivers[Y].insert(cell->name);
220 continue;
221 }
222
223 if (cell->type == "$_AND_")
224 {
225 SigBit A = sigmap(cell->getPort("\\A").as_bit());
226 SigBit B = sigmap(cell->getPort("\\B").as_bit());
227 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
228 unused_bits.erase(A);
229 unused_bits.erase(B);
230 undriven_bits.erase(Y);
231 and_map[Y] = make_pair(A, B);
232 toposort.node(cell->name);
233 bit_users[A].insert(cell->name);
234 bit_users[B].insert(cell->name);
235 bit_drivers[Y].insert(cell->name);
236 continue;
237 }
238
239 if (cell->type == "$__ABC9_FF_")
240 {
241 SigBit D = sigmap(cell->getPort("\\D").as_bit());
242 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
243 unused_bits.erase(D);
244 undriven_bits.erase(Q);
245 alias_map[Q] = D;
246 auto r = ff_bits.insert(std::make_pair(D, std::make_tuple(Q, 0, 2)));
247 log_assert(r.second);
248 continue;
249 }
250
251 RTLIL::Module* inst_module = module->design->module(cell->type);
252 if (inst_module) {
253 bool abc9_box = inst_module->attributes.count("\\abc9_box_id") && !cell->get_bool_attribute("\\abc9_keep");
254
255 for (const auto &conn : cell->connections()) {
256 auto port_wire = inst_module->wire(conn.first);
257
258 if (port_wire->port_output) {
259 int arrival = 0;
260 auto it = port_wire->attributes.find("\\abc9_arrival");
261 if (it != port_wire->attributes.end()) {
262 if (it->second.flags != 0)
263 log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
264 arrival = it->second.as_int();
265 }
266 if (arrival)
267 for (auto bit : sigmap(conn.second))
268 arrival_times[bit] = arrival;
269 }
270
271 if (abc9_box) {
272 // Ignore inout for the sake of topographical ordering
273 if (port_wire->port_input && !port_wire->port_output)
274 for (auto bit : sigmap(conn.second))
275 bit_users[bit].insert(cell->name);
276 if (port_wire->port_output)
277 for (auto bit : sigmap(conn.second))
278 bit_drivers[bit].insert(cell->name);
279 }
280 }
281
282 if (abc9_box) {
283 abc9_box_seen = true;
284
285 toposort.node(cell->name);
286
287 if (inst_module->get_bool_attribute("\\abc9_flop"))
288 flop_boxes.push_back(cell);
289 continue;
290 }
291 }
292
293 bool cell_known = inst_module || cell->known();
294 for (const auto &c : cell->connections()) {
295 if (c.second.is_fully_const()) continue;
296 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
297 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
298 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
299 if (!is_input && !is_output)
300 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
301
302 if (is_input)
303 for (auto b : c.second) {
304 Wire *w = b.wire;
305 if (!w) continue;
306 if (!w->port_output || !cell_known) {
307 SigBit I = sigmap(b);
308 if (I != b)
309 alias_map[b] = I;
310 output_bits.insert(b);
311 }
312 }
313 }
314
315 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
316 }
317
318 if (abc9_box_seen) {
319 dict<IdString, std::pair<IdString,int>> flop_q;
320 for (auto cell : flop_boxes) {
321 auto r = flop_q.insert(std::make_pair(cell->type, std::make_pair(IdString(), 0)));
322 SigBit d;
323 if (r.second) {
324 for (const auto &conn : cell->connections()) {
325 const SigSpec &rhs = conn.second;
326 if (!rhs.is_bit())
327 continue;
328 if (!ff_bits.count(rhs))
329 continue;
330 r.first->second.first = conn.first;
331 Module *inst_module = module->design->module(cell->type);
332 Wire *wire = inst_module->wire(conn.first);
333 log_assert(wire);
334 auto jt = wire->attributes.find("\\abc9_arrival");
335 if (jt != wire->attributes.end()) {
336 if (jt->second.flags != 0)
337 log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
338 r.first->second.second = jt->second.as_int();
339 }
340 d = rhs;
341 log_assert(d == sigmap(d));
342 break;
343 }
344 }
345 else
346 d = cell->getPort(r.first->second.first);
347
348 auto &rhs = ff_bits.at(d);
349
350 auto it = cell->attributes.find(ID(abc9_mergeability));
351 log_assert(it != cell->attributes.end());
352 std::get<1>(rhs) = it->second.as_int();
353 cell->attributes.erase(it);
354
355 it = cell->attributes.find(ID(abc9_init));
356 log_assert(it != cell->attributes.end());
357 log_assert(GetSize(it->second) == 1);
358 if (it->second[0] == State::S1)
359 std::get<2>(rhs) = 1;
360 else if (it->second[0] == State::S0)
361 std::get<2>(rhs) = 0;
362 else {
363 log_assert(it->second[0] == State::Sx);
364 std::get<2>(rhs) = 0;
365 }
366 cell->attributes.erase(it);
367
368 const SigBit &q = std::get<0>(rhs);
369 auto arrival = r.first->second.second;
370 if (arrival)
371 arrival_times[q] = arrival;
372 }
373
374 for (auto &it : bit_users)
375 if (bit_drivers.count(it.first))
376 for (auto driver_cell : bit_drivers.at(it.first))
377 for (auto user_cell : it.second)
378 toposort.edge(driver_cell, user_cell);
379
380 #if 0
381 toposort.analyze_loops = true;
382 #endif
383 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
384 #if 0
385 unsigned i = 0;
386 for (auto &it : toposort.loops) {
387 log(" loop %d\n", i++);
388 for (auto cell_name : it) {
389 auto cell = module->cell(cell_name);
390 log_assert(cell);
391 log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
392 }
393 }
394 #endif
395 log_assert(no_loops);
396
397 for (auto cell_name : toposort.sorted) {
398 RTLIL::Cell *cell = module->cell(cell_name);
399 log_assert(cell);
400
401 RTLIL::Module* box_module = module->design->module(cell->type);
402 if (!box_module || !box_module->attributes.count("\\abc9_box_id")
403 || cell->get_bool_attribute("\\abc9_keep"))
404 continue;
405
406 bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
407
408 auto r = box_ports.insert(cell->type);
409 if (r.second) {
410 // Make carry in the last PI, and carry out the last PO
411 // since ABC requires it this way
412 IdString carry_in, carry_out;
413 for (const auto &port_name : box_module->ports) {
414 auto w = box_module->wire(port_name);
415 log_assert(w);
416 if (w->get_bool_attribute("\\abc9_carry")) {
417 if (w->port_input) {
418 if (carry_in != IdString())
419 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
420 carry_in = port_name;
421 }
422 if (w->port_output) {
423 if (carry_out != IdString())
424 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
425 carry_out = port_name;
426 }
427 }
428 else
429 r.first->second.push_back(port_name);
430 }
431
432 if (carry_in != IdString() && carry_out == IdString())
433 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
434 if (carry_in == IdString() && carry_out != IdString())
435 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
436 if (carry_in != IdString()) {
437 log_assert(carry_out != IdString());
438 r.first->second.push_back(carry_in);
439 r.first->second.push_back(carry_out);
440 }
441 }
442
443 // Fully pad all unused input connections of this box cell with S0
444 // Fully pad all undriven output connections of this box cell with anonymous wires
445 for (auto port_name : r.first->second) {
446 auto w = box_module->wire(port_name);
447 log_assert(w);
448 auto it = cell->connections_.find(port_name);
449 if (w->port_input) {
450 RTLIL::SigSpec rhs;
451 if (it != cell->connections_.end()) {
452 if (GetSize(it->second) < GetSize(w))
453 it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
454 rhs = it->second;
455 }
456 else {
457 rhs = RTLIL::SigSpec(State::S0, GetSize(w));
458 cell->setPort(port_name, rhs);
459 }
460
461 for (auto b : rhs) {
462 SigBit I = sigmap(b);
463 if (b == RTLIL::Sx)
464 b = State::S0;
465 else if (I != b) {
466 if (I == RTLIL::Sx)
467 alias_map[b] = State::S0;
468 else
469 alias_map[b] = I;
470 }
471 co_bits.emplace_back(b);
472 unused_bits.erase(I);
473 }
474 }
475 if (w->port_output) {
476 RTLIL::SigSpec rhs;
477 auto it = cell->connections_.find(w->name);
478 if (it != cell->connections_.end()) {
479 if (GetSize(it->second) < GetSize(w))
480 it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
481 rhs = it->second;
482 }
483 else {
484 Wire *wire = module->addWire(NEW_ID, GetSize(w));
485 if (blackbox)
486 wire->set_bool_attribute(ID(abc9_padding));
487 rhs = wire;
488 cell->setPort(port_name, rhs);
489 }
490
491 for (const auto &b : rhs.bits()) {
492 SigBit O = sigmap(b);
493 if (O != b)
494 alias_map[O] = b;
495 ci_bits.emplace_back(b);
496 undriven_bits.erase(O);
497 }
498 }
499 }
500
501 // Connect <cell>.$abc9_currQ (inserted by abc9_map.v) as an input to the flop box
502 if (box_module->get_bool_attribute("\\abc9_flop")) {
503 SigSpec rhs = module->wire(stringf("%s.$abc9_currQ", cell->name.c_str()));
504 if (rhs.empty())
505 log_error("'%s.$abc9_currQ' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
506
507 for (auto b : rhs) {
508 SigBit I = sigmap(b);
509 if (b == RTLIL::Sx)
510 b = State::S0;
511 else if (I != b) {
512 if (I == RTLIL::Sx)
513 alias_map[b] = State::S0;
514 else
515 alias_map[b] = I;
516 }
517 co_bits.emplace_back(b);
518 unused_bits.erase(I);
519 }
520 }
521
522 box_list.emplace_back(cell);
523 }
524
525 // TODO: Free memory from toposort, bit_drivers, bit_users
526 }
527
528 for (auto bit : input_bits)
529 undriven_bits.erase(sigmap(bit));
530 for (auto bit : output_bits)
531 unused_bits.erase(sigmap(bit));
532 for (auto bit : unused_bits)
533 undriven_bits.erase(bit);
534
535 // Make all undriven bits a primary input
536 for (auto bit : undriven_bits) {
537 input_bits.insert(bit);
538 undriven_bits.erase(bit);
539 }
540
541 aig_map[State::S0] = 0;
542 aig_map[State::S1] = 1;
543
544 // pool<> iterates in LIFO order...
545 for (int i = input_bits.size()-1; i >= 0; i--) {
546 const auto &bit = *input_bits.element(i);
547 aig_m++, aig_i++;
548 log_assert(!aig_map.count(bit));
549 aig_map[bit] = 2*aig_m;
550 }
551
552 for (const auto &i : ff_bits) {
553 const SigBit &q = std::get<0>(i.second);
554 aig_m++, aig_i++;
555 log_assert(!aig_map.count(q));
556 aig_map[q] = 2*aig_m;
557 }
558
559 for (auto &bit : ci_bits) {
560 aig_m++, aig_i++;
561 log_assert(!aig_map.count(bit));
562 aig_map[bit] = 2*aig_m;
563 }
564
565 for (auto bit : co_bits) {
566 ordered_outputs[bit] = aig_o++;
567 aig_outputs.push_back(bit2aig(bit));
568 }
569
570 // pool<> iterates in LIFO order...
571 for (int i = output_bits.size()-1; i >= 0; i--) {
572 const auto &bit = *output_bits.element(i);
573 ordered_outputs[bit] = aig_o++;
574 aig_outputs.push_back(bit2aig(bit));
575 }
576
577 for (auto &i : ff_bits) {
578 const SigBit &d = i.first;
579 aig_o++;
580 aig_outputs.push_back(aig_map.at(d));
581 }
582 }
583
584 void write_aiger(std::ostream &f, bool ascii_mode)
585 {
586 int aig_obc = aig_o;
587 int aig_obcj = aig_obc;
588 int aig_obcjf = aig_obcj;
589
590 log_assert(aig_m == aig_i + aig_l + aig_a);
591 log_assert(aig_obcjf == GetSize(aig_outputs));
592
593 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
594 f << stringf("\n");
595
596 if (ascii_mode)
597 {
598 for (int i = 0; i < aig_i; i++)
599 f << stringf("%d\n", 2*i+2);
600
601 for (int i = 0; i < aig_obc; i++)
602 f << stringf("%d\n", aig_outputs.at(i));
603
604 for (int i = aig_obc; i < aig_obcj; i++)
605 f << stringf("1\n");
606
607 for (int i = aig_obc; i < aig_obcj; i++)
608 f << stringf("%d\n", aig_outputs.at(i));
609
610 for (int i = aig_obcj; i < aig_obcjf; i++)
611 f << stringf("%d\n", aig_outputs.at(i));
612
613 for (int i = 0; i < aig_a; i++)
614 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
615 }
616 else
617 {
618 for (int i = 0; i < aig_obc; i++)
619 f << stringf("%d\n", aig_outputs.at(i));
620
621 for (int i = aig_obc; i < aig_obcj; i++)
622 f << stringf("1\n");
623
624 for (int i = aig_obc; i < aig_obcj; i++)
625 f << stringf("%d\n", aig_outputs.at(i));
626
627 for (int i = aig_obcj; i < aig_obcjf; i++)
628 f << stringf("%d\n", aig_outputs.at(i));
629
630 for (int i = 0; i < aig_a; i++) {
631 int lhs = 2*(aig_i+aig_l+i)+2;
632 int rhs0 = aig_gates.at(i).first;
633 int rhs1 = aig_gates.at(i).second;
634 int delta0 = lhs - rhs0;
635 int delta1 = rhs0 - rhs1;
636 aiger_encode(f, delta0);
637 aiger_encode(f, delta1);
638 }
639 }
640
641 f << "c";
642
643 auto write_buffer = [](std::stringstream &buffer, int i32) {
644 int32_t i32_be = to_big_endian(i32);
645 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
646 };
647 std::stringstream h_buffer;
648 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
649 write_h_buffer(1);
650 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
651 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
652 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
653 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
654 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
655 write_h_buffer(input_bits.size() + ff_bits.size());
656 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
657 write_h_buffer(output_bits.size() + ff_bits.size());
658 log_debug("boxNum = %d\n", GetSize(box_list));
659 write_h_buffer(box_list.size());
660
661 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
662 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
663 };
664 std::stringstream i_buffer;
665 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
666 for (auto bit : input_bits)
667 write_i_buffer(arrival_times.at(bit, 0));
668 //std::stringstream o_buffer;
669 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
670 //for (auto bit : output_bits)
671 // write_o_buffer(0);
672
673 if (!box_list.empty() || !ff_bits.empty()) {
674 RTLIL::Module *holes_module = module->design->addModule("$__holes__");
675 log_assert(holes_module);
676
677 dict<IdString, Cell*> cell_cache;
678
679 int port_id = 1;
680 int box_count = 0;
681 for (auto cell : box_list) {
682 RTLIL::Module* orig_box_module = module->design->module(cell->type);
683 log_assert(orig_box_module);
684 IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
685 RTLIL::Module* box_module = module->design->module(derived_name);
686 if (box_module->has_processes())
687 Pass::call_on_module(module->design, box_module, "proc");
688
689 auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
690 Cell *holes_cell = r.first->second;
691 if (r.second && box_module->get_bool_attribute("\\whitebox")) {
692 holes_cell = holes_module->addCell(cell->name, cell->type);
693 holes_cell->parameters = cell->parameters;
694 r.first->second = holes_cell;
695 }
696
697 int box_inputs = 0, box_outputs = 0;
698 for (auto port_name : box_ports.at(cell->type)) {
699 RTLIL::Wire *w = box_module->wire(port_name);
700 log_assert(w);
701 RTLIL::Wire *holes_wire;
702 RTLIL::SigSpec port_sig;
703
704 if (w->port_input)
705 for (int i = 0; i < GetSize(w); i++) {
706 box_inputs++;
707 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
708 if (!holes_wire) {
709 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
710 holes_wire->port_input = true;
711 holes_wire->port_id = port_id++;
712 holes_module->ports.push_back(holes_wire->name);
713 }
714 if (holes_cell)
715 port_sig.append(holes_wire);
716 }
717 if (w->port_output) {
718 box_outputs += GetSize(w);
719 for (int i = 0; i < GetSize(w); i++) {
720 if (GetSize(w) == 1)
721 holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
722 else
723 holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
724 holes_wire->port_output = true;
725 holes_wire->port_id = port_id++;
726 holes_module->ports.push_back(holes_wire->name);
727 if (holes_cell)
728 port_sig.append(holes_wire);
729 else
730 holes_module->connect(holes_wire, State::S0);
731 }
732 }
733 if (!port_sig.empty()) {
734 if (r.second)
735 holes_cell->setPort(w->name, port_sig);
736 else
737 holes_module->connect(holes_cell->getPort(w->name), port_sig);
738 }
739 }
740
741 // For flops only, create an extra 1-bit input that drives a new wire
742 // called "<cell>.$abc9_currQ" that is used below
743 if (box_module->get_bool_attribute("\\abc9_flop")) {
744 log_assert(holes_cell);
745
746 box_inputs++;
747 Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
748 if (!holes_wire) {
749 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
750 holes_wire->port_input = true;
751 holes_wire->port_id = port_id++;
752 holes_module->ports.push_back(holes_wire->name);
753 }
754 Wire *w = holes_module->addWire(stringf("%s.$abc9_currQ", cell->name.c_str()));
755 holes_module->connect(w, holes_wire);
756 }
757
758 write_h_buffer(box_inputs);
759 write_h_buffer(box_outputs);
760 write_h_buffer(box_module->attributes.at("\\abc9_box_id").as_int());
761 write_h_buffer(box_count++);
762 }
763
764 std::stringstream r_buffer;
765 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
766 log_debug("flopNum = %d\n", GetSize(ff_bits));
767 write_r_buffer(ff_bits.size());
768
769 std::stringstream s_buffer;
770 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
771 write_s_buffer(ff_bits.size());
772
773 for (const auto &i : ff_bits) {
774 const SigBit &q = std::get<0>(i.second);
775 int mergeability = std::get<1>(i.second);
776 log_assert(mergeability > 0);
777 write_r_buffer(mergeability);
778 int init = std::get<2>(i.second);
779 write_s_buffer(init);
780 write_i_buffer(arrival_times.at(q, 0));
781 //write_o_buffer(0);
782 }
783
784 f << "r";
785 std::string buffer_str = r_buffer.str();
786 int32_t buffer_size_be = to_big_endian(buffer_str.size());
787 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
788 f.write(buffer_str.data(), buffer_str.size());
789
790 f << "s";
791 buffer_str = s_buffer.str();
792 buffer_size_be = to_big_endian(buffer_str.size());
793 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
794 f.write(buffer_str.data(), buffer_str.size());
795
796 if (holes_module) {
797 log_push();
798
799 // NB: fixup_ports() will sort ports by name
800 //holes_module->fixup_ports();
801 holes_module->check();
802
803 // Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
804 // since boxes may contain parameters in which case `flatten` would have
805 // created a new $paramod ...
806 Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
807
808 dict<SigSig, SigSig> replace;
809 for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
810 auto cell = it->second;
811 if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
812 "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
813 SigBit D = cell->getPort("\\D");
814 SigBit Q = cell->getPort("\\Q");
815 // Remove the DFF cell from what needs to be a combinatorial box
816 it = holes_module->cells_.erase(it);
817 Wire *port;
818 if (GetSize(Q.wire) == 1)
819 port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
820 else
821 port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
822 log_assert(port);
823 // Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
824 // in order to extract the combinatorial control logic that feeds the box
825 // (i.e. clock enable, synchronous reset, etc.)
826 replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
827 // Since `flatten` above would have created wires named "<cell>.Q",
828 // extract the pre-techmap cell name
829 auto pos = Q.wire->name.str().rfind(".");
830 log_assert(pos != std::string::npos);
831 IdString driver = Q.wire->name.substr(0, pos);
832 // And drive the signal that was previously driven by "DFF.Q" (typically
833 // used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
834 // wire (which itself is driven an input port) we inserted above
835 Wire *currQ = holes_module->wire(stringf("%s.$abc9_currQ", driver.c_str()));
836 log_assert(currQ);
837 holes_module->connect(Q, currQ);
838 continue;
839 }
840 else if (!cell->type.in("$_NOT_", "$_AND_"))
841 log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
842 ++it;
843 }
844
845 for (auto &conn : holes_module->connections_) {
846 auto it = replace.find(conn);
847 if (it != replace.end())
848 conn = it->second;
849 }
850
851 // Move into a new (temporary) design so that "clean" will only
852 // operate (and run checks on) this one module
853 RTLIL::Design *holes_design = new RTLIL::Design;
854 module->design->modules_.erase(holes_module->name);
855 holes_design->add(holes_module);
856 Pass::call(holes_design, "opt -purge");
857
858 std::stringstream a_buffer;
859 XAigerWriter writer(holes_module);
860 writer.write_aiger(a_buffer, false /*ascii_mode*/);
861 delete holes_design;
862
863 f << "a";
864 std::string buffer_str = a_buffer.str();
865 int32_t buffer_size_be = to_big_endian(buffer_str.size());
866 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
867 f.write(buffer_str.data(), buffer_str.size());
868
869 log_pop();
870 }
871 }
872
873 f << "h";
874 std::string buffer_str = h_buffer.str();
875 int32_t buffer_size_be = to_big_endian(buffer_str.size());
876 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
877 f.write(buffer_str.data(), buffer_str.size());
878
879 f << "i";
880 buffer_str = i_buffer.str();
881 buffer_size_be = to_big_endian(buffer_str.size());
882 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
883 f.write(buffer_str.data(), buffer_str.size());
884 //f << "o";
885 //buffer_str = o_buffer.str();
886 //buffer_size_be = to_big_endian(buffer_str.size());
887 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
888 //f.write(buffer_str.data(), buffer_str.size());
889
890 f << stringf("Generated by %s\n", yosys_version_str);
891
892 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
893 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
894 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
895 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
896 }
897
898 void write_map(std::ostream &f, bool verbose_map)
899 {
900 dict<int, string> input_lines;
901 dict<int, string> output_lines;
902 dict<int, string> wire_lines;
903
904 for (auto wire : module->wires())
905 {
906 //if (!verbose_map && wire->name[0] == '$')
907 // continue;
908
909 SigSpec sig = sigmap(wire);
910
911 for (int i = 0; i < GetSize(wire); i++)
912 {
913 RTLIL::SigBit b(wire, i);
914 if (input_bits.count(b)) {
915 int a = aig_map.at(b);
916 log_assert((a & 1) == 0);
917 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
918 }
919
920 if (output_bits.count(b)) {
921 int o = ordered_outputs.at(b);
922 int init = 2;
923 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
924 continue;
925 }
926
927 if (verbose_map) {
928 if (aig_map.count(sig[i]) == 0)
929 continue;
930
931 int a = aig_map.at(sig[i]);
932 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
933 }
934 }
935 }
936
937 input_lines.sort();
938 for (auto &it : input_lines)
939 f << it.second;
940 log_assert(input_lines.size() == input_bits.size());
941
942 int box_count = 0;
943 for (auto cell : box_list)
944 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
945
946 output_lines.sort();
947 for (auto &it : output_lines)
948 f << it.second;
949 log_assert(output_lines.size() == output_bits.size());
950
951 wire_lines.sort();
952 for (auto &it : wire_lines)
953 f << it.second;
954 }
955 };
956
957 struct XAigerBackend : public Backend {
958 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
959 void help() YS_OVERRIDE
960 {
961 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
962 log("\n");
963 log(" write_xaiger [options] [filename]\n");
964 log("\n");
965 log("Write the current design to an XAIGER file. The design must be flattened and\n");
966 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
967 log("\n");
968 log(" -ascii\n");
969 log(" write ASCII version of AIGER format\n");
970 log("\n");
971 log(" -map <filename>\n");
972 log(" write an extra file with port and box symbols\n");
973 log("\n");
974 log(" -vmap <filename>\n");
975 log(" like -map, but more verbose\n");
976 log("\n");
977 }
978 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
979 {
980 bool ascii_mode = false;
981 bool verbose_map = false;
982 std::string map_filename;
983
984 log_header(design, "Executing XAIGER backend.\n");
985
986 size_t argidx;
987 for (argidx = 1; argidx < args.size(); argidx++)
988 {
989 if (args[argidx] == "-ascii") {
990 ascii_mode = true;
991 continue;
992 }
993 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
994 map_filename = args[++argidx];
995 continue;
996 }
997 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
998 map_filename = args[++argidx];
999 verbose_map = true;
1000 continue;
1001 }
1002 break;
1003 }
1004 extra_args(f, filename, args, argidx, !ascii_mode);
1005
1006 Module *top_module = design->top_module();
1007
1008 if (top_module == nullptr)
1009 log_error("Can't find top module in current design!\n");
1010
1011 XAigerWriter writer(top_module);
1012 writer.write_aiger(*f, ascii_mode);
1013
1014 if (!map_filename.empty()) {
1015 std::ofstream mapf;
1016 mapf.open(map_filename.c_str(), std::ofstream::trunc);
1017 if (mapf.fail())
1018 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
1019 writer.write_map(mapf, verbose_map);
1020 }
1021 }
1022 } XAigerBackend;
1023
1024 PRIVATE_NAMESPACE_END