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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50
51 USING_YOSYS_NAMESPACE
52 PRIVATE_NAMESPACE_BEGIN
53
54 inline int32_t to_big_endian(int32_t i32) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
56 return bswap32(i32);
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
58 return i32;
59 #else
60 #error "Unknown endianness"
61 #endif
62 }
63
64 void aiger_encode(std::ostream &f, int x)
65 {
66 log_assert(x >= 0);
67
68 while (x & ~0x7f) {
69 f.put((x & 0x7f) | 0x80);
70 x = x >> 7;
71 }
72
73 f.put(x);
74 }
75
76 struct XAigerWriter
77 {
78 Module *module;
79 SigMap sigmap;
80
81 pool<SigBit> input_bits, output_bits;
82 dict<SigBit, SigBit> not_map, alias_map;
83 dict<SigBit, pair<SigBit, SigBit>> and_map;
84 vector<SigBit> ci_bits, co_bits;
85 dict<SigBit, Cell*> ff_bits;
86 dict<SigBit, float> arrival_times;
87
88 vector<pair<int, int>> aig_gates;
89 vector<int> aig_outputs;
90 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
91
92 dict<SigBit, int> aig_map;
93 dict<SigBit, int> ordered_outputs;
94
95 vector<Cell*> box_list;
96
97 int mkgate(int a0, int a1)
98 {
99 aig_m++, aig_a++;
100 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
101 return 2*aig_m;
102 }
103
104 int bit2aig(SigBit bit)
105 {
106 auto it = aig_map.find(bit);
107 if (it != aig_map.end()) {
108 log_assert(it->second >= 0);
109 return it->second;
110 }
111
112 // NB: Cannot use iterator returned from aig_map.insert()
113 // since this function is called recursively
114
115 int a = -1;
116 if (not_map.count(bit)) {
117 a = bit2aig(not_map.at(bit)) ^ 1;
118 } else
119 if (and_map.count(bit)) {
120 auto args = and_map.at(bit);
121 int a0 = bit2aig(args.first);
122 int a1 = bit2aig(args.second);
123 a = mkgate(a0, a1);
124 } else
125 if (alias_map.count(bit)) {
126 a = bit2aig(alias_map.at(bit));
127 }
128
129 if (bit == State::Sx || bit == State::Sz) {
130 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
131 a = aig_map.at(State::S0);
132 }
133
134 log_assert(a >= 0);
135 aig_map[bit] = a;
136 return a;
137 }
138
139 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
140 {
141 pool<SigBit> undriven_bits;
142 pool<SigBit> unused_bits;
143
144 // promote public wires
145 for (auto wire : module->wires())
146 if (wire->name[0] == '\\')
147 sigmap.add(wire);
148
149 // promote input wires
150 for (auto wire : module->wires())
151 if (wire->port_input)
152 sigmap.add(wire);
153
154 // promote keep wires
155 for (auto wire : module->wires())
156 if (wire->get_bool_attribute(ID::keep))
157 sigmap.add(wire);
158
159 for (auto wire : module->wires())
160 for (int i = 0; i < GetSize(wire); i++)
161 {
162 SigBit wirebit(wire, i);
163 SigBit bit = sigmap(wirebit);
164
165 if (bit.wire == nullptr) {
166 if (wire->port_output) {
167 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
168 output_bits.insert(wirebit);
169 }
170 continue;
171 }
172
173 undriven_bits.insert(bit);
174 unused_bits.insert(bit);
175
176 bool keep = wire->get_bool_attribute(ID::keep);
177 if (wire->port_input || keep)
178 input_bits.insert(bit);
179
180 if (wire->port_output || keep) {
181 if (bit != wirebit)
182 alias_map[wirebit] = bit;
183 output_bits.insert(wirebit);
184 }
185 }
186
187 dict<IdString,dict<IdString,int>> arrival_cache;
188 for (auto cell : module->cells()) {
189 RTLIL::Module* inst_module = module->design->module(cell->type);
190 if (!cell->has_keep_attr()) {
191 if (cell->type == "$_NOT_")
192 {
193 SigBit A = sigmap(cell->getPort("\\A").as_bit());
194 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
195 unused_bits.erase(A);
196 undriven_bits.erase(Y);
197 not_map[Y] = A;
198 continue;
199 }
200
201 if (cell->type == "$_AND_")
202 {
203 SigBit A = sigmap(cell->getPort("\\A").as_bit());
204 SigBit B = sigmap(cell->getPort("\\B").as_bit());
205 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
206 unused_bits.erase(A);
207 unused_bits.erase(B);
208 undriven_bits.erase(Y);
209 and_map[Y] = make_pair(A, B);
210 continue;
211 }
212
213 if (cell->type == "$__ABC9_FF_" &&
214 // The presence of an abc9_mergeability attribute indicates
215 // that we do want to pass this flop to ABC
216 cell->attributes.count("\\abc9_mergeability"))
217 {
218 SigBit D = sigmap(cell->getPort("\\D").as_bit());
219 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
220 unused_bits.erase(D);
221 undriven_bits.erase(Q);
222 alias_map[Q] = D;
223 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
224 log_assert(r.second);
225 continue;
226 }
227
228 if (inst_module) {
229 auto it = cell->attributes.find("\\abc9_box_seq");
230 if (it != cell->attributes.end()) {
231 int abc9_box_seq = it->second.as_int();
232 if (GetSize(box_list) <= abc9_box_seq)
233 box_list.resize(abc9_box_seq+1);
234 box_list[abc9_box_seq] = cell;
235 // Only flop boxes may have arrival times
236 if (!inst_module->get_bool_attribute("\\abc9_flop"))
237 continue;
238 }
239
240 auto &cell_arrivals = arrival_cache[cell->type];
241 for (const auto &conn : cell->connections()) {
242 auto r = cell_arrivals.insert(conn.first);
243 auto &arrival = r.first->second;
244 if (r.second) {
245 auto port_wire = inst_module->wire(conn.first);
246 if (port_wire->port_output) {
247 auto it = port_wire->attributes.find("\\abc9_arrival");
248 if (it != port_wire->attributes.end()) {
249 if (it->second.flags != 0)
250 log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
251 arrival = it->second.as_int();
252 }
253 }
254 }
255 if (arrival)
256 for (auto bit : sigmap(conn.second))
257 arrival_times[bit] = arrival;
258 }
259 }
260 }
261
262 bool cell_known = inst_module || cell->known();
263 for (const auto &c : cell->connections()) {
264 if (c.second.is_fully_const()) continue;
265 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
266 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
267 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
268 if (!is_input && !is_output)
269 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
270
271 if (is_input)
272 for (auto b : c.second) {
273 Wire *w = b.wire;
274 if (!w) continue;
275 // Do not add as PO if bit is already a PI
276 if (input_bits.count(b))
277 continue;
278 if (!w->port_output || !cell_known) {
279 SigBit I = sigmap(b);
280 if (I != b)
281 alias_map[b] = I;
282 output_bits.insert(b);
283 }
284 }
285 }
286
287 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
288 }
289
290 dict<IdString, std::vector<IdString>> box_ports;
291 for (auto cell : box_list) {
292 log_assert(cell);
293
294 RTLIL::Module* box_module = module->design->module(cell->type);
295 log_assert(box_module);
296 log_assert(box_module->attributes.count("\\abc9_box_id"));
297
298 auto r = box_ports.insert(cell->type);
299 if (r.second) {
300 // Make carry in the last PI, and carry out the last PO
301 // since ABC requires it this way
302 IdString carry_in, carry_out;
303 for (const auto &port_name : box_module->ports) {
304 auto w = box_module->wire(port_name);
305 log_assert(w);
306 if (w->get_bool_attribute("\\abc9_carry")) {
307 if (w->port_input) {
308 if (carry_in != IdString())
309 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
310 carry_in = port_name;
311 }
312 if (w->port_output) {
313 if (carry_out != IdString())
314 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
315 carry_out = port_name;
316 }
317 }
318 else
319 r.first->second.push_back(port_name);
320 }
321
322 if (carry_in != IdString() && carry_out == IdString())
323 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
324 if (carry_in == IdString() && carry_out != IdString())
325 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
326 if (carry_in != IdString()) {
327 r.first->second.push_back(carry_in);
328 r.first->second.push_back(carry_out);
329 }
330 }
331
332 // Fully pad all unused input connections of this box cell with S0
333 // Fully pad all undriven output connections of this box cell with anonymous wires
334 for (auto port_name : r.first->second) {
335 auto w = box_module->wire(port_name);
336 log_assert(w);
337 auto rhs = cell->getPort(port_name);
338 if (w->port_input)
339 for (auto b : rhs) {
340 SigBit I = sigmap(b);
341 if (b == RTLIL::Sx)
342 b = State::S0;
343 else if (I != b) {
344 if (I == RTLIL::Sx)
345 alias_map[b] = State::S0;
346 else
347 alias_map[b] = I;
348 }
349 co_bits.emplace_back(b);
350 unused_bits.erase(I);
351 }
352 if (w->port_output)
353 for (const auto &b : rhs.bits()) {
354 SigBit O = sigmap(b);
355 if (O != b)
356 alias_map[O] = b;
357 ci_bits.emplace_back(b);
358 undriven_bits.erase(O);
359 // If PI and CI, then must be a (* keep *) wire
360 if (input_bits.erase(O)) {
361 log_assert(output_bits.count(O));
362 log_assert(O.wire->get_bool_attribute(ID::keep));
363 }
364 }
365 }
366
367 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
368 if (box_module->get_bool_attribute("\\abc9_flop")) {
369 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
370 if (rhs.empty())
371 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
372
373 for (auto b : rhs) {
374 SigBit I = sigmap(b);
375 if (b == RTLIL::Sx)
376 b = State::S0;
377 else if (I != b) {
378 if (I == RTLIL::Sx)
379 alias_map[b] = State::S0;
380 else
381 alias_map[b] = I;
382 }
383 co_bits.emplace_back(b);
384 unused_bits.erase(I);
385 }
386 }
387 }
388
389 for (auto bit : input_bits)
390 undriven_bits.erase(bit);
391 for (auto bit : output_bits)
392 unused_bits.erase(sigmap(bit));
393 for (auto bit : unused_bits)
394 undriven_bits.erase(bit);
395
396 // Make all undriven bits a primary input
397 for (auto bit : undriven_bits) {
398 input_bits.insert(bit);
399 undriven_bits.erase(bit);
400 }
401
402 if (holes_mode) {
403 struct sort_by_port_id {
404 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
405 return a.wire->port_id < b.wire->port_id ||
406 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
407 }
408 };
409 input_bits.sort(sort_by_port_id());
410 output_bits.sort(sort_by_port_id());
411 }
412
413 aig_map[State::S0] = 0;
414 aig_map[State::S1] = 1;
415
416 for (const auto &bit : input_bits) {
417 aig_m++, aig_i++;
418 log_assert(!aig_map.count(bit));
419 aig_map[bit] = 2*aig_m;
420 }
421
422 for (const auto &i : ff_bits) {
423 const Cell *cell = i.second;
424 const SigBit &q = sigmap(cell->getPort("\\Q"));
425 aig_m++, aig_i++;
426 log_assert(!aig_map.count(q));
427 aig_map[q] = 2*aig_m;
428 }
429
430 for (auto &bit : ci_bits) {
431 aig_m++, aig_i++;
432 log_assert(!aig_map.count(bit));
433 aig_map[bit] = 2*aig_m;
434 }
435
436 for (auto bit : co_bits) {
437 ordered_outputs[bit] = aig_o++;
438 aig_outputs.push_back(bit2aig(bit));
439 }
440
441 for (const auto &bit : output_bits) {
442 ordered_outputs[bit] = aig_o++;
443 int aig;
444 // Unlike bit2aig() which checks aig_map first, for
445 // inout/keep bits, since aig_map will point to
446 // the PI, first attempt to find the NOT/AND driver
447 // before resorting to an aig_map lookup (which
448 // could be another PO)
449 if (input_bits.count(bit)) {
450 if (not_map.count(bit)) {
451 aig = bit2aig(not_map.at(bit)) ^ 1;
452 } else if (and_map.count(bit)) {
453 auto args = and_map.at(bit);
454 int a0 = bit2aig(args.first);
455 int a1 = bit2aig(args.second);
456 aig = mkgate(a0, a1);
457 }
458 else
459 aig = aig_map.at(bit);
460 }
461 else
462 aig = bit2aig(bit);
463 aig_outputs.push_back(aig);
464 }
465
466 for (auto &i : ff_bits) {
467 const SigBit &d = i.first;
468 aig_o++;
469 aig_outputs.push_back(aig_map.at(d));
470 }
471 }
472
473 void write_aiger(std::ostream &f, bool ascii_mode)
474 {
475 int aig_obc = aig_o;
476 int aig_obcj = aig_obc;
477 int aig_obcjf = aig_obcj;
478
479 log_assert(aig_m == aig_i + aig_l + aig_a);
480 log_assert(aig_obcjf == GetSize(aig_outputs));
481
482 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
483 f << stringf("\n");
484
485 if (ascii_mode)
486 {
487 for (int i = 0; i < aig_i; i++)
488 f << stringf("%d\n", 2*i+2);
489
490 for (int i = 0; i < aig_obc; i++)
491 f << stringf("%d\n", aig_outputs.at(i));
492
493 for (int i = aig_obc; i < aig_obcj; i++)
494 f << stringf("1\n");
495
496 for (int i = aig_obc; i < aig_obcj; i++)
497 f << stringf("%d\n", aig_outputs.at(i));
498
499 for (int i = aig_obcj; i < aig_obcjf; i++)
500 f << stringf("%d\n", aig_outputs.at(i));
501
502 for (int i = 0; i < aig_a; i++)
503 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
504 }
505 else
506 {
507 for (int i = 0; i < aig_obc; i++)
508 f << stringf("%d\n", aig_outputs.at(i));
509
510 for (int i = aig_obc; i < aig_obcj; i++)
511 f << stringf("1\n");
512
513 for (int i = aig_obc; i < aig_obcj; i++)
514 f << stringf("%d\n", aig_outputs.at(i));
515
516 for (int i = aig_obcj; i < aig_obcjf; i++)
517 f << stringf("%d\n", aig_outputs.at(i));
518
519 for (int i = 0; i < aig_a; i++) {
520 int lhs = 2*(aig_i+aig_l+i)+2;
521 int rhs0 = aig_gates.at(i).first;
522 int rhs1 = aig_gates.at(i).second;
523 int delta0 = lhs - rhs0;
524 int delta1 = rhs0 - rhs1;
525 aiger_encode(f, delta0);
526 aiger_encode(f, delta1);
527 }
528 }
529
530 f << "c";
531
532 auto write_buffer = [](std::stringstream &buffer, int i32) {
533 int32_t i32_be = to_big_endian(i32);
534 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
535 };
536 std::stringstream h_buffer;
537 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
538 write_h_buffer(1);
539 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
540 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
541 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
542 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
543 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
544 write_h_buffer(input_bits.size() + ff_bits.size());
545 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
546 write_h_buffer(output_bits.size() + ff_bits.size());
547 log_debug("boxNum = %d\n", GetSize(box_list));
548 write_h_buffer(box_list.size());
549
550 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
551 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
552 };
553 std::stringstream i_buffer;
554 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
555 for (auto bit : input_bits)
556 write_i_buffer(arrival_times.at(bit, 0));
557 //std::stringstream o_buffer;
558 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
559 //for (auto bit : output_bits)
560 // write_o_buffer(0);
561
562 if (!box_list.empty() || !ff_bits.empty()) {
563 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
564 log_assert(holes_module);
565
566 dict<IdString, std::tuple<int,int,int>> cell_cache;
567
568 int box_count = 0;
569 for (auto cell : box_list) {
570 log_assert(cell);
571
572 RTLIL::Module* box_module = module->design->module(cell->type);
573 log_assert(box_module);
574
575 auto r = cell_cache.insert(cell->type);
576 auto &v = r.first->second;
577 if (r.second) {
578 int box_inputs = 0, box_outputs = 0;
579 for (auto port_name : box_module->ports) {
580 RTLIL::Wire *w = box_module->wire(port_name);
581 log_assert(w);
582 if (w->port_input)
583 box_inputs += GetSize(w);
584 if (w->port_output)
585 box_outputs += GetSize(w);
586 }
587
588 // For flops only, create an extra 1-bit input that drives a new wire
589 // called "<cell>.abc9_ff.Q" that is used below
590 if (box_module->get_bool_attribute("\\abc9_flop"))
591 box_inputs++;
592
593 std::get<0>(v) = box_inputs;
594 std::get<1>(v) = box_outputs;
595 std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
596 }
597
598 write_h_buffer(std::get<0>(v));
599 write_h_buffer(std::get<1>(v));
600 write_h_buffer(std::get<2>(v));
601 write_h_buffer(box_count++);
602 }
603
604 std::stringstream r_buffer;
605 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
606 log_debug("flopNum = %d\n", GetSize(ff_bits));
607 write_r_buffer(ff_bits.size());
608
609 std::stringstream s_buffer;
610 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
611 write_s_buffer(ff_bits.size());
612
613 for (const auto &i : ff_bits) {
614 const SigBit &d = i.first;
615 const Cell *cell = i.second;
616
617 int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
618 log_assert(mergeability > 0);
619 write_r_buffer(mergeability);
620
621 Const init = cell->attributes.at(ID(abc9_init));
622 log_assert(GetSize(init) == 1);
623 if (init == State::S1)
624 write_s_buffer(1);
625 else if (init == State::S0)
626 write_s_buffer(0);
627 else {
628 log_assert(init == State::Sx);
629 write_s_buffer(0);
630 }
631
632 write_i_buffer(arrival_times.at(d, 0));
633 //write_o_buffer(0);
634 }
635
636 f << "r";
637 std::string buffer_str = r_buffer.str();
638 int32_t buffer_size_be = to_big_endian(buffer_str.size());
639 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
640 f.write(buffer_str.data(), buffer_str.size());
641
642 f << "s";
643 buffer_str = s_buffer.str();
644 buffer_size_be = to_big_endian(buffer_str.size());
645 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
646 f.write(buffer_str.data(), buffer_str.size());
647
648 if (holes_module) {
649 std::stringstream a_buffer;
650 XAigerWriter writer(holes_module, true /* holes_mode */);
651 writer.write_aiger(a_buffer, false /*ascii_mode*/);
652
653 f << "a";
654 std::string buffer_str = a_buffer.str();
655 int32_t buffer_size_be = to_big_endian(buffer_str.size());
656 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
657 f.write(buffer_str.data(), buffer_str.size());
658 }
659 }
660
661 f << "h";
662 std::string buffer_str = h_buffer.str();
663 int32_t buffer_size_be = to_big_endian(buffer_str.size());
664 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
665 f.write(buffer_str.data(), buffer_str.size());
666
667 f << "i";
668 buffer_str = i_buffer.str();
669 buffer_size_be = to_big_endian(buffer_str.size());
670 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
671 f.write(buffer_str.data(), buffer_str.size());
672 //f << "o";
673 //buffer_str = o_buffer.str();
674 //buffer_size_be = to_big_endian(buffer_str.size());
675 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
676 //f.write(buffer_str.data(), buffer_str.size());
677
678 f << stringf("Generated by %s\n", yosys_version_str);
679
680 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
681 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
682 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
683 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
684 }
685
686 void write_map(std::ostream &f)
687 {
688 dict<int, string> input_lines;
689 dict<int, string> output_lines;
690
691 for (auto wire : module->wires())
692 {
693 SigSpec sig = sigmap(wire);
694
695 for (int i = 0; i < GetSize(wire); i++)
696 {
697 RTLIL::SigBit b(wire, i);
698 if (input_bits.count(b)) {
699 int a = aig_map.at(b);
700 log_assert((a & 1) == 0);
701 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
702 }
703
704 if (output_bits.count(b)) {
705 int o = ordered_outputs.at(b);
706 int init = 2;
707 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
708 continue;
709 }
710 }
711 }
712
713 input_lines.sort();
714 for (auto &it : input_lines)
715 f << it.second;
716 log_assert(input_lines.size() == input_bits.size());
717
718 int box_count = 0;
719 for (auto cell : box_list)
720 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
721
722 output_lines.sort();
723 for (auto &it : output_lines)
724 f << it.second;
725 log_assert(output_lines.size() == output_bits.size());
726 }
727 };
728
729 struct XAigerBackend : public Backend {
730 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
731 void help() YS_OVERRIDE
732 {
733 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
734 log("\n");
735 log(" write_xaiger [options] [filename]\n");
736 log("\n");
737 log("Write the top module (according to the (* top *) attribute or if only one module\n");
738 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
739 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
740 log("pseudo-outputs.\n");
741 log("\n");
742 log(" -ascii\n");
743 log(" write ASCII version of AIGER format\n");
744 log("\n");
745 log(" -map <filename>\n");
746 log(" write an extra file with port and box symbols\n");
747 log("\n");
748 }
749 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
750 {
751 bool ascii_mode = false;
752 std::string map_filename;
753
754 log_header(design, "Executing XAIGER backend.\n");
755
756 size_t argidx;
757 for (argidx = 1; argidx < args.size(); argidx++)
758 {
759 if (args[argidx] == "-ascii") {
760 ascii_mode = true;
761 continue;
762 }
763 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
764 map_filename = args[++argidx];
765 continue;
766 }
767 break;
768 }
769 extra_args(f, filename, args, argidx, !ascii_mode);
770
771 Module *top_module = design->top_module();
772
773 if (top_module == nullptr)
774 log_error("Can't find top module in current design!\n");
775
776 if (!design->selected_whole_module(top_module))
777 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
778
779 if (!top_module->processes.empty())
780 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
781 if (!top_module->memories.empty())
782 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
783
784 XAigerWriter writer(top_module);
785 writer.write_aiger(*f, ascii_mode);
786
787 if (!map_filename.empty()) {
788 std::ofstream mapf;
789 mapf.open(map_filename.c_str(), std::ofstream::trunc);
790 if (mapf.fail())
791 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
792 writer.write_map(mapf);
793 }
794 }
795 } XAigerBackend;
796
797 PRIVATE_NAMESPACE_END