2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 // https://stackoverflow.com/a/46137633
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
32 inline static uint32_t bswap32(uint32_t x
)
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value
= number_to_be_reversed
;
36 uint8_t lolo
= (value
>> 0) & 0xFF;
37 uint8_t lohi
= (value
>> 8) & 0xFF;
38 uint8_t hilo
= (value
>> 16) & 0xFF;
39 uint8_t hihi
= (value
>> 24) & 0xFF;
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
52 PRIVATE_NAMESPACE_BEGIN
54 inline int32_t to_big_endian(int32_t i32
) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
60 #error "Unknown endianness"
64 void aiger_encode(std::ostream
&f
, int x
)
69 f
.put((x
& 0x7f) | 0x80);
81 pool
<SigBit
> input_bits
, output_bits
;
82 dict
<SigBit
, SigBit
> not_map
, alias_map
;
83 dict
<SigBit
, pair
<SigBit
, SigBit
>> and_map
;
84 vector
<SigBit
> ci_bits
, co_bits
;
85 dict
<SigBit
, Cell
*> ff_bits
;
86 dict
<SigBit
, float> arrival_times
;
88 vector
<pair
<int, int>> aig_gates
;
89 vector
<int> aig_outputs
;
90 int aig_m
= 0, aig_i
= 0, aig_l
= 0, aig_o
= 0, aig_a
= 0;
92 dict
<SigBit
, int> aig_map
;
93 dict
<SigBit
, int> ordered_outputs
;
95 vector
<Cell
*> box_list
;
97 int mkgate(int a0
, int a1
)
100 aig_gates
.push_back(a0
> a1
? make_pair(a0
, a1
) : make_pair(a1
, a0
));
104 int bit2aig(SigBit bit
)
106 auto it
= aig_map
.find(bit
);
107 if (it
!= aig_map
.end()) {
108 log_assert(it
->second
>= 0);
112 // NB: Cannot use iterator returned from aig_map.insert()
113 // since this function is called recursively
116 if (not_map
.count(bit
)) {
117 a
= bit2aig(not_map
.at(bit
)) ^ 1;
119 if (and_map
.count(bit
)) {
120 auto args
= and_map
.at(bit
);
121 int a0
= bit2aig(args
.first
);
122 int a1
= bit2aig(args
.second
);
125 if (alias_map
.count(bit
)) {
126 a
= bit2aig(alias_map
.at(bit
));
129 if (bit
== State::Sx
|| bit
== State::Sz
) {
130 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
131 a
= aig_map
.at(State::S0
);
139 XAigerWriter(Module
*module
, bool holes_mode
=false) : module(module
), sigmap(module
)
141 pool
<SigBit
> undriven_bits
;
142 pool
<SigBit
> unused_bits
;
144 // promote public wires
145 for (auto wire
: module
->wires())
146 if (wire
->name
[0] == '\\')
149 // promote input wires
150 for (auto wire
: module
->wires())
151 if (wire
->port_input
)
154 // promote keep wires
155 for (auto wire
: module
->wires())
156 if (wire
->get_bool_attribute(ID::keep
))
159 for (auto wire
: module
->wires())
160 for (int i
= 0; i
< GetSize(wire
); i
++)
162 SigBit
wirebit(wire
, i
);
163 SigBit bit
= sigmap(wirebit
);
165 if (bit
.wire
== nullptr) {
166 if (wire
->port_output
) {
167 aig_map
[wirebit
] = (bit
== State::S1
) ? 1 : 0;
168 output_bits
.insert(wirebit
);
173 undriven_bits
.insert(bit
);
174 unused_bits
.insert(bit
);
176 bool keep
= wire
->get_bool_attribute(ID::keep
);
177 if (wire
->port_input
|| keep
)
178 input_bits
.insert(bit
);
180 if (wire
->port_output
|| keep
) {
182 alias_map
[wirebit
] = bit
;
183 output_bits
.insert(wirebit
);
187 dict
<IdString
,dict
<IdString
,int>> arrival_cache
;
188 for (auto cell
: module
->cells()) {
189 RTLIL::Module
* inst_module
= module
->design
->module(cell
->type
);
190 if (!cell
->has_keep_attr()) {
191 if (cell
->type
== "$_NOT_")
193 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
194 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
195 unused_bits
.erase(A
);
196 undriven_bits
.erase(Y
);
201 if (cell
->type
== "$_AND_")
203 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
204 SigBit B
= sigmap(cell
->getPort("\\B").as_bit());
205 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
206 unused_bits
.erase(A
);
207 unused_bits
.erase(B
);
208 undriven_bits
.erase(Y
);
209 and_map
[Y
] = make_pair(A
, B
);
213 if (cell
->type
== "$__ABC9_FF_" &&
214 // The presence of an abc9_mergeability attribute indicates
215 // that we do want to pass this flop to ABC
216 cell
->attributes
.count("\\abc9_mergeability"))
218 SigBit D
= sigmap(cell
->getPort("\\D").as_bit());
219 SigBit Q
= sigmap(cell
->getPort("\\Q").as_bit());
220 unused_bits
.erase(D
);
221 undriven_bits
.erase(Q
);
223 auto r
YS_ATTRIBUTE(unused
) = ff_bits
.insert(std::make_pair(D
, cell
));
224 log_assert(r
.second
);
229 auto it
= cell
->attributes
.find("\\abc9_box_seq");
230 if (it
!= cell
->attributes
.end()) {
231 int abc9_box_seq
= it
->second
.as_int();
232 if (GetSize(box_list
) <= abc9_box_seq
)
233 box_list
.resize(abc9_box_seq
+1);
234 box_list
[abc9_box_seq
] = cell
;
235 // Only flop boxes may have arrival times
236 if (!inst_module
->get_bool_attribute("\\abc9_flop"))
240 auto &cell_arrivals
= arrival_cache
[cell
->type
];
241 for (const auto &conn
: cell
->connections()) {
242 auto r
= cell_arrivals
.insert(conn
.first
);
243 auto &arrival
= r
.first
->second
;
245 auto port_wire
= inst_module
->wire(conn
.first
);
246 if (port_wire
->port_output
) {
247 auto it
= port_wire
->attributes
.find("\\abc9_arrival");
248 if (it
!= port_wire
->attributes
.end()) {
249 if (it
->second
.flags
!= 0)
250 log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire
), log_id(cell
->type
));
251 arrival
= it
->second
.as_int();
256 for (auto bit
: sigmap(conn
.second
))
257 arrival_times
[bit
] = arrival
;
262 bool cell_known
= inst_module
|| cell
->known();
263 for (const auto &c
: cell
->connections()) {
264 if (c
.second
.is_fully_const()) continue;
265 auto port_wire
= inst_module
? inst_module
->wire(c
.first
) : nullptr;
266 auto is_input
= (port_wire
&& port_wire
->port_input
) || !cell_known
|| cell
->input(c
.first
);
267 auto is_output
= (port_wire
&& port_wire
->port_output
) || !cell_known
|| cell
->output(c
.first
);
268 if (!is_input
&& !is_output
)
269 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c
.first
), log_id(cell
), log_id(cell
->type
));
272 for (auto b
: c
.second
) {
275 // Do not add as PO if bit is already a PI
276 if (input_bits
.count(b
))
278 if (!w
->port_output
|| !cell_known
) {
279 SigBit I
= sigmap(b
);
282 output_bits
.insert(b
);
287 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
290 dict
<IdString
, std::vector
<IdString
>> box_ports
;
291 for (auto cell
: box_list
) {
294 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
295 log_assert(box_module
);
296 log_assert(box_module
->attributes
.count("\\abc9_box_id"));
298 auto r
= box_ports
.insert(cell
->type
);
300 // Make carry in the last PI, and carry out the last PO
301 // since ABC requires it this way
302 IdString carry_in
, carry_out
;
303 for (const auto &port_name
: box_module
->ports
) {
304 auto w
= box_module
->wire(port_name
);
306 if (w
->get_bool_attribute("\\abc9_carry")) {
308 if (carry_in
!= IdString())
309 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module
));
310 carry_in
= port_name
;
312 if (w
->port_output
) {
313 if (carry_out
!= IdString())
314 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module
));
315 carry_out
= port_name
;
319 r
.first
->second
.push_back(port_name
);
322 if (carry_in
!= IdString() && carry_out
== IdString())
323 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module
));
324 if (carry_in
== IdString() && carry_out
!= IdString())
325 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module
));
326 if (carry_in
!= IdString()) {
327 r
.first
->second
.push_back(carry_in
);
328 r
.first
->second
.push_back(carry_out
);
332 // Fully pad all unused input connections of this box cell with S0
333 // Fully pad all undriven output connections of this box cell with anonymous wires
334 for (auto port_name
: r
.first
->second
) {
335 auto w
= box_module
->wire(port_name
);
337 auto rhs
= cell
->getPort(port_name
);
340 SigBit I
= sigmap(b
);
345 alias_map
[b
] = State::S0
;
349 co_bits
.emplace_back(b
);
350 unused_bits
.erase(I
);
353 for (const auto &b
: rhs
.bits()) {
354 SigBit O
= sigmap(b
);
357 ci_bits
.emplace_back(b
);
358 undriven_bits
.erase(O
);
362 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
363 if (box_module
->get_bool_attribute("\\abc9_flop")) {
364 SigSpec rhs
= module
->wire(stringf("%s.abc9_ff.Q", cell
->name
.c_str()));
366 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell
), log_id(module
));
369 SigBit I
= sigmap(b
);
374 alias_map
[b
] = State::S0
;
378 co_bits
.emplace_back(b
);
379 unused_bits
.erase(I
);
384 for (auto bit
: input_bits
)
385 undriven_bits
.erase(bit
);
386 for (auto bit
: output_bits
)
387 unused_bits
.erase(sigmap(bit
));
388 for (auto bit
: unused_bits
)
389 undriven_bits
.erase(bit
);
391 // Make all undriven bits a primary input
392 for (auto bit
: undriven_bits
) {
393 input_bits
.insert(bit
);
394 undriven_bits
.erase(bit
);
398 struct sort_by_port_id
{
399 bool operator()(const RTLIL::SigBit
& a
, const RTLIL::SigBit
& b
) const {
400 return a
.wire
->port_id
< b
.wire
->port_id
||
401 (a
.wire
->port_id
== b
.wire
->port_id
&& a
.offset
< b
.offset
);
404 input_bits
.sort(sort_by_port_id());
405 output_bits
.sort(sort_by_port_id());
408 aig_map
[State::S0
] = 0;
409 aig_map
[State::S1
] = 1;
411 for (const auto &bit
: input_bits
) {
413 log_assert(!aig_map
.count(bit
));
414 aig_map
[bit
] = 2*aig_m
;
417 for (const auto &i
: ff_bits
) {
418 const Cell
*cell
= i
.second
;
419 const SigBit
&q
= sigmap(cell
->getPort("\\Q"));
421 log_assert(!aig_map
.count(q
));
422 aig_map
[q
] = 2*aig_m
;
425 for (auto &bit
: ci_bits
) {
427 log_assert(!aig_map
.count(bit
));
428 aig_map
[bit
] = 2*aig_m
;
431 for (auto bit
: co_bits
) {
432 ordered_outputs
[bit
] = aig_o
++;
433 aig_outputs
.push_back(bit2aig(bit
));
436 for (const auto &bit
: output_bits
) {
437 ordered_outputs
[bit
] = aig_o
++;
439 // Unlike bit2aig() which checks aig_map first, for
440 // inout/keep bits, since aig_map will point to
441 // the PI, first attempt to find the NOT/AND driver
442 // before resorting to an aig_map lookup (which
443 // could be another PO)
444 if (input_bits
.count(bit
)) {
445 if (not_map
.count(bit
)) {
446 aig
= bit2aig(not_map
.at(bit
)) ^ 1;
447 } else if (and_map
.count(bit
)) {
448 auto args
= and_map
.at(bit
);
449 int a0
= bit2aig(args
.first
);
450 int a1
= bit2aig(args
.second
);
451 aig
= mkgate(a0
, a1
);
454 aig
= aig_map
.at(bit
);
458 aig_outputs
.push_back(aig
);
461 for (auto &i
: ff_bits
) {
462 const SigBit
&d
= i
.first
;
464 aig_outputs
.push_back(aig_map
.at(d
));
468 void write_aiger(std::ostream
&f
, bool ascii_mode
)
471 int aig_obcj
= aig_obc
;
472 int aig_obcjf
= aig_obcj
;
474 log_assert(aig_m
== aig_i
+ aig_l
+ aig_a
);
475 log_assert(aig_obcjf
== GetSize(aig_outputs
));
477 f
<< stringf("%s %d %d %d %d %d", ascii_mode
? "aag" : "aig", aig_m
, aig_i
, aig_l
, aig_o
, aig_a
);
482 for (int i
= 0; i
< aig_i
; i
++)
483 f
<< stringf("%d\n", 2*i
+2);
485 for (int i
= 0; i
< aig_obc
; i
++)
486 f
<< stringf("%d\n", aig_outputs
.at(i
));
488 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
491 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
492 f
<< stringf("%d\n", aig_outputs
.at(i
));
494 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
495 f
<< stringf("%d\n", aig_outputs
.at(i
));
497 for (int i
= 0; i
< aig_a
; i
++)
498 f
<< stringf("%d %d %d\n", 2*(aig_i
+aig_l
+i
)+2, aig_gates
.at(i
).first
, aig_gates
.at(i
).second
);
502 for (int i
= 0; i
< aig_obc
; i
++)
503 f
<< stringf("%d\n", aig_outputs
.at(i
));
505 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
508 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
509 f
<< stringf("%d\n", aig_outputs
.at(i
));
511 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
512 f
<< stringf("%d\n", aig_outputs
.at(i
));
514 for (int i
= 0; i
< aig_a
; i
++) {
515 int lhs
= 2*(aig_i
+aig_l
+i
)+2;
516 int rhs0
= aig_gates
.at(i
).first
;
517 int rhs1
= aig_gates
.at(i
).second
;
518 int delta0
= lhs
- rhs0
;
519 int delta1
= rhs0
- rhs1
;
520 aiger_encode(f
, delta0
);
521 aiger_encode(f
, delta1
);
527 auto write_buffer
= [](std::stringstream
&buffer
, int i32
) {
528 int32_t i32_be
= to_big_endian(i32
);
529 buffer
.write(reinterpret_cast<const char*>(&i32_be
), sizeof(i32_be
));
531 std::stringstream h_buffer
;
532 auto write_h_buffer
= std::bind(write_buffer
, std::ref(h_buffer
), std::placeholders::_1
);
534 log_debug("ciNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
) + GetSize(ci_bits
));
535 write_h_buffer(input_bits
.size() + ff_bits
.size() + ci_bits
.size());
536 log_debug("coNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
) + GetSize(co_bits
));
537 write_h_buffer(output_bits
.size() + GetSize(ff_bits
) + GetSize(co_bits
));
538 log_debug("piNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
));
539 write_h_buffer(input_bits
.size() + ff_bits
.size());
540 log_debug("poNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
));
541 write_h_buffer(output_bits
.size() + ff_bits
.size());
542 log_debug("boxNum = %d\n", GetSize(box_list
));
543 write_h_buffer(box_list
.size());
545 auto write_buffer_float
= [](std::stringstream
&buffer
, float f32
) {
546 buffer
.write(reinterpret_cast<const char*>(&f32
), sizeof(f32
));
548 std::stringstream i_buffer
;
549 auto write_i_buffer
= std::bind(write_buffer_float
, std::ref(i_buffer
), std::placeholders::_1
);
550 for (auto bit
: input_bits
)
551 write_i_buffer(arrival_times
.at(bit
, 0));
552 //std::stringstream o_buffer;
553 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
554 //for (auto bit : output_bits)
555 // write_o_buffer(0);
557 if (!box_list
.empty() || !ff_bits
.empty()) {
558 RTLIL::Module
*holes_module
= module
->design
->module(stringf("%s$holes", module
->name
.c_str()));
559 log_assert(holes_module
);
561 dict
<IdString
, std::tuple
<int,int,int>> cell_cache
;
564 for (auto cell
: box_list
) {
567 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
568 log_assert(box_module
);
570 auto r
= cell_cache
.insert(cell
->type
);
571 auto &v
= r
.first
->second
;
573 int box_inputs
= 0, box_outputs
= 0;
574 for (auto port_name
: box_module
->ports
) {
575 RTLIL::Wire
*w
= box_module
->wire(port_name
);
578 box_inputs
+= GetSize(w
);
580 box_outputs
+= GetSize(w
);
583 // For flops only, create an extra 1-bit input that drives a new wire
584 // called "<cell>.abc9_ff.Q" that is used below
585 if (box_module
->get_bool_attribute("\\abc9_flop"))
588 std::get
<0>(v
) = box_inputs
;
589 std::get
<1>(v
) = box_outputs
;
590 std::get
<2>(v
) = box_module
->attributes
.at("\\abc9_box_id").as_int();
593 write_h_buffer(std::get
<0>(v
));
594 write_h_buffer(std::get
<1>(v
));
595 write_h_buffer(std::get
<2>(v
));
596 write_h_buffer(box_count
++);
599 std::stringstream r_buffer
;
600 auto write_r_buffer
= std::bind(write_buffer
, std::ref(r_buffer
), std::placeholders::_1
);
601 log_debug("flopNum = %d\n", GetSize(ff_bits
));
602 write_r_buffer(ff_bits
.size());
604 std::stringstream s_buffer
;
605 auto write_s_buffer
= std::bind(write_buffer
, std::ref(s_buffer
), std::placeholders::_1
);
606 write_s_buffer(ff_bits
.size());
608 for (const auto &i
: ff_bits
) {
609 const SigBit
&d
= i
.first
;
610 const Cell
*cell
= i
.second
;
612 int mergeability
= cell
->attributes
.at(ID(abc9_mergeability
)).as_int();
613 log_assert(mergeability
> 0);
614 write_r_buffer(mergeability
);
616 Const init
= cell
->attributes
.at(ID(abc9_init
));
617 log_assert(GetSize(init
) == 1);
618 if (init
== State::S1
)
620 else if (init
== State::S0
)
623 log_assert(init
== State::Sx
);
627 write_i_buffer(arrival_times
.at(d
, 0));
632 std::string buffer_str
= r_buffer
.str();
633 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
634 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
635 f
.write(buffer_str
.data(), buffer_str
.size());
638 buffer_str
= s_buffer
.str();
639 buffer_size_be
= to_big_endian(buffer_str
.size());
640 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
641 f
.write(buffer_str
.data(), buffer_str
.size());
644 std::stringstream a_buffer
;
645 XAigerWriter
writer(holes_module
, true /* holes_mode */);
646 writer
.write_aiger(a_buffer
, false /*ascii_mode*/);
649 std::string buffer_str
= a_buffer
.str();
650 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
651 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
652 f
.write(buffer_str
.data(), buffer_str
.size());
657 std::string buffer_str
= h_buffer
.str();
658 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
659 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
660 f
.write(buffer_str
.data(), buffer_str
.size());
663 buffer_str
= i_buffer
.str();
664 buffer_size_be
= to_big_endian(buffer_str
.size());
665 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
666 f
.write(buffer_str
.data(), buffer_str
.size());
668 //buffer_str = o_buffer.str();
669 //buffer_size_be = to_big_endian(buffer_str.size());
670 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
671 //f.write(buffer_str.data(), buffer_str.size());
673 f
<< stringf("Generated by %s\n", yosys_version_str
);
675 module
->design
->scratchpad_set_int("write_xaiger.num_ands", and_map
.size());
676 module
->design
->scratchpad_set_int("write_xaiger.num_wires", aig_map
.size());
677 module
->design
->scratchpad_set_int("write_xaiger.num_inputs", input_bits
.size());
678 module
->design
->scratchpad_set_int("write_xaiger.num_outputs", output_bits
.size());
681 void write_map(std::ostream
&f
)
683 dict
<int, string
> input_lines
;
684 dict
<int, string
> output_lines
;
686 for (auto wire
: module
->wires())
688 SigSpec sig
= sigmap(wire
);
690 for (int i
= 0; i
< GetSize(wire
); i
++)
692 RTLIL::SigBit
b(wire
, i
);
693 if (input_bits
.count(b
)) {
694 int a
= aig_map
.at(b
);
695 log_assert((a
& 1) == 0);
696 input_lines
[a
] += stringf("input %d %d %s\n", (a
>> 1)-1, i
, log_id(wire
));
699 if (output_bits
.count(b
)) {
700 int o
= ordered_outputs
.at(b
);
702 output_lines
[o
] += stringf("output %d %d %s %d\n", o
- GetSize(co_bits
), i
, log_id(wire
), init
);
709 for (auto &it
: input_lines
)
711 log_assert(input_lines
.size() == input_bits
.size());
714 for (auto cell
: box_list
)
715 f
<< stringf("box %d %d %s\n", box_count
++, 0, log_id(cell
->name
));
718 for (auto &it
: output_lines
)
720 log_assert(output_lines
.size() == output_bits
.size());
724 struct XAigerBackend
: public Backend
{
725 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
726 void help() YS_OVERRIDE
728 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
730 log(" write_xaiger [options] [filename]\n");
732 log("Write the top module (according to the (* top *) attribute or if only one module\n");
733 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
734 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
735 log("pseudo-outputs.\n");
738 log(" write ASCII version of AIGER format\n");
740 log(" -map <filename>\n");
741 log(" write an extra file with port and box symbols\n");
744 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
746 bool ascii_mode
= false;
747 std::string map_filename
;
749 log_header(design
, "Executing XAIGER backend.\n");
752 for (argidx
= 1; argidx
< args
.size(); argidx
++)
754 if (args
[argidx
] == "-ascii") {
758 if (map_filename
.empty() && args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
759 map_filename
= args
[++argidx
];
764 extra_args(f
, filename
, args
, argidx
, !ascii_mode
);
766 Module
*top_module
= design
->top_module();
768 if (top_module
== nullptr)
769 log_error("Can't find top module in current design!\n");
771 if (!design
->selected_whole_module(top_module
))
772 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module
));
774 if (!top_module
->processes
.empty())
775 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module
));
776 if (!top_module
->memories
.empty())
777 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module
));
779 XAigerWriter
writer(top_module
);
780 writer
.write_aiger(*f
, ascii_mode
);
782 if (!map_filename
.empty()) {
784 mapf
.open(map_filename
.c_str(), std::ofstream::trunc
);
786 log_error("Can't open file `%s' for writing: %s\n", map_filename
.c_str(), strerror(errno
));
787 writer
.write_map(mapf
);
792 PRIVATE_NAMESPACE_END