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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50
51 USING_YOSYS_NAMESPACE
52 PRIVATE_NAMESPACE_BEGIN
53
54 inline int32_t to_big_endian(int32_t i32) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
56 return bswap32(i32);
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
58 return i32;
59 #else
60 #error "Unknown endianness"
61 #endif
62 }
63
64 void aiger_encode(std::ostream &f, int x)
65 {
66 log_assert(x >= 0);
67
68 while (x & ~0x7f) {
69 f.put((x & 0x7f) | 0x80);
70 x = x >> 7;
71 }
72
73 f.put(x);
74 }
75
76 struct XAigerWriter
77 {
78 Module *module;
79 SigMap sigmap;
80
81 pool<SigBit> input_bits, output_bits;
82 dict<SigBit, SigBit> not_map, alias_map;
83 dict<SigBit, pair<SigBit, SigBit>> and_map;
84 vector<SigBit> ci_bits, co_bits;
85 dict<SigBit, Cell*> ff_bits;
86 dict<SigBit, float> arrival_times;
87
88 vector<pair<int, int>> aig_gates;
89 vector<int> aig_outputs;
90 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
91
92 dict<SigBit, int> aig_map;
93 dict<SigBit, int> ordered_outputs;
94
95 vector<Cell*> box_list;
96
97 int mkgate(int a0, int a1)
98 {
99 aig_m++, aig_a++;
100 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
101 return 2*aig_m;
102 }
103
104 int bit2aig(SigBit bit)
105 {
106 auto it = aig_map.find(bit);
107 if (it != aig_map.end()) {
108 log_assert(it->second >= 0);
109 return it->second;
110 }
111
112 // NB: Cannot use iterator returned from aig_map.insert()
113 // since this function is called recursively
114
115 int a = -1;
116 if (not_map.count(bit)) {
117 a = bit2aig(not_map.at(bit)) ^ 1;
118 } else
119 if (and_map.count(bit)) {
120 auto args = and_map.at(bit);
121 int a0 = bit2aig(args.first);
122 int a1 = bit2aig(args.second);
123 a = mkgate(a0, a1);
124 } else
125 if (alias_map.count(bit)) {
126 a = bit2aig(alias_map.at(bit));
127 }
128
129 if (bit == State::Sx || bit == State::Sz) {
130 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
131 a = aig_map.at(State::S0);
132 }
133
134 log_assert(a >= 0);
135 aig_map[bit] = a;
136 return a;
137 }
138
139 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
140 {
141 pool<SigBit> undriven_bits;
142 pool<SigBit> unused_bits;
143
144 // promote public wires
145 for (auto wire : module->wires())
146 if (wire->name[0] == '\\')
147 sigmap.add(wire);
148
149 // promote input wires
150 for (auto wire : module->wires())
151 if (wire->port_input)
152 sigmap.add(wire);
153
154 // promote keep wires
155 for (auto wire : module->wires())
156 if (wire->get_bool_attribute(ID::keep))
157 sigmap.add(wire);
158
159 for (auto wire : module->wires())
160 for (int i = 0; i < GetSize(wire); i++)
161 {
162 SigBit wirebit(wire, i);
163 SigBit bit = sigmap(wirebit);
164
165 if (bit.wire == nullptr) {
166 if (wire->port_output) {
167 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
168 output_bits.insert(wirebit);
169 }
170 continue;
171 }
172
173 undriven_bits.insert(bit);
174 unused_bits.insert(bit);
175
176 bool keep = wire->get_bool_attribute(ID::keep);
177 if (wire->port_input || keep)
178 input_bits.insert(bit);
179
180 if (wire->port_output || keep) {
181 if (bit != wirebit)
182 alias_map[wirebit] = bit;
183 output_bits.insert(wirebit);
184 }
185 }
186
187 dict<IdString,dict<IdString,int>> arrival_cache;
188 for (auto cell : module->cells()) {
189 RTLIL::Module* inst_module = module->design->module(cell->type);
190 if (!cell->has_keep_attr()) {
191 if (cell->type == "$_NOT_")
192 {
193 SigBit A = sigmap(cell->getPort("\\A").as_bit());
194 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
195 unused_bits.erase(A);
196 undriven_bits.erase(Y);
197 not_map[Y] = A;
198 continue;
199 }
200
201 if (cell->type == "$_AND_")
202 {
203 SigBit A = sigmap(cell->getPort("\\A").as_bit());
204 SigBit B = sigmap(cell->getPort("\\B").as_bit());
205 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
206 unused_bits.erase(A);
207 unused_bits.erase(B);
208 undriven_bits.erase(Y);
209 and_map[Y] = make_pair(A, B);
210 continue;
211 }
212
213 if (cell->type == "$__ABC9_FF_" &&
214 // The presence of an abc9_mergeability attribute indicates
215 // that we do want to pass this flop to ABC
216 cell->attributes.count("\\abc9_mergeability"))
217 {
218 SigBit D = sigmap(cell->getPort("\\D").as_bit());
219 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
220 unused_bits.erase(D);
221 undriven_bits.erase(Q);
222 alias_map[Q] = D;
223 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
224 log_assert(r.second);
225 continue;
226 }
227
228 if (inst_module) {
229 bool abc9_flop = false;
230 auto it = cell->attributes.find("\\abc9_box_seq");
231 if (it != cell->attributes.end()) {
232 int abc9_box_seq = it->second.as_int();
233 if (GetSize(box_list) <= abc9_box_seq)
234 box_list.resize(abc9_box_seq+1);
235 box_list[abc9_box_seq] = cell;
236 // Only flop boxes may have arrival times
237 abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
238 if (!abc9_flop)
239 continue;
240 }
241
242 auto &cell_arrivals = arrival_cache[cell->type];
243 for (const auto &conn : cell->connections()) {
244 auto r = cell_arrivals.insert(conn.first);
245 auto &arrival = r.first->second;
246 if (r.second) {
247 auto port_wire = inst_module->wire(conn.first);
248 if (port_wire->port_output) {
249 auto it = port_wire->attributes.find("\\abc9_arrival");
250 if (it != port_wire->attributes.end()) {
251 if (it->second.flags != 0)
252 log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
253 arrival = it->second.as_int();
254 }
255 }
256 }
257 if (arrival)
258 for (auto bit : sigmap(conn.second))
259 arrival_times[bit] = arrival;
260 }
261
262 if (abc9_flop)
263 continue;
264 }
265 }
266
267 bool cell_known = inst_module || cell->known();
268 for (const auto &c : cell->connections()) {
269 if (c.second.is_fully_const()) continue;
270 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
271 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
272 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
273 if (!is_input && !is_output)
274 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
275
276 if (is_input)
277 for (auto b : c.second) {
278 Wire *w = b.wire;
279 if (!w) continue;
280 // Do not add as PO if bit is already a PI
281 if (input_bits.count(b))
282 continue;
283 if (!w->port_output || !cell_known) {
284 SigBit I = sigmap(b);
285 if (I != b)
286 alias_map[b] = I;
287 output_bits.insert(b);
288 }
289 }
290 }
291
292 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
293 }
294
295 dict<IdString, std::vector<IdString>> box_ports;
296 for (auto cell : box_list) {
297 log_assert(cell);
298
299 RTLIL::Module* box_module = module->design->module(cell->type);
300 log_assert(box_module);
301 log_assert(box_module->attributes.count("\\abc9_box_id"));
302
303 auto r = box_ports.insert(cell->type);
304 if (r.second) {
305 // Make carry in the last PI, and carry out the last PO
306 // since ABC requires it this way
307 IdString carry_in, carry_out;
308 for (const auto &port_name : box_module->ports) {
309 auto w = box_module->wire(port_name);
310 log_assert(w);
311 if (w->get_bool_attribute("\\abc9_carry")) {
312 if (w->port_input) {
313 if (carry_in != IdString())
314 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
315 carry_in = port_name;
316 }
317 if (w->port_output) {
318 if (carry_out != IdString())
319 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
320 carry_out = port_name;
321 }
322 }
323 else
324 r.first->second.push_back(port_name);
325 }
326
327 if (carry_in != IdString() && carry_out == IdString())
328 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
329 if (carry_in == IdString() && carry_out != IdString())
330 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
331 if (carry_in != IdString()) {
332 r.first->second.push_back(carry_in);
333 r.first->second.push_back(carry_out);
334 }
335 }
336
337 for (auto port_name : r.first->second) {
338 auto w = box_module->wire(port_name);
339 log_assert(w);
340 auto rhs = cell->connections_.at(port_name, SigSpec());
341 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
342 if (w->port_input)
343 for (auto b : rhs) {
344 SigBit I = sigmap(b);
345 if (b == RTLIL::Sx)
346 b = State::S0;
347 else if (I != b) {
348 if (I == RTLIL::Sx)
349 alias_map[b] = State::S0;
350 else
351 alias_map[b] = I;
352 }
353 co_bits.emplace_back(b);
354 unused_bits.erase(I);
355 }
356 if (w->port_output)
357 for (const auto &b : rhs) {
358 SigBit O = sigmap(b);
359 if (O != b)
360 alias_map[O] = b;
361 ci_bits.emplace_back(b);
362 undriven_bits.erase(O);
363 // If PI and CI, then must be a (* keep *) wire
364 if (input_bits.erase(O)) {
365 log_assert(output_bits.count(O));
366 log_assert(O.wire->get_bool_attribute(ID::keep));
367 }
368 }
369 }
370
371 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
372 if (box_module->get_bool_attribute("\\abc9_flop")) {
373 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
374 if (rhs.empty())
375 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
376
377 for (auto b : rhs) {
378 SigBit I = sigmap(b);
379 if (b == RTLIL::Sx)
380 b = State::S0;
381 else if (I != b) {
382 if (I == RTLIL::Sx)
383 alias_map[b] = State::S0;
384 else
385 alias_map[b] = I;
386 }
387 co_bits.emplace_back(b);
388 unused_bits.erase(I);
389 }
390 }
391 }
392
393 for (auto bit : input_bits)
394 undriven_bits.erase(bit);
395 for (auto bit : output_bits)
396 unused_bits.erase(sigmap(bit));
397 for (auto bit : unused_bits)
398 undriven_bits.erase(bit);
399
400 // Make all undriven bits a primary input
401 for (auto bit : undriven_bits) {
402 input_bits.insert(bit);
403 undriven_bits.erase(bit);
404 }
405
406 if (holes_mode) {
407 struct sort_by_port_id {
408 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
409 return a.wire->port_id < b.wire->port_id ||
410 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
411 }
412 };
413 input_bits.sort(sort_by_port_id());
414 output_bits.sort(sort_by_port_id());
415 }
416
417 aig_map[State::S0] = 0;
418 aig_map[State::S1] = 1;
419
420 for (const auto &bit : input_bits) {
421 aig_m++, aig_i++;
422 log_assert(!aig_map.count(bit));
423 aig_map[bit] = 2*aig_m;
424 }
425
426 for (const auto &i : ff_bits) {
427 const Cell *cell = i.second;
428 const SigBit &q = sigmap(cell->getPort("\\Q"));
429 aig_m++, aig_i++;
430 log_assert(!aig_map.count(q));
431 aig_map[q] = 2*aig_m;
432 }
433
434 for (auto &bit : ci_bits) {
435 aig_m++, aig_i++;
436 // 1'bx may exist here due to a box output
437 // that has been padded to its full width
438 if (bit == State::Sx)
439 continue;
440 log_assert(!aig_map.count(bit));
441 aig_map[bit] = 2*aig_m;
442 }
443
444 for (auto bit : co_bits) {
445 ordered_outputs[bit] = aig_o++;
446 aig_outputs.push_back(bit2aig(bit));
447 }
448
449 for (const auto &bit : output_bits) {
450 ordered_outputs[bit] = aig_o++;
451 int aig;
452 // Unlike bit2aig() which checks aig_map first, for
453 // inout/keep bits, since aig_map will point to
454 // the PI, first attempt to find the NOT/AND driver
455 // before resorting to an aig_map lookup (which
456 // could be another PO)
457 if (input_bits.count(bit)) {
458 if (not_map.count(bit)) {
459 aig = bit2aig(not_map.at(bit)) ^ 1;
460 } else if (and_map.count(bit)) {
461 auto args = and_map.at(bit);
462 int a0 = bit2aig(args.first);
463 int a1 = bit2aig(args.second);
464 aig = mkgate(a0, a1);
465 }
466 else
467 aig = aig_map.at(bit);
468 }
469 else
470 aig = bit2aig(bit);
471 aig_outputs.push_back(aig);
472 }
473
474 for (auto &i : ff_bits) {
475 const SigBit &d = i.first;
476 aig_o++;
477 aig_outputs.push_back(aig_map.at(d));
478 }
479 }
480
481 void write_aiger(std::ostream &f, bool ascii_mode)
482 {
483 int aig_obc = aig_o;
484 int aig_obcj = aig_obc;
485 int aig_obcjf = aig_obcj;
486
487 log_assert(aig_m == aig_i + aig_l + aig_a);
488 log_assert(aig_obcjf == GetSize(aig_outputs));
489
490 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
491 f << stringf("\n");
492
493 if (ascii_mode)
494 {
495 for (int i = 0; i < aig_i; i++)
496 f << stringf("%d\n", 2*i+2);
497
498 for (int i = 0; i < aig_obc; i++)
499 f << stringf("%d\n", aig_outputs.at(i));
500
501 for (int i = aig_obc; i < aig_obcj; i++)
502 f << stringf("1\n");
503
504 for (int i = aig_obc; i < aig_obcj; i++)
505 f << stringf("%d\n", aig_outputs.at(i));
506
507 for (int i = aig_obcj; i < aig_obcjf; i++)
508 f << stringf("%d\n", aig_outputs.at(i));
509
510 for (int i = 0; i < aig_a; i++)
511 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
512 }
513 else
514 {
515 for (int i = 0; i < aig_obc; i++)
516 f << stringf("%d\n", aig_outputs.at(i));
517
518 for (int i = aig_obc; i < aig_obcj; i++)
519 f << stringf("1\n");
520
521 for (int i = aig_obc; i < aig_obcj; i++)
522 f << stringf("%d\n", aig_outputs.at(i));
523
524 for (int i = aig_obcj; i < aig_obcjf; i++)
525 f << stringf("%d\n", aig_outputs.at(i));
526
527 for (int i = 0; i < aig_a; i++) {
528 int lhs = 2*(aig_i+aig_l+i)+2;
529 int rhs0 = aig_gates.at(i).first;
530 int rhs1 = aig_gates.at(i).second;
531 int delta0 = lhs - rhs0;
532 int delta1 = rhs0 - rhs1;
533 aiger_encode(f, delta0);
534 aiger_encode(f, delta1);
535 }
536 }
537
538 f << "c";
539
540 auto write_buffer = [](std::stringstream &buffer, int i32) {
541 int32_t i32_be = to_big_endian(i32);
542 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
543 };
544 std::stringstream h_buffer;
545 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
546 write_h_buffer(1);
547 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
548 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
549 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
550 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
551 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
552 write_h_buffer(input_bits.size() + ff_bits.size());
553 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
554 write_h_buffer(output_bits.size() + ff_bits.size());
555 log_debug("boxNum = %d\n", GetSize(box_list));
556 write_h_buffer(box_list.size());
557
558 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
559 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
560 };
561 std::stringstream i_buffer;
562 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
563 for (auto bit : input_bits)
564 write_i_buffer(arrival_times.at(bit, 0));
565 //std::stringstream o_buffer;
566 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
567 //for (auto bit : output_bits)
568 // write_o_buffer(0);
569
570 if (!box_list.empty() || !ff_bits.empty()) {
571 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
572 log_assert(holes_module);
573
574 dict<IdString, std::tuple<int,int,int>> cell_cache;
575
576 int box_count = 0;
577 for (auto cell : box_list) {
578 log_assert(cell);
579
580 RTLIL::Module* box_module = module->design->module(cell->type);
581 log_assert(box_module);
582
583 auto r = cell_cache.insert(cell->type);
584 auto &v = r.first->second;
585 if (r.second) {
586 int box_inputs = 0, box_outputs = 0;
587 for (auto port_name : box_module->ports) {
588 RTLIL::Wire *w = box_module->wire(port_name);
589 log_assert(w);
590 if (w->port_input)
591 box_inputs += GetSize(w);
592 if (w->port_output)
593 box_outputs += GetSize(w);
594 }
595
596 // For flops only, create an extra 1-bit input that drives a new wire
597 // called "<cell>.abc9_ff.Q" that is used below
598 if (box_module->get_bool_attribute("\\abc9_flop"))
599 box_inputs++;
600
601 std::get<0>(v) = box_inputs;
602 std::get<1>(v) = box_outputs;
603 std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
604 }
605
606 write_h_buffer(std::get<0>(v));
607 write_h_buffer(std::get<1>(v));
608 write_h_buffer(std::get<2>(v));
609 write_h_buffer(box_count++);
610 }
611
612 std::stringstream r_buffer;
613 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
614 log_debug("flopNum = %d\n", GetSize(ff_bits));
615 write_r_buffer(ff_bits.size());
616
617 std::stringstream s_buffer;
618 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
619 write_s_buffer(ff_bits.size());
620
621 for (const auto &i : ff_bits) {
622 const SigBit &d = i.first;
623 const Cell *cell = i.second;
624
625 int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
626 log_assert(mergeability > 0);
627 write_r_buffer(mergeability);
628
629 Const init = cell->attributes.at(ID(abc9_init));
630 log_assert(GetSize(init) == 1);
631 if (init == State::S1)
632 write_s_buffer(1);
633 else if (init == State::S0)
634 write_s_buffer(0);
635 else {
636 log_assert(init == State::Sx);
637 write_s_buffer(0);
638 }
639
640 write_i_buffer(arrival_times.at(d, 0));
641 //write_o_buffer(0);
642 }
643
644 f << "r";
645 std::string buffer_str = r_buffer.str();
646 int32_t buffer_size_be = to_big_endian(buffer_str.size());
647 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
648 f.write(buffer_str.data(), buffer_str.size());
649
650 f << "s";
651 buffer_str = s_buffer.str();
652 buffer_size_be = to_big_endian(buffer_str.size());
653 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
654 f.write(buffer_str.data(), buffer_str.size());
655
656 if (holes_module) {
657 std::stringstream a_buffer;
658 XAigerWriter writer(holes_module, true /* holes_mode */);
659 writer.write_aiger(a_buffer, false /*ascii_mode*/);
660
661 f << "a";
662 std::string buffer_str = a_buffer.str();
663 int32_t buffer_size_be = to_big_endian(buffer_str.size());
664 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
665 f.write(buffer_str.data(), buffer_str.size());
666 }
667 }
668
669 f << "h";
670 std::string buffer_str = h_buffer.str();
671 int32_t buffer_size_be = to_big_endian(buffer_str.size());
672 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
673 f.write(buffer_str.data(), buffer_str.size());
674
675 f << "i";
676 buffer_str = i_buffer.str();
677 buffer_size_be = to_big_endian(buffer_str.size());
678 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
679 f.write(buffer_str.data(), buffer_str.size());
680 //f << "o";
681 //buffer_str = o_buffer.str();
682 //buffer_size_be = to_big_endian(buffer_str.size());
683 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
684 //f.write(buffer_str.data(), buffer_str.size());
685
686 f << stringf("Generated by %s\n", yosys_version_str);
687
688 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
689 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
690 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
691 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
692 }
693
694 void write_map(std::ostream &f)
695 {
696 dict<int, string> input_lines;
697 dict<int, string> output_lines;
698
699 for (auto wire : module->wires())
700 {
701 SigSpec sig = sigmap(wire);
702
703 for (int i = 0; i < GetSize(wire); i++)
704 {
705 RTLIL::SigBit b(wire, i);
706 if (input_bits.count(b)) {
707 int a = aig_map.at(b);
708 log_assert((a & 1) == 0);
709 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
710 }
711
712 if (output_bits.count(b)) {
713 int o = ordered_outputs.at(b);
714 int init = 2;
715 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
716 continue;
717 }
718 }
719 }
720
721 input_lines.sort();
722 for (auto &it : input_lines)
723 f << it.second;
724 log_assert(input_lines.size() == input_bits.size());
725
726 int box_count = 0;
727 for (auto cell : box_list)
728 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
729
730 output_lines.sort();
731 for (auto &it : output_lines)
732 f << it.second;
733 log_assert(output_lines.size() == output_bits.size());
734 }
735 };
736
737 struct XAigerBackend : public Backend {
738 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
739 void help() YS_OVERRIDE
740 {
741 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
742 log("\n");
743 log(" write_xaiger [options] [filename]\n");
744 log("\n");
745 log("Write the top module (according to the (* top *) attribute or if only one module\n");
746 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
747 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
748 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
749 log("module, if it exists.\n");
750 log("\n");
751 log(" -ascii\n");
752 log(" write ASCII version of AIGER format\n");
753 log("\n");
754 log(" -map <filename>\n");
755 log(" write an extra file with port and box symbols\n");
756 log("\n");
757 }
758 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
759 {
760 bool ascii_mode = false;
761 std::string map_filename;
762
763 log_header(design, "Executing XAIGER backend.\n");
764
765 size_t argidx;
766 for (argidx = 1; argidx < args.size(); argidx++)
767 {
768 if (args[argidx] == "-ascii") {
769 ascii_mode = true;
770 continue;
771 }
772 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
773 map_filename = args[++argidx];
774 continue;
775 }
776 break;
777 }
778 extra_args(f, filename, args, argidx, !ascii_mode);
779
780 Module *top_module = design->top_module();
781
782 if (top_module == nullptr)
783 log_error("Can't find top module in current design!\n");
784
785 if (!design->selected_whole_module(top_module))
786 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
787
788 if (!top_module->processes.empty())
789 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
790 if (!top_module->memories.empty())
791 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
792
793 XAigerWriter writer(top_module);
794 writer.write_aiger(*f, ascii_mode);
795
796 if (!map_filename.empty()) {
797 std::ofstream mapf;
798 mapf.open(map_filename.c_str(), std::ofstream::trunc);
799 if (mapf.fail())
800 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
801 writer.write_map(mapf);
802 }
803 }
804 } XAigerBackend;
805
806 PRIVATE_NAMESPACE_END