2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 // https://stackoverflow.com/a/46137633
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
32 inline static uint32_t bswap32(uint32_t x
)
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value
= number_to_be_reversed
;
36 uint8_t lolo
= (value
>> 0) & 0xFF;
37 uint8_t lohi
= (value
>> 8) & 0xFF;
38 uint8_t hilo
= (value
>> 16) & 0xFF;
39 uint8_t hihi
= (value
>> 24) & 0xFF;
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
52 PRIVATE_NAMESPACE_BEGIN
54 inline int32_t to_big_endian(int32_t i32
) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
60 #error "Unknown endianness"
64 void aiger_encode(std::ostream
&f
, int x
)
69 f
.put((x
& 0x7f) | 0x80);
81 pool
<SigBit
> input_bits
, output_bits
;
82 dict
<SigBit
, SigBit
> not_map
, alias_map
;
83 dict
<SigBit
, pair
<SigBit
, SigBit
>> and_map
;
84 vector
<SigBit
> ci_bits
, co_bits
;
85 dict
<SigBit
, Cell
*> ff_bits
;
86 dict
<SigBit
, float> arrival_times
;
88 vector
<pair
<int, int>> aig_gates
;
89 vector
<int> aig_outputs
;
90 int aig_m
= 0, aig_i
= 0, aig_l
= 0, aig_o
= 0, aig_a
= 0;
92 dict
<SigBit
, int> aig_map
;
93 dict
<SigBit
, int> ordered_outputs
;
95 vector
<Cell
*> box_list
;
96 dict
<IdString
, std::vector
<IdString
>> box_ports
;
98 int mkgate(int a0
, int a1
)
101 aig_gates
.push_back(a0
> a1
? make_pair(a0
, a1
) : make_pair(a1
, a0
));
105 int bit2aig(SigBit bit
)
107 auto it
= aig_map
.find(bit
);
108 if (it
!= aig_map
.end()) {
109 log_assert(it
->second
>= 0);
113 // NB: Cannot use iterator returned from aig_map.insert()
114 // since this function is called recursively
117 if (not_map
.count(bit
)) {
118 a
= bit2aig(not_map
.at(bit
)) ^ 1;
120 if (and_map
.count(bit
)) {
121 auto args
= and_map
.at(bit
);
122 int a0
= bit2aig(args
.first
);
123 int a1
= bit2aig(args
.second
);
126 if (alias_map
.count(bit
)) {
127 a
= bit2aig(alias_map
.at(bit
));
130 if (bit
== State::Sx
|| bit
== State::Sz
) {
131 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
132 a
= aig_map
.at(State::S0
);
140 XAigerWriter(Module
*module
, bool holes_mode
=false) : module(module
), sigmap(module
)
142 pool
<SigBit
> undriven_bits
;
143 pool
<SigBit
> unused_bits
;
145 // promote public wires
146 for (auto wire
: module
->wires())
147 if (wire
->name
[0] == '\\')
150 // promote input wires
151 for (auto wire
: module
->wires())
152 if (wire
->port_input
)
155 // promote keep wires
156 for (auto wire
: module
->wires())
157 if (wire
->get_bool_attribute(ID::keep
))
161 for (auto wire
: module
->wires())
162 for (int i
= 0; i
< GetSize(wire
); i
++)
164 SigBit
wirebit(wire
, i
);
165 SigBit bit
= sigmap(wirebit
);
167 if (bit
.wire
== nullptr) {
168 if (wire
->port_output
) {
169 aig_map
[wirebit
] = (bit
== State::S1
) ? 1 : 0;
170 output_bits
.insert(wirebit
);
175 undriven_bits
.insert(bit
);
176 unused_bits
.insert(bit
);
178 if (wire
->port_input
)
179 input_bits
.insert(bit
);
181 if (wire
->port_output
) {
183 alias_map
[wirebit
] = bit
;
184 output_bits
.insert(wirebit
);
188 for (auto cell
: module
->cells()) {
189 if (cell
->type
== "$_NOT_")
191 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
192 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
193 unused_bits
.erase(A
);
194 undriven_bits
.erase(Y
);
199 if (cell
->type
== "$_AND_")
201 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
202 SigBit B
= sigmap(cell
->getPort("\\B").as_bit());
203 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
204 unused_bits
.erase(A
);
205 unused_bits
.erase(B
);
206 undriven_bits
.erase(Y
);
207 and_map
[Y
] = make_pair(A
, B
);
211 if (cell
->type
== "$__ABC9_FF_" &&
212 // The presence of an abc9_mergeability attribute indicates
213 // that we do want to pass this flop to ABC
214 cell
->attributes
.count("\\abc9_mergeability"))
216 SigBit D
= sigmap(cell
->getPort("\\D").as_bit());
217 SigBit Q
= sigmap(cell
->getPort("\\Q").as_bit());
218 unused_bits
.erase(D
);
219 undriven_bits
.erase(Q
);
221 auto r
YS_ATTRIBUTE(unused
) = ff_bits
.insert(std::make_pair(D
, cell
));
222 log_assert(r
.second
);
226 RTLIL::Module
* inst_module
= module
->design
->module(cell
->type
);
228 auto it
= cell
->attributes
.find("\\abc9_box_seq");
229 if (it
!= cell
->attributes
.end()) {
230 int abc9_box_seq
= it
->second
.as_int();
231 if (GetSize(box_list
) <= abc9_box_seq
)
232 box_list
.resize(abc9_box_seq
+1);
233 box_list
[abc9_box_seq
] = cell
;
234 if (!inst_module
->get_bool_attribute("\\abc9_flop"))
238 for (const auto &conn
: cell
->connections()) {
239 auto port_wire
= inst_module
->wire(conn
.first
);
240 if (port_wire
->port_output
) {
242 auto it
= port_wire
->attributes
.find("\\abc9_arrival");
243 if (it
!= port_wire
->attributes
.end()) {
244 if (it
->second
.flags
!= 0)
245 log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire
), log_id(cell
->type
));
246 arrival
= it
->second
.as_int();
249 for (auto bit
: sigmap(conn
.second
))
250 arrival_times
[bit
] = arrival
;
255 bool cell_known
= inst_module
|| cell
->known();
256 for (const auto &c
: cell
->connections()) {
257 if (c
.second
.is_fully_const()) continue;
258 auto port_wire
= inst_module
? inst_module
->wire(c
.first
) : nullptr;
259 auto is_input
= (port_wire
&& port_wire
->port_input
) || !cell_known
|| cell
->input(c
.first
);
260 auto is_output
= (port_wire
&& port_wire
->port_output
) || !cell_known
|| cell
->output(c
.first
);
261 if (!is_input
&& !is_output
)
262 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c
.first
), log_id(cell
), log_id(cell
->type
));
265 for (auto b
: c
.second
) {
268 if (!w
->port_output
|| !cell_known
) {
269 SigBit I
= sigmap(b
);
272 output_bits
.insert(b
);
277 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
280 for (auto cell
: box_list
) {
283 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
284 log_assert(box_module
);
285 log_assert(box_module
->attributes
.count("\\abc9_box_id"));
287 auto r
= box_ports
.insert(cell
->type
);
289 // Make carry in the last PI, and carry out the last PO
290 // since ABC requires it this way
291 IdString carry_in
, carry_out
;
292 for (const auto &port_name
: box_module
->ports
) {
293 auto w
= box_module
->wire(port_name
);
295 if (w
->get_bool_attribute("\\abc9_carry")) {
297 if (carry_in
!= IdString())
298 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module
));
299 carry_in
= port_name
;
301 if (w
->port_output
) {
302 if (carry_out
!= IdString())
303 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module
));
304 carry_out
= port_name
;
308 r
.first
->second
.push_back(port_name
);
311 if (carry_in
!= IdString() && carry_out
== IdString())
312 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module
));
313 if (carry_in
== IdString() && carry_out
!= IdString())
314 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module
));
315 if (carry_in
!= IdString()) {
316 r
.first
->second
.push_back(carry_in
);
317 r
.first
->second
.push_back(carry_out
);
321 // Fully pad all unused input connections of this box cell with S0
322 // Fully pad all undriven output connections of this box cell with anonymous wires
323 for (auto port_name
: r
.first
->second
) {
324 auto w
= box_module
->wire(port_name
);
326 auto rhs
= cell
->getPort(port_name
);
329 SigBit I
= sigmap(b
);
334 alias_map
[b
] = State::S0
;
338 co_bits
.emplace_back(b
);
339 unused_bits
.erase(I
);
342 for (const auto &b
: rhs
.bits()) {
343 SigBit O
= sigmap(b
);
346 ci_bits
.emplace_back(b
);
347 undriven_bits
.erase(O
);
351 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
352 if (box_module
->get_bool_attribute("\\abc9_flop")) {
353 SigSpec rhs
= module
->wire(stringf("%s.abc9_ff.Q", cell
->name
.c_str()));
355 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell
), log_id(module
));
358 SigBit I
= sigmap(b
);
363 alias_map
[b
] = State::S0
;
367 co_bits
.emplace_back(b
);
368 unused_bits
.erase(I
);
373 for (auto bit
: input_bits
)
374 undriven_bits
.erase(bit
);
375 for (auto bit
: output_bits
)
376 unused_bits
.erase(sigmap(bit
));
377 for (auto bit
: unused_bits
)
378 undriven_bits
.erase(bit
);
380 // Make all undriven bits a primary input
381 for (auto bit
: undriven_bits
) {
382 input_bits
.insert(bit
);
383 undriven_bits
.erase(bit
);
387 struct sort_by_port_id
{
388 bool operator()(const RTLIL::SigBit
& a
, const RTLIL::SigBit
& b
) const {
389 return a
.wire
->port_id
< b
.wire
->port_id
;
392 input_bits
.sort(sort_by_port_id());
393 output_bits
.sort(sort_by_port_id());
396 aig_map
[State::S0
] = 0;
397 aig_map
[State::S1
] = 1;
399 for (const auto &bit
: input_bits
) {
401 log_assert(!aig_map
.count(bit
));
402 aig_map
[bit
] = 2*aig_m
;
405 for (const auto &i
: ff_bits
) {
406 const Cell
*cell
= i
.second
;
407 const SigBit
&q
= sigmap(cell
->getPort("\\Q"));
409 log_assert(!aig_map
.count(q
));
410 aig_map
[q
] = 2*aig_m
;
413 for (auto &bit
: ci_bits
) {
415 log_assert(!aig_map
.count(bit
));
416 aig_map
[bit
] = 2*aig_m
;
419 for (auto bit
: co_bits
) {
420 ordered_outputs
[bit
] = aig_o
++;
421 aig_outputs
.push_back(bit2aig(bit
));
424 for (const auto &bit
: output_bits
) {
425 ordered_outputs
[bit
] = aig_o
++;
426 aig_outputs
.push_back(bit2aig(bit
));
429 for (auto &i
: ff_bits
) {
430 const SigBit
&d
= i
.first
;
432 aig_outputs
.push_back(aig_map
.at(d
));
436 void write_aiger(std::ostream
&f
, bool ascii_mode
)
439 int aig_obcj
= aig_obc
;
440 int aig_obcjf
= aig_obcj
;
442 log_assert(aig_m
== aig_i
+ aig_l
+ aig_a
);
443 log_assert(aig_obcjf
== GetSize(aig_outputs
));
445 f
<< stringf("%s %d %d %d %d %d", ascii_mode
? "aag" : "aig", aig_m
, aig_i
, aig_l
, aig_o
, aig_a
);
450 for (int i
= 0; i
< aig_i
; i
++)
451 f
<< stringf("%d\n", 2*i
+2);
453 for (int i
= 0; i
< aig_obc
; i
++)
454 f
<< stringf("%d\n", aig_outputs
.at(i
));
456 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
459 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
460 f
<< stringf("%d\n", aig_outputs
.at(i
));
462 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
463 f
<< stringf("%d\n", aig_outputs
.at(i
));
465 for (int i
= 0; i
< aig_a
; i
++)
466 f
<< stringf("%d %d %d\n", 2*(aig_i
+aig_l
+i
)+2, aig_gates
.at(i
).first
, aig_gates
.at(i
).second
);
470 for (int i
= 0; i
< aig_obc
; i
++)
471 f
<< stringf("%d\n", aig_outputs
.at(i
));
473 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
476 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
477 f
<< stringf("%d\n", aig_outputs
.at(i
));
479 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
480 f
<< stringf("%d\n", aig_outputs
.at(i
));
482 for (int i
= 0; i
< aig_a
; i
++) {
483 int lhs
= 2*(aig_i
+aig_l
+i
)+2;
484 int rhs0
= aig_gates
.at(i
).first
;
485 int rhs1
= aig_gates
.at(i
).second
;
486 int delta0
= lhs
- rhs0
;
487 int delta1
= rhs0
- rhs1
;
488 aiger_encode(f
, delta0
);
489 aiger_encode(f
, delta1
);
495 auto write_buffer
= [](std::stringstream
&buffer
, int i32
) {
496 int32_t i32_be
= to_big_endian(i32
);
497 buffer
.write(reinterpret_cast<const char*>(&i32_be
), sizeof(i32_be
));
499 std::stringstream h_buffer
;
500 auto write_h_buffer
= std::bind(write_buffer
, std::ref(h_buffer
), std::placeholders::_1
);
502 log_debug("ciNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
) + GetSize(ci_bits
));
503 write_h_buffer(input_bits
.size() + ff_bits
.size() + ci_bits
.size());
504 log_debug("coNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
) + GetSize(co_bits
));
505 write_h_buffer(output_bits
.size() + GetSize(ff_bits
) + GetSize(co_bits
));
506 log_debug("piNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
));
507 write_h_buffer(input_bits
.size() + ff_bits
.size());
508 log_debug("poNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
));
509 write_h_buffer(output_bits
.size() + ff_bits
.size());
510 log_debug("boxNum = %d\n", GetSize(box_list
));
511 write_h_buffer(box_list
.size());
513 auto write_buffer_float
= [](std::stringstream
&buffer
, float f32
) {
514 buffer
.write(reinterpret_cast<const char*>(&f32
), sizeof(f32
));
516 std::stringstream i_buffer
;
517 auto write_i_buffer
= std::bind(write_buffer_float
, std::ref(i_buffer
), std::placeholders::_1
);
518 for (auto bit
: input_bits
)
519 write_i_buffer(arrival_times
.at(bit
, 0));
520 //std::stringstream o_buffer;
521 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
522 //for (auto bit : output_bits)
523 // write_o_buffer(0);
525 if (!box_list
.empty() || !ff_bits
.empty()) {
526 RTLIL::Module
*holes_module
= module
->design
->module(stringf("%s$holes", module
->name
.c_str()));
527 log_assert(holes_module
);
529 dict
<IdString
, Cell
*> cell_cache
;
532 for (auto cell
: box_list
) {
535 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
536 log_assert(box_module
);
538 int box_inputs
= 0, box_outputs
= 0;
539 for (auto port_name
: box_module
->ports
) {
540 RTLIL::Wire
*w
= box_module
->wire(port_name
);
543 box_inputs
+= GetSize(w
);
545 box_outputs
+= GetSize(w
);
548 // For flops only, create an extra 1-bit input that drives a new wire
549 // called "<cell>.abc9_ff.Q" that is used below
550 if (box_module
->get_bool_attribute("\\abc9_flop"))
553 write_h_buffer(box_inputs
);
554 write_h_buffer(box_outputs
);
555 write_h_buffer(box_module
->attributes
.at("\\abc9_box_id").as_int());
556 write_h_buffer(box_count
++);
559 std::stringstream r_buffer
;
560 auto write_r_buffer
= std::bind(write_buffer
, std::ref(r_buffer
), std::placeholders::_1
);
561 log_debug("flopNum = %d\n", GetSize(ff_bits
));
562 write_r_buffer(ff_bits
.size());
564 std::stringstream s_buffer
;
565 auto write_s_buffer
= std::bind(write_buffer
, std::ref(s_buffer
), std::placeholders::_1
);
566 write_s_buffer(ff_bits
.size());
568 for (const auto &i
: ff_bits
) {
569 const SigBit
&d
= i
.first
;
570 const Cell
*cell
= i
.second
;
572 int mergeability
= cell
->attributes
.at(ID(abc9_mergeability
)).as_int();
573 log_assert(mergeability
> 0);
574 write_r_buffer(mergeability
);
576 Const init
= cell
->attributes
.at(ID(abc9_init
));
577 log_assert(GetSize(init
) == 1);
578 if (init
== State::S1
)
580 else if (init
== State::S0
)
583 log_assert(init
== State::Sx
);
587 write_i_buffer(arrival_times
.at(d
, 0));
592 std::string buffer_str
= r_buffer
.str();
593 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
594 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
595 f
.write(buffer_str
.data(), buffer_str
.size());
598 buffer_str
= s_buffer
.str();
599 buffer_size_be
= to_big_endian(buffer_str
.size());
600 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
601 f
.write(buffer_str
.data(), buffer_str
.size());
604 std::stringstream a_buffer
;
605 XAigerWriter
writer(holes_module
, true /* holes_mode */);
606 writer
.write_aiger(a_buffer
, false /*ascii_mode*/);
609 std::string buffer_str
= a_buffer
.str();
610 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
611 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
612 f
.write(buffer_str
.data(), buffer_str
.size());
617 std::string buffer_str
= h_buffer
.str();
618 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
619 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
620 f
.write(buffer_str
.data(), buffer_str
.size());
623 buffer_str
= i_buffer
.str();
624 buffer_size_be
= to_big_endian(buffer_str
.size());
625 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
626 f
.write(buffer_str
.data(), buffer_str
.size());
628 //buffer_str = o_buffer.str();
629 //buffer_size_be = to_big_endian(buffer_str.size());
630 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
631 //f.write(buffer_str.data(), buffer_str.size());
633 f
<< stringf("Generated by %s\n", yosys_version_str
);
635 module
->design
->scratchpad_set_int("write_xaiger.num_ands", and_map
.size());
636 module
->design
->scratchpad_set_int("write_xaiger.num_wires", aig_map
.size());
637 module
->design
->scratchpad_set_int("write_xaiger.num_inputs", input_bits
.size());
638 module
->design
->scratchpad_set_int("write_xaiger.num_outputs", output_bits
.size());
641 void write_map(std::ostream
&f
)
643 dict
<int, string
> input_lines
;
644 dict
<int, string
> output_lines
;
646 for (auto wire
: module
->wires())
648 SigSpec sig
= sigmap(wire
);
650 for (int i
= 0; i
< GetSize(wire
); i
++)
652 RTLIL::SigBit
b(wire
, i
);
653 if (input_bits
.count(b
)) {
654 int a
= aig_map
.at(b
);
655 log_assert((a
& 1) == 0);
656 input_lines
[a
] += stringf("input %d %d %s\n", (a
>> 1)-1, i
, log_id(wire
));
659 if (output_bits
.count(b
)) {
660 int o
= ordered_outputs
.at(b
);
662 output_lines
[o
] += stringf("output %d %d %s %d\n", o
- GetSize(co_bits
), i
, log_id(wire
), init
);
669 for (auto &it
: input_lines
)
671 log_assert(input_lines
.size() == input_bits
.size());
674 for (auto cell
: box_list
)
675 f
<< stringf("box %d %d %s\n", box_count
++, 0, log_id(cell
->name
));
678 for (auto &it
: output_lines
)
680 log_assert(output_lines
.size() == output_bits
.size());
684 struct XAigerBackend
: public Backend
{
685 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
686 void help() YS_OVERRIDE
688 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
690 log(" write_xaiger [options] [filename]\n");
692 log("Write the top module (according to the (* top *) attribute or if only one module\n");
693 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
694 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
695 log("pseudo-outputs.\n");
698 log(" write ASCII version of AIGER format\n");
700 log(" -map <filename>\n");
701 log(" write an extra file with port and box symbols\n");
704 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
706 bool ascii_mode
= false;
707 std::string map_filename
;
709 log_header(design
, "Executing XAIGER backend.\n");
712 for (argidx
= 1; argidx
< args
.size(); argidx
++)
714 if (args
[argidx
] == "-ascii") {
718 if (map_filename
.empty() && args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
719 map_filename
= args
[++argidx
];
724 extra_args(f
, filename
, args
, argidx
, !ascii_mode
);
726 Module
*top_module
= design
->top_module();
728 if (top_module
== nullptr)
729 log_error("Can't find top module in current design!\n");
731 if (!design
->selected_whole_module(top_module
))
732 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module
));
734 if (!top_module
->processes
.empty())
735 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module
));
736 if (!top_module
->memories
.empty())
737 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module
));
739 XAigerWriter
writer(top_module
);
740 writer
.write_aiger(*f
, ascii_mode
);
742 if (!map_filename
.empty()) {
744 mapf
.open(map_filename
.c_str(), std::ofstream::trunc
);
746 log_error("Can't open file `%s' for writing: %s\n", map_filename
.c_str(), strerror(errno
));
747 writer
.write_map(mapf
);
752 PRIVATE_NAMESPACE_END