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Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50
51 USING_YOSYS_NAMESPACE
52 PRIVATE_NAMESPACE_BEGIN
53
54 inline int32_t to_big_endian(int32_t i32) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
56 return bswap32(i32);
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
58 return i32;
59 #else
60 #error "Unknown endianness"
61 #endif
62 }
63
64 void aiger_encode(std::ostream &f, int x)
65 {
66 log_assert(x >= 0);
67
68 while (x & ~0x7f) {
69 f.put((x & 0x7f) | 0x80);
70 x = x >> 7;
71 }
72
73 f.put(x);
74 }
75
76 struct XAigerWriter
77 {
78 Module *module;
79 SigMap sigmap;
80
81 pool<SigBit> input_bits, output_bits;
82 dict<SigBit, SigBit> not_map, alias_map;
83 dict<SigBit, pair<SigBit, SigBit>> and_map;
84 vector<SigBit> ci_bits, co_bits;
85 dict<SigBit, Cell*> ff_bits;
86 dict<SigBit, float> arrival_times;
87
88 vector<pair<int, int>> aig_gates;
89 vector<int> aig_outputs;
90 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
91
92 dict<SigBit, int> aig_map;
93 dict<SigBit, int> ordered_outputs;
94
95 vector<Cell*> box_list;
96
97 int mkgate(int a0, int a1)
98 {
99 aig_m++, aig_a++;
100 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
101 return 2*aig_m;
102 }
103
104 int bit2aig(SigBit bit)
105 {
106 auto it = aig_map.find(bit);
107 if (it != aig_map.end()) {
108 log_assert(it->second >= 0);
109 return it->second;
110 }
111
112 // NB: Cannot use iterator returned from aig_map.insert()
113 // since this function is called recursively
114
115 int a = -1;
116 if (not_map.count(bit)) {
117 a = bit2aig(not_map.at(bit)) ^ 1;
118 } else
119 if (and_map.count(bit)) {
120 auto args = and_map.at(bit);
121 int a0 = bit2aig(args.first);
122 int a1 = bit2aig(args.second);
123 a = mkgate(a0, a1);
124 } else
125 if (alias_map.count(bit)) {
126 a = bit2aig(alias_map.at(bit));
127 }
128
129 if (bit == State::Sx || bit == State::Sz) {
130 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
131 a = aig_map.at(State::S0);
132 }
133
134 log_assert(a >= 0);
135 aig_map[bit] = a;
136 return a;
137 }
138
139 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
140 {
141 pool<SigBit> undriven_bits;
142 pool<SigBit> unused_bits;
143
144 // promote public wires
145 for (auto wire : module->wires())
146 if (wire->name[0] == '\\')
147 sigmap.add(wire);
148
149 // promote input wires
150 for (auto wire : module->wires())
151 if (wire->port_input)
152 sigmap.add(wire);
153
154 // promote keep wires
155 for (auto wire : module->wires())
156 if (wire->get_bool_attribute(ID::keep))
157 sigmap.add(wire);
158
159 for (auto wire : module->wires())
160 for (int i = 0; i < GetSize(wire); i++)
161 {
162 SigBit wirebit(wire, i);
163 SigBit bit = sigmap(wirebit);
164
165 if (bit.wire == nullptr) {
166 if (wire->port_output) {
167 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
168 output_bits.insert(wirebit);
169 }
170 continue;
171 }
172
173 undriven_bits.insert(bit);
174 unused_bits.insert(bit);
175
176 bool keep = wire->get_bool_attribute(ID::keep);
177 if (wire->port_input || keep)
178 input_bits.insert(bit);
179
180 if (wire->port_output || keep) {
181 if (bit != wirebit)
182 alias_map[wirebit] = bit;
183 output_bits.insert(wirebit);
184 }
185 }
186
187 dict<IdString,dict<IdString,std::vector<int>>> arrivals_cache;
188 for (auto cell : module->cells()) {
189 RTLIL::Module* inst_module = module->design->module(cell->type);
190 if (!cell->has_keep_attr()) {
191 if (cell->type == "$_NOT_")
192 {
193 SigBit A = sigmap(cell->getPort("\\A").as_bit());
194 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
195 unused_bits.erase(A);
196 undriven_bits.erase(Y);
197 not_map[Y] = A;
198 continue;
199 }
200
201 if (cell->type == "$_AND_")
202 {
203 SigBit A = sigmap(cell->getPort("\\A").as_bit());
204 SigBit B = sigmap(cell->getPort("\\B").as_bit());
205 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
206 unused_bits.erase(A);
207 unused_bits.erase(B);
208 undriven_bits.erase(Y);
209 and_map[Y] = make_pair(A, B);
210 continue;
211 }
212
213 if (cell->type == "$__ABC9_FF_" &&
214 // The presence of an abc9_mergeability attribute indicates
215 // that we do want to pass this flop to ABC
216 cell->attributes.count("\\abc9_mergeability"))
217 {
218 SigBit D = sigmap(cell->getPort("\\D").as_bit());
219 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
220 unused_bits.erase(D);
221 undriven_bits.erase(Q);
222 alias_map[Q] = D;
223 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
224 log_assert(r.second);
225 continue;
226 }
227
228 if (inst_module) {
229 bool abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
230 auto it = cell->attributes.find("\\abc9_box_seq");
231 if (it != cell->attributes.end()) {
232 int abc9_box_seq = it->second.as_int();
233 if (GetSize(box_list) <= abc9_box_seq)
234 box_list.resize(abc9_box_seq+1);
235 box_list[abc9_box_seq] = cell;
236 // Only flop boxes may have arrival times
237 // (all others are combinatorial)
238 if (!abc9_flop)
239 continue;
240 }
241
242 auto &cell_arrivals = arrivals_cache[cell->type];
243 for (const auto &conn : cell->connections()) {
244 auto port_wire = inst_module->wire(conn.first);
245 if (!port_wire->port_output)
246 continue;
247
248 auto r = cell_arrivals.insert(conn.first);
249 auto &arrivals = r.first->second;
250 if (r.second) {
251 auto it = port_wire->attributes.find("\\abc9_arrival");
252 if (it == port_wire->attributes.end())
253 continue;
254 if (it->second.flags == 0)
255 arrivals.emplace_back(it->second.as_int());
256 else
257 for (const auto &tok : split_tokens(it->second.decode_string()))
258 arrivals.push_back(atoi(tok.c_str()));
259 }
260
261 if (arrivals.empty())
262 continue;
263
264 if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
265 log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
266 GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
267
268 auto jt = arrivals.begin();
269 #ifndef NDEBUG
270 if (ys_debug(1)) {
271 static std::set<std::pair<IdString,IdString>> seen;
272 if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt);
273 }
274 #endif
275 for (auto bit : sigmap(conn.second)) {
276 arrival_times[bit] = *jt;
277 if (arrivals.size() > 1)
278 jt++;
279 }
280 }
281
282 if (abc9_flop)
283 continue;
284 }
285 }
286
287 bool cell_known = inst_module || cell->known();
288 for (const auto &c : cell->connections()) {
289 if (c.second.is_fully_const()) continue;
290 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
291 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
292 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
293 if (!is_input && !is_output)
294 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
295
296 if (is_input)
297 for (auto b : c.second) {
298 Wire *w = b.wire;
299 if (!w) continue;
300 // Do not add as PO if bit is already a PI
301 if (input_bits.count(b))
302 continue;
303 if (!w->port_output || !cell_known) {
304 SigBit I = sigmap(b);
305 if (I != b)
306 alias_map[b] = I;
307 output_bits.insert(b);
308 }
309 }
310 }
311
312 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
313 }
314
315 dict<IdString, std::vector<IdString>> box_ports;
316 for (auto cell : box_list) {
317 log_assert(cell);
318
319 RTLIL::Module* box_module = module->design->module(cell->type);
320 log_assert(box_module);
321 log_assert(box_module->attributes.count("\\abc9_box_id"));
322
323 auto r = box_ports.insert(cell->type);
324 if (r.second) {
325 // Make carry in the last PI, and carry out the last PO
326 // since ABC requires it this way
327 IdString carry_in, carry_out;
328 for (const auto &port_name : box_module->ports) {
329 auto w = box_module->wire(port_name);
330 log_assert(w);
331 if (w->get_bool_attribute("\\abc9_carry")) {
332 if (w->port_input) {
333 if (carry_in != IdString())
334 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
335 carry_in = port_name;
336 }
337 if (w->port_output) {
338 if (carry_out != IdString())
339 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
340 carry_out = port_name;
341 }
342 }
343 else
344 r.first->second.push_back(port_name);
345 }
346
347 if (carry_in != IdString() && carry_out == IdString())
348 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
349 if (carry_in == IdString() && carry_out != IdString())
350 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
351 if (carry_in != IdString()) {
352 r.first->second.push_back(carry_in);
353 r.first->second.push_back(carry_out);
354 }
355 }
356
357 for (auto port_name : r.first->second) {
358 auto w = box_module->wire(port_name);
359 log_assert(w);
360 auto rhs = cell->connections_.at(port_name, SigSpec());
361 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
362 if (w->port_input)
363 for (auto b : rhs) {
364 SigBit I = sigmap(b);
365 if (b == RTLIL::Sx)
366 b = State::S0;
367 else if (I != b) {
368 if (I == RTLIL::Sx)
369 alias_map[b] = State::S0;
370 else
371 alias_map[b] = I;
372 }
373 co_bits.emplace_back(b);
374 unused_bits.erase(I);
375 }
376 if (w->port_output)
377 for (const auto &b : rhs) {
378 SigBit O = sigmap(b);
379 if (O != b)
380 alias_map[O] = b;
381 ci_bits.emplace_back(b);
382 undriven_bits.erase(O);
383 // If PI and CI, then must be a (* keep *) wire
384 if (input_bits.erase(O)) {
385 log_assert(output_bits.count(O));
386 log_assert(O.wire->get_bool_attribute(ID::keep));
387 }
388 }
389 }
390
391 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
392 if (box_module->get_bool_attribute("\\abc9_flop")) {
393 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
394 if (rhs.empty())
395 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
396
397 for (auto b : rhs) {
398 SigBit I = sigmap(b);
399 if (b == RTLIL::Sx)
400 b = State::S0;
401 else if (I != b) {
402 if (I == RTLIL::Sx)
403 alias_map[b] = State::S0;
404 else
405 alias_map[b] = I;
406 }
407 co_bits.emplace_back(b);
408 unused_bits.erase(I);
409 }
410 }
411 }
412
413 for (auto bit : input_bits)
414 undriven_bits.erase(bit);
415 for (auto bit : output_bits)
416 unused_bits.erase(sigmap(bit));
417 for (auto bit : unused_bits)
418 undriven_bits.erase(bit);
419
420 // Make all undriven bits a primary input
421 for (auto bit : undriven_bits) {
422 input_bits.insert(bit);
423 undriven_bits.erase(bit);
424 }
425
426 if (holes_mode) {
427 struct sort_by_port_id {
428 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
429 return a.wire->port_id < b.wire->port_id ||
430 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
431 }
432 };
433 input_bits.sort(sort_by_port_id());
434 output_bits.sort(sort_by_port_id());
435 }
436
437 aig_map[State::S0] = 0;
438 aig_map[State::S1] = 1;
439
440 for (const auto &bit : input_bits) {
441 aig_m++, aig_i++;
442 log_assert(!aig_map.count(bit));
443 aig_map[bit] = 2*aig_m;
444 }
445
446 for (const auto &i : ff_bits) {
447 const Cell *cell = i.second;
448 const SigBit &q = sigmap(cell->getPort("\\Q"));
449 aig_m++, aig_i++;
450 log_assert(!aig_map.count(q));
451 aig_map[q] = 2*aig_m;
452 }
453
454 for (auto &bit : ci_bits) {
455 aig_m++, aig_i++;
456 // 1'bx may exist here due to a box output
457 // that has been padded to its full width
458 if (bit == State::Sx)
459 continue;
460 log_assert(!aig_map.count(bit));
461 aig_map[bit] = 2*aig_m;
462 }
463
464 for (auto bit : co_bits) {
465 ordered_outputs[bit] = aig_o++;
466 aig_outputs.push_back(bit2aig(bit));
467 }
468
469 for (const auto &bit : output_bits) {
470 ordered_outputs[bit] = aig_o++;
471 int aig;
472 // Unlike bit2aig() which checks aig_map first, for
473 // inout/keep bits, since aig_map will point to
474 // the PI, first attempt to find the NOT/AND driver
475 // before resorting to an aig_map lookup (which
476 // could be another PO)
477 if (input_bits.count(bit)) {
478 if (not_map.count(bit)) {
479 aig = bit2aig(not_map.at(bit)) ^ 1;
480 } else if (and_map.count(bit)) {
481 auto args = and_map.at(bit);
482 int a0 = bit2aig(args.first);
483 int a1 = bit2aig(args.second);
484 aig = mkgate(a0, a1);
485 }
486 else
487 aig = aig_map.at(bit);
488 }
489 else
490 aig = bit2aig(bit);
491 aig_outputs.push_back(aig);
492 }
493
494 for (auto &i : ff_bits) {
495 const SigBit &d = i.first;
496 aig_o++;
497 aig_outputs.push_back(aig_map.at(d));
498 }
499 }
500
501 void write_aiger(std::ostream &f, bool ascii_mode)
502 {
503 int aig_obc = aig_o;
504 int aig_obcj = aig_obc;
505 int aig_obcjf = aig_obcj;
506
507 log_assert(aig_m == aig_i + aig_l + aig_a);
508 log_assert(aig_obcjf == GetSize(aig_outputs));
509
510 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
511 f << stringf("\n");
512
513 if (ascii_mode)
514 {
515 for (int i = 0; i < aig_i; i++)
516 f << stringf("%d\n", 2*i+2);
517
518 for (int i = 0; i < aig_obc; i++)
519 f << stringf("%d\n", aig_outputs.at(i));
520
521 for (int i = aig_obc; i < aig_obcj; i++)
522 f << stringf("1\n");
523
524 for (int i = aig_obc; i < aig_obcj; i++)
525 f << stringf("%d\n", aig_outputs.at(i));
526
527 for (int i = aig_obcj; i < aig_obcjf; i++)
528 f << stringf("%d\n", aig_outputs.at(i));
529
530 for (int i = 0; i < aig_a; i++)
531 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
532 }
533 else
534 {
535 for (int i = 0; i < aig_obc; i++)
536 f << stringf("%d\n", aig_outputs.at(i));
537
538 for (int i = aig_obc; i < aig_obcj; i++)
539 f << stringf("1\n");
540
541 for (int i = aig_obc; i < aig_obcj; i++)
542 f << stringf("%d\n", aig_outputs.at(i));
543
544 for (int i = aig_obcj; i < aig_obcjf; i++)
545 f << stringf("%d\n", aig_outputs.at(i));
546
547 for (int i = 0; i < aig_a; i++) {
548 int lhs = 2*(aig_i+aig_l+i)+2;
549 int rhs0 = aig_gates.at(i).first;
550 int rhs1 = aig_gates.at(i).second;
551 int delta0 = lhs - rhs0;
552 int delta1 = rhs0 - rhs1;
553 aiger_encode(f, delta0);
554 aiger_encode(f, delta1);
555 }
556 }
557
558 f << "c";
559
560 auto write_buffer = [](std::stringstream &buffer, int i32) {
561 int32_t i32_be = to_big_endian(i32);
562 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
563 };
564 std::stringstream h_buffer;
565 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
566 write_h_buffer(1);
567 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
568 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
569 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
570 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
571 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
572 write_h_buffer(input_bits.size() + ff_bits.size());
573 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
574 write_h_buffer(output_bits.size() + ff_bits.size());
575 log_debug("boxNum = %d\n", GetSize(box_list));
576 write_h_buffer(box_list.size());
577
578 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
579 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
580 };
581 std::stringstream i_buffer;
582 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
583 for (auto bit : input_bits)
584 write_i_buffer(arrival_times.at(bit, 0));
585 //std::stringstream o_buffer;
586 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
587 //for (auto bit : output_bits)
588 // write_o_buffer(0);
589
590 if (!box_list.empty() || !ff_bits.empty()) {
591 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
592 log_assert(holes_module);
593
594 dict<IdString, std::tuple<int,int,int>> cell_cache;
595
596 int box_count = 0;
597 for (auto cell : box_list) {
598 log_assert(cell);
599
600 RTLIL::Module* box_module = module->design->module(cell->type);
601 log_assert(box_module);
602
603 IdString derived_type = box_module->derive(box_module->design, cell->parameters);
604 box_module = box_module->design->module(derived_type);
605 log_assert(box_module);
606
607 auto r = cell_cache.insert(derived_type);
608 auto &v = r.first->second;
609 if (r.second) {
610 int box_inputs = 0, box_outputs = 0;
611 for (auto port_name : box_module->ports) {
612 RTLIL::Wire *w = box_module->wire(port_name);
613 log_assert(w);
614 if (w->port_input)
615 box_inputs += GetSize(w);
616 if (w->port_output)
617 box_outputs += GetSize(w);
618 }
619
620 // For flops only, create an extra 1-bit input that drives a new wire
621 // called "<cell>.abc9_ff.Q" that is used below
622 if (box_module->get_bool_attribute("\\abc9_flop"))
623 box_inputs++;
624
625 std::get<0>(v) = box_inputs;
626 std::get<1>(v) = box_outputs;
627 std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
628 }
629
630 write_h_buffer(std::get<0>(v));
631 write_h_buffer(std::get<1>(v));
632 write_h_buffer(std::get<2>(v));
633 write_h_buffer(box_count++);
634 }
635
636 std::stringstream r_buffer;
637 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
638 log_debug("flopNum = %d\n", GetSize(ff_bits));
639 write_r_buffer(ff_bits.size());
640
641 std::stringstream s_buffer;
642 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
643 write_s_buffer(ff_bits.size());
644
645 for (const auto &i : ff_bits) {
646 const SigBit &d = i.first;
647 const Cell *cell = i.second;
648
649 int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
650 log_assert(mergeability > 0);
651 write_r_buffer(mergeability);
652
653 Const init = cell->attributes.at(ID(abc9_init));
654 log_assert(GetSize(init) == 1);
655 if (init == State::S1)
656 write_s_buffer(1);
657 else if (init == State::S0)
658 write_s_buffer(0);
659 else {
660 log_assert(init == State::Sx);
661 write_s_buffer(0);
662 }
663
664 write_i_buffer(arrival_times.at(d, 0));
665 //write_o_buffer(0);
666 }
667
668 f << "r";
669 std::string buffer_str = r_buffer.str();
670 int32_t buffer_size_be = to_big_endian(buffer_str.size());
671 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
672 f.write(buffer_str.data(), buffer_str.size());
673
674 f << "s";
675 buffer_str = s_buffer.str();
676 buffer_size_be = to_big_endian(buffer_str.size());
677 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
678 f.write(buffer_str.data(), buffer_str.size());
679
680 if (holes_module) {
681 std::stringstream a_buffer;
682 XAigerWriter writer(holes_module, true /* holes_mode */);
683 writer.write_aiger(a_buffer, false /*ascii_mode*/);
684
685 f << "a";
686 std::string buffer_str = a_buffer.str();
687 int32_t buffer_size_be = to_big_endian(buffer_str.size());
688 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
689 f.write(buffer_str.data(), buffer_str.size());
690 }
691 }
692
693 f << "h";
694 std::string buffer_str = h_buffer.str();
695 int32_t buffer_size_be = to_big_endian(buffer_str.size());
696 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
697 f.write(buffer_str.data(), buffer_str.size());
698
699 f << "i";
700 buffer_str = i_buffer.str();
701 buffer_size_be = to_big_endian(buffer_str.size());
702 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
703 f.write(buffer_str.data(), buffer_str.size());
704 //f << "o";
705 //buffer_str = o_buffer.str();
706 //buffer_size_be = to_big_endian(buffer_str.size());
707 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
708 //f.write(buffer_str.data(), buffer_str.size());
709
710 f << stringf("Generated by %s\n", yosys_version_str);
711
712 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
713 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
714 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
715 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
716 }
717
718 void write_map(std::ostream &f)
719 {
720 dict<int, string> input_lines;
721 dict<int, string> output_lines;
722
723 for (auto wire : module->wires())
724 {
725 SigSpec sig = sigmap(wire);
726
727 for (int i = 0; i < GetSize(wire); i++)
728 {
729 RTLIL::SigBit b(wire, i);
730 if (input_bits.count(b)) {
731 int a = aig_map.at(b);
732 log_assert((a & 1) == 0);
733 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
734 }
735
736 if (output_bits.count(b)) {
737 int o = ordered_outputs.at(b);
738 int init = 2;
739 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
740 continue;
741 }
742 }
743 }
744
745 input_lines.sort();
746 for (auto &it : input_lines)
747 f << it.second;
748 log_assert(input_lines.size() == input_bits.size());
749
750 int box_count = 0;
751 for (auto cell : box_list)
752 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
753
754 output_lines.sort();
755 for (auto &it : output_lines)
756 f << it.second;
757 log_assert(output_lines.size() == output_bits.size());
758 }
759 };
760
761 struct XAigerBackend : public Backend {
762 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
763 void help() YS_OVERRIDE
764 {
765 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
766 log("\n");
767 log(" write_xaiger [options] [filename]\n");
768 log("\n");
769 log("Write the top module (according to the (* top *) attribute or if only one module\n");
770 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
771 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
772 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
773 log("module, if it exists.\n");
774 log("\n");
775 log(" -ascii\n");
776 log(" write ASCII version of AIGER format\n");
777 log("\n");
778 log(" -map <filename>\n");
779 log(" write an extra file with port and box symbols\n");
780 log("\n");
781 }
782 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
783 {
784 bool ascii_mode = false;
785 std::string map_filename;
786
787 log_header(design, "Executing XAIGER backend.\n");
788
789 size_t argidx;
790 for (argidx = 1; argidx < args.size(); argidx++)
791 {
792 if (args[argidx] == "-ascii") {
793 ascii_mode = true;
794 continue;
795 }
796 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
797 map_filename = args[++argidx];
798 continue;
799 }
800 break;
801 }
802 extra_args(f, filename, args, argidx, !ascii_mode);
803
804 Module *top_module = design->top_module();
805
806 if (top_module == nullptr)
807 log_error("Can't find top module in current design!\n");
808
809 if (!design->selected_whole_module(top_module))
810 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
811
812 if (!top_module->processes.empty())
813 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
814 if (!top_module->memories.empty())
815 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
816
817 XAigerWriter writer(top_module);
818 writer.write_aiger(*f, ascii_mode);
819
820 if (!map_filename.empty()) {
821 std::ofstream mapf;
822 mapf.open(map_filename.c_str(), std::ofstream::trunc);
823 if (mapf.fail())
824 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
825 writer.write_map(mapf);
826 }
827 }
828 } XAigerBackend;
829
830 PRIVATE_NAMESPACE_END