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Merge branch 'master' into clk2ff-better-names
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
51
52 USING_YOSYS_NAMESPACE
53 PRIVATE_NAMESPACE_BEGIN
54
55 inline int32_t to_big_endian(int32_t i32) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 return bswap32(i32);
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
59 return i32;
60 #else
61 #error "Unknown endianness"
62 #endif
63 }
64
65 void aiger_encode(std::ostream &f, int x)
66 {
67 log_assert(x >= 0);
68
69 while (x & ~0x7f) {
70 f.put((x & 0x7f) | 0x80);
71 x = x >> 7;
72 }
73
74 f.put(x);
75 }
76
77 struct XAigerWriter
78 {
79 Design *design;
80 Module *module;
81 SigMap sigmap;
82
83 dict<SigBit, State> init_map;
84 pool<SigBit> input_bits, output_bits;
85 dict<SigBit, SigBit> not_map, alias_map;
86 dict<SigBit, pair<SigBit, SigBit>> and_map;
87 vector<SigBit> ci_bits, co_bits;
88 vector<Cell*> ff_list;
89 dict<SigBit, float> arrival_times;
90
91 vector<pair<int, int>> aig_gates;
92 vector<int> aig_outputs;
93 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
94
95 dict<SigBit, int> aig_map;
96 dict<SigBit, int> ordered_outputs;
97
98 vector<Cell*> box_list;
99
100 int mkgate(int a0, int a1)
101 {
102 aig_m++, aig_a++;
103 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
104 return 2*aig_m;
105 }
106
107 int bit2aig(SigBit bit)
108 {
109 auto it = aig_map.find(bit);
110 if (it != aig_map.end()) {
111 log_assert(it->second >= 0);
112 return it->second;
113 }
114
115 // NB: Cannot use iterator returned from aig_map.insert()
116 // since this function is called recursively
117
118 int a = -1;
119 if (not_map.count(bit)) {
120 a = bit2aig(not_map.at(bit)) ^ 1;
121 } else
122 if (and_map.count(bit)) {
123 auto args = and_map.at(bit);
124 int a0 = bit2aig(args.first);
125 int a1 = bit2aig(args.second);
126 a = mkgate(a0, a1);
127 } else
128 if (alias_map.count(bit)) {
129 a = bit2aig(alias_map.at(bit));
130 }
131
132 if (bit == State::Sx || bit == State::Sz) {
133 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
134 a = aig_map.at(State::S0);
135 }
136
137 log_assert(a >= 0);
138 aig_map[bit] = a;
139 return a;
140 }
141
142 XAigerWriter(Module *module, bool dff_mode) : design(module->design), module(module), sigmap(module)
143 {
144 pool<SigBit> undriven_bits;
145 pool<SigBit> unused_bits;
146
147 // promote public wires
148 for (auto wire : module->wires())
149 if (wire->name.isPublic())
150 sigmap.add(wire);
151
152 // promote input wires
153 for (auto wire : module->wires())
154 if (wire->port_input)
155 sigmap.add(wire);
156
157 // promote keep wires
158 for (auto wire : module->wires())
159 if (wire->get_bool_attribute(ID::keep))
160 sigmap.add(wire);
161
162 for (auto wire : module->wires()) {
163 auto it = wire->attributes.find(ID::init);
164 for (int i = 0; i < GetSize(wire); i++)
165 {
166 SigBit wirebit(wire, i);
167 SigBit bit = sigmap(wirebit);
168
169 if (bit.wire == nullptr) {
170 if (wire->port_output) {
171 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
172 output_bits.insert(wirebit);
173 }
174 continue;
175 }
176
177 undriven_bits.insert(bit);
178 unused_bits.insert(bit);
179
180 if (wire->port_input)
181 input_bits.insert(bit);
182
183 bool keep = wire->get_bool_attribute(ID::keep);
184 if (wire->port_output || keep) {
185 if (bit != wirebit)
186 alias_map[wirebit] = bit;
187 output_bits.insert(wirebit);
188 }
189
190 if (it != wire->attributes.end()) {
191 auto s = it->second[i];
192 if (s != State::Sx) {
193 auto r = init_map.insert(std::make_pair(bit, it->second[i]));
194 if (!r.second && r.first->second != it->second[i])
195 log_error("Bit '%s' has a conflicting (* init *) value.\n", log_signal(bit));
196 }
197 }
198 }
199 }
200
201 TimingInfo timing;
202
203 for (auto cell : module->cells()) {
204 if (!cell->has_keep_attr()) {
205 if (cell->type == ID($_NOT_))
206 {
207 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
208 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
209 unused_bits.erase(A);
210 undriven_bits.erase(Y);
211 not_map[Y] = A;
212 continue;
213 }
214
215 if (cell->type == ID($_AND_))
216 {
217 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
218 SigBit B = sigmap(cell->getPort(ID::B).as_bit());
219 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
220 unused_bits.erase(A);
221 unused_bits.erase(B);
222 undriven_bits.erase(Y);
223 and_map[Y] = make_pair(A, B);
224 continue;
225 }
226
227 if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
228 {
229 SigBit D = sigmap(cell->getPort(ID::D).as_bit());
230 SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
231 unused_bits.erase(D);
232 undriven_bits.erase(Q);
233 alias_map[Q] = D;
234 ff_list.emplace_back(cell);
235 continue;
236 }
237
238 if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
239 continue;
240 }
241
242 RTLIL::Module* inst_module = design->module(cell->type);
243 if (inst_module && inst_module->get_blackbox_attribute()) {
244 bool abc9_flop = false;
245
246 auto it = cell->attributes.find(ID::abc9_box_seq);
247 if (it != cell->attributes.end()) {
248 log_assert(!cell->has_keep_attr());
249 log_assert(cell->parameters.empty());
250 int abc9_box_seq = it->second.as_int();
251 if (GetSize(box_list) <= abc9_box_seq)
252 box_list.resize(abc9_box_seq+1);
253 box_list[abc9_box_seq] = cell;
254 // Only flop boxes may have arrival times
255 // (all others are combinatorial)
256 log_assert(cell->parameters.empty());
257 abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
258 if (!abc9_flop)
259 continue;
260 }
261
262 if (!timing.count(inst_module->name))
263 timing.setup_module(inst_module);
264
265 for (auto &i : timing.at(inst_module->name).arrival) {
266 if (!cell->hasPort(i.first.name))
267 continue;
268
269 auto port_wire = inst_module->wire(i.first.name);
270 log_assert(port_wire->port_output);
271
272 auto d = i.second.first;
273 if (d == 0)
274 continue;
275 auto offset = i.first.offset;
276
277 #ifndef NDEBUG
278 if (ys_debug(1)) {
279 static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
280 if (seen.emplace(inst_module->name, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n",
281 log_id(cell->type), log_id(i.first.name), offset, d);
282 }
283 #endif
284 arrival_times[cell->getPort(i.first.name)[offset]] = d;
285 }
286
287 if (abc9_flop)
288 continue;
289 }
290
291 bool cell_known = inst_module || cell->known();
292 for (const auto &c : cell->connections()) {
293 if (c.second.is_fully_const()) continue;
294 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
295 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
296 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
297 if (!is_input && !is_output)
298 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
299
300 if (is_input)
301 for (auto b : c.second) {
302 Wire *w = b.wire;
303 if (!w) continue;
304 // Do not add as PO if bit is already a PI
305 if (input_bits.count(b))
306 continue;
307 if (!w->port_output || !cell_known) {
308 SigBit I = sigmap(b);
309 if (I != b)
310 alias_map[b] = I;
311 output_bits.insert(b);
312 }
313 }
314 }
315
316 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
317 }
318
319 dict<IdString, std::vector<IdString>> box_ports;
320 for (auto cell : box_list) {
321 log_assert(cell);
322
323 RTLIL::Module* box_module = design->module(cell->type);
324 log_assert(box_module);
325 log_assert(box_module->has_attribute(ID::abc9_box_id));
326
327 auto r = box_ports.insert(cell->type);
328 if (r.second) {
329 // Make carry in the last PI, and carry out the last PO
330 // since ABC requires it this way
331 IdString carry_in, carry_out;
332 for (const auto &port_name : box_module->ports) {
333 auto w = box_module->wire(port_name);
334 log_assert(w);
335 if (w->get_bool_attribute(ID::abc9_carry)) {
336 if (w->port_input) {
337 if (carry_in != IdString())
338 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
339 carry_in = port_name;
340 }
341 if (w->port_output) {
342 if (carry_out != IdString())
343 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
344 carry_out = port_name;
345 }
346 }
347 else
348 r.first->second.push_back(port_name);
349 }
350
351 if (carry_in != IdString() && carry_out == IdString())
352 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
353 if (carry_in == IdString() && carry_out != IdString())
354 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
355 if (carry_in != IdString()) {
356 r.first->second.push_back(carry_in);
357 r.first->second.push_back(carry_out);
358 }
359 }
360
361 for (auto port_name : r.first->second) {
362 auto w = box_module->wire(port_name);
363 log_assert(w);
364 auto rhs = cell->connections_.at(port_name, SigSpec());
365 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
366 if (w->port_input)
367 for (auto b : rhs) {
368 SigBit I = sigmap(b);
369 if (b == RTLIL::Sx)
370 b = State::S0;
371 else if (I != b) {
372 if (I == RTLIL::Sx)
373 alias_map[b] = State::S0;
374 else
375 alias_map[b] = I;
376 }
377 co_bits.emplace_back(b);
378 unused_bits.erase(I);
379 }
380 if (w->port_output)
381 for (const auto &b : rhs) {
382 SigBit O = sigmap(b);
383 if (O != b)
384 alias_map[O] = b;
385 ci_bits.emplace_back(b);
386 undriven_bits.erase(O);
387 }
388 }
389 }
390
391 for (auto bit : input_bits)
392 undriven_bits.erase(bit);
393 for (auto bit : output_bits)
394 unused_bits.erase(sigmap(bit));
395 for (auto bit : unused_bits)
396 undriven_bits.erase(bit);
397
398 // Make all undriven bits a primary input
399 for (auto bit : undriven_bits) {
400 input_bits.insert(bit);
401 undriven_bits.erase(bit);
402 }
403
404 struct sort_by_port_id {
405 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
406 return a.wire->port_id < b.wire->port_id ||
407 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
408 }
409 };
410 input_bits.sort(sort_by_port_id());
411 output_bits.sort(sort_by_port_id());
412
413 aig_map[State::S0] = 0;
414 aig_map[State::S1] = 1;
415
416 for (const auto &bit : input_bits) {
417 aig_m++, aig_i++;
418 log_assert(!aig_map.count(bit));
419 aig_map[bit] = 2*aig_m;
420 }
421
422 for (auto cell : ff_list) {
423 const SigBit &q = sigmap(cell->getPort(ID::Q));
424 aig_m++, aig_i++;
425 log_assert(!aig_map.count(q));
426 aig_map[q] = 2*aig_m;
427 }
428
429 for (auto &bit : ci_bits) {
430 aig_m++, aig_i++;
431 // 1'bx may exist here due to a box output
432 // that has been padded to its full width
433 if (bit == State::Sx)
434 continue;
435 if (aig_map.count(bit))
436 log_error("Visited AIG node more than once; this could be a combinatorial loop that has not been broken\n");
437 aig_map[bit] = 2*aig_m;
438 }
439
440 for (auto bit : co_bits) {
441 ordered_outputs[bit] = aig_o++;
442 aig_outputs.push_back(bit2aig(bit));
443 }
444
445 for (const auto &bit : output_bits) {
446 ordered_outputs[bit] = aig_o++;
447 int aig;
448 // Unlike bit2aig() which checks aig_map first for
449 // inout/scc bits, since aig_map will point to
450 // the PI, first attempt to find the NOT/AND driver
451 // before resorting to an aig_map lookup (which
452 // could be another PO)
453 if (input_bits.count(bit)) {
454 if (not_map.count(bit)) {
455 aig = bit2aig(not_map.at(bit)) ^ 1;
456 } else if (and_map.count(bit)) {
457 auto args = and_map.at(bit);
458 int a0 = bit2aig(args.first);
459 int a1 = bit2aig(args.second);
460 aig = mkgate(a0, a1);
461 }
462 else
463 aig = aig_map.at(bit);
464 }
465 else
466 aig = bit2aig(bit);
467 aig_outputs.push_back(aig);
468 }
469
470 for (auto cell : ff_list) {
471 const SigBit &d = sigmap(cell->getPort(ID::D));
472 aig_o++;
473 aig_outputs.push_back(aig_map.at(d));
474 }
475 }
476
477 void write_aiger(std::ostream &f, bool ascii_mode)
478 {
479 int aig_obc = aig_o;
480 int aig_obcj = aig_obc;
481 int aig_obcjf = aig_obcj;
482
483 log_assert(aig_m == aig_i + aig_l + aig_a);
484 log_assert(aig_obcjf == GetSize(aig_outputs));
485
486 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
487 f << stringf("\n");
488
489 if (ascii_mode)
490 {
491 for (int i = 0; i < aig_i; i++)
492 f << stringf("%d\n", 2*i+2);
493
494 for (int i = 0; i < aig_obc; i++)
495 f << stringf("%d\n", aig_outputs.at(i));
496
497 for (int i = aig_obc; i < aig_obcj; i++)
498 f << stringf("1\n");
499
500 for (int i = aig_obc; i < aig_obcj; i++)
501 f << stringf("%d\n", aig_outputs.at(i));
502
503 for (int i = aig_obcj; i < aig_obcjf; i++)
504 f << stringf("%d\n", aig_outputs.at(i));
505
506 for (int i = 0; i < aig_a; i++)
507 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
508 }
509 else
510 {
511 for (int i = 0; i < aig_obc; i++)
512 f << stringf("%d\n", aig_outputs.at(i));
513
514 for (int i = aig_obc; i < aig_obcj; i++)
515 f << stringf("1\n");
516
517 for (int i = aig_obc; i < aig_obcj; i++)
518 f << stringf("%d\n", aig_outputs.at(i));
519
520 for (int i = aig_obcj; i < aig_obcjf; i++)
521 f << stringf("%d\n", aig_outputs.at(i));
522
523 for (int i = 0; i < aig_a; i++) {
524 int lhs = 2*(aig_i+aig_l+i)+2;
525 int rhs0 = aig_gates.at(i).first;
526 int rhs1 = aig_gates.at(i).second;
527 int delta0 = lhs - rhs0;
528 int delta1 = rhs0 - rhs1;
529 aiger_encode(f, delta0);
530 aiger_encode(f, delta1);
531 }
532 }
533
534 f << "c";
535
536 auto write_buffer = [](std::stringstream &buffer, int i32) {
537 int32_t i32_be = to_big_endian(i32);
538 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
539 };
540 std::stringstream h_buffer;
541 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
542 write_h_buffer(1);
543 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_list) + GetSize(ci_bits));
544 write_h_buffer(GetSize(input_bits) + GetSize(ff_list) + GetSize(ci_bits));
545 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_list) + GetSize(co_bits));
546 write_h_buffer(GetSize(output_bits) + GetSize(ff_list) + GetSize(co_bits));
547 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_list));
548 write_h_buffer(GetSize(input_bits) + GetSize(ff_list));
549 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_list));
550 write_h_buffer(GetSize(output_bits) + GetSize(ff_list));
551 log_debug("boxNum = %d\n", GetSize(box_list));
552 write_h_buffer(GetSize(box_list));
553
554 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
555 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
556 };
557 std::stringstream i_buffer;
558 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
559 for (auto bit : input_bits)
560 write_i_buffer(arrival_times.at(bit, 0));
561 //std::stringstream o_buffer;
562 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
563 //for (auto bit : output_bits)
564 // write_o_buffer(0);
565
566 if (!box_list.empty() || !ff_list.empty()) {
567 dict<IdString, std::tuple<int,int,int>> cell_cache;
568
569 int box_count = 0;
570 for (auto cell : box_list) {
571 log_assert(cell);
572 log_assert(cell->parameters.empty());
573
574 auto r = cell_cache.insert(cell->type);
575 auto &v = r.first->second;
576 if (r.second) {
577 RTLIL::Module* box_module = design->module(cell->type);
578 log_assert(box_module);
579
580 int box_inputs = 0, box_outputs = 0;
581 for (auto port_name : box_module->ports) {
582 RTLIL::Wire *w = box_module->wire(port_name);
583 log_assert(w);
584 if (w->port_input)
585 box_inputs += GetSize(w);
586 if (w->port_output)
587 box_outputs += GetSize(w);
588 }
589
590 std::get<0>(v) = box_inputs;
591 std::get<1>(v) = box_outputs;
592 std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
593 }
594
595 write_h_buffer(std::get<0>(v));
596 write_h_buffer(std::get<1>(v));
597 write_h_buffer(std::get<2>(v));
598 write_h_buffer(box_count++);
599 }
600
601 std::stringstream r_buffer;
602 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
603 log_debug("flopNum = %d\n", GetSize(ff_list));
604 write_r_buffer(ff_list.size());
605
606 std::stringstream s_buffer;
607 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
608 write_s_buffer(ff_list.size());
609
610 dict<SigSpec, int> clk_to_mergeability;
611 for (const auto cell : ff_list) {
612 const SigBit &d = sigmap(cell->getPort(ID::D));
613 const SigBit &q = sigmap(cell->getPort(ID::Q));
614
615 SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
616 auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1));
617 int mergeability = r.first->second;
618 log_assert(mergeability > 0);
619 write_r_buffer(mergeability);
620
621 State init = init_map.at(q, State::Sx);
622 log_debug("Cell '%s' (type %s) has (* init *) value '%s'.\n", log_id(cell), log_id(cell->type), log_signal(init));
623 if (init == State::S1)
624 write_s_buffer(1);
625 else if (init == State::S0)
626 write_s_buffer(0);
627 else {
628 log_assert(init == State::Sx);
629 write_s_buffer(2);
630 }
631
632 // Use arrival time from output of flop box
633 write_i_buffer(arrival_times.at(d, 0));
634 //write_o_buffer(0);
635 }
636
637 f << "r";
638 std::string buffer_str = r_buffer.str();
639 int32_t buffer_size_be = to_big_endian(buffer_str.size());
640 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
641 f.write(buffer_str.data(), buffer_str.size());
642
643 f << "s";
644 buffer_str = s_buffer.str();
645 buffer_size_be = to_big_endian(buffer_str.size());
646 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
647 f.write(buffer_str.data(), buffer_str.size());
648
649 RTLIL::Design *holes_design;
650 auto it = saved_designs.find("$abc9_holes");
651 if (it != saved_designs.end())
652 holes_design = it->second;
653 else
654 holes_design = nullptr;
655 RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
656 if (holes_module) {
657 std::stringstream a_buffer;
658 XAigerWriter writer(holes_module, false /* dff_mode */);
659 writer.write_aiger(a_buffer, false /*ascii_mode*/);
660
661 f << "a";
662 std::string buffer_str = a_buffer.str();
663 int32_t buffer_size_be = to_big_endian(buffer_str.size());
664 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
665 f.write(buffer_str.data(), buffer_str.size());
666 }
667 }
668
669 f << "h";
670 std::string buffer_str = h_buffer.str();
671 int32_t buffer_size_be = to_big_endian(buffer_str.size());
672 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
673 f.write(buffer_str.data(), buffer_str.size());
674
675 f << "i";
676 buffer_str = i_buffer.str();
677 buffer_size_be = to_big_endian(buffer_str.size());
678 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
679 f.write(buffer_str.data(), buffer_str.size());
680 //f << "o";
681 //buffer_str = o_buffer.str();
682 //buffer_size_be = to_big_endian(buffer_str.size());
683 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
684 //f.write(buffer_str.data(), buffer_str.size());
685
686 f << stringf("Generated by %s\n", yosys_version_str);
687
688 design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
689 design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
690 design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
691 design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
692 }
693
694 void write_map(std::ostream &f)
695 {
696 dict<int, string> input_lines;
697 dict<int, string> output_lines;
698
699 for (auto wire : module->wires())
700 {
701 for (int i = 0; i < GetSize(wire); i++)
702 {
703 RTLIL::SigBit b(wire, i);
704 if (input_bits.count(b)) {
705 int a = aig_map.at(b);
706 log_assert((a & 1) == 0);
707 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, wire->start_offset+i, log_id(wire));
708 }
709
710 if (output_bits.count(b)) {
711 int o = ordered_outputs.at(b);
712 output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), wire->start_offset+i, log_id(wire));
713 }
714 }
715 }
716
717 input_lines.sort();
718 for (auto &it : input_lines)
719 f << it.second;
720 log_assert(input_lines.size() == input_bits.size());
721
722 int box_count = 0;
723 for (auto cell : box_list)
724 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
725
726 output_lines.sort();
727 for (auto &it : output_lines)
728 f << it.second;
729 log_assert(output_lines.size() == output_bits.size());
730 }
731 };
732
733 struct XAigerBackend : public Backend {
734 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
735 void help() override
736 {
737 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
738 log("\n");
739 log(" write_xaiger [options] [filename]\n");
740 log("\n");
741 log("Write the top module (according to the (* top *) attribute or if only one module\n");
742 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, (optionally\n");
743 log("$_DFF_N_, $_DFF_P_), or non (* abc9_box *) cells will be converted into psuedo-\n");
744 log("inputs and pseudo-outputs. Whitebox contents will be taken from the equivalent\n");
745 log("module in the '$abc9_holes' design, if it exists.\n");
746 log("\n");
747 log(" -ascii\n");
748 log(" write ASCII version of AIGER format\n");
749 log("\n");
750 log(" -map <filename>\n");
751 log(" write an extra file with port and box symbols\n");
752 log("\n");
753 log(" -dff\n");
754 log(" write $_DFF_[NP]_ cells\n");
755 log("\n");
756 }
757 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
758 {
759 bool ascii_mode = false, dff_mode = false;
760 std::string map_filename;
761
762 log_header(design, "Executing XAIGER backend.\n");
763
764 size_t argidx;
765 for (argidx = 1; argidx < args.size(); argidx++)
766 {
767 if (args[argidx] == "-ascii") {
768 ascii_mode = true;
769 continue;
770 }
771 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
772 map_filename = args[++argidx];
773 continue;
774 }
775 if (args[argidx] == "-dff") {
776 dff_mode = true;
777 continue;
778 }
779 break;
780 }
781 extra_args(f, filename, args, argidx, !ascii_mode);
782
783 Module *top_module = design->top_module();
784
785 if (top_module == nullptr)
786 log_error("Can't find top module in current design!\n");
787
788 if (!design->selected_whole_module(top_module))
789 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
790
791 if (!top_module->processes.empty())
792 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
793 if (!top_module->memories.empty())
794 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
795
796 XAigerWriter writer(top_module, dff_mode);
797 writer.write_aiger(*f, ascii_mode);
798
799 if (!map_filename.empty()) {
800 std::ofstream mapf;
801 mapf.open(map_filename.c_str(), std::ofstream::trunc);
802 if (mapf.fail())
803 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
804 writer.write_map(mapf);
805 }
806 }
807 } XAigerBackend;
808
809 PRIVATE_NAMESPACE_END