e7d767721387f9782c7da6d904ee9a3b35ff7766
2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 // https://stackoverflow.com/a/46137633
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
32 inline static uint32_t bswap32(uint32_t x
)
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value
= number_to_be_reversed
;
36 uint8_t lolo
= (value
>> 0) & 0xFF;
37 uint8_t lohi
= (value
>> 8) & 0xFF;
38 uint8_t hilo
= (value
>> 16) & 0xFF;
39 uint8_t hihi
= (value
>> 24) & 0xFF;
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
52 PRIVATE_NAMESPACE_BEGIN
54 inline int32_t to_big_endian(int32_t i32
) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
60 #error "Unknown endianness"
64 void aiger_encode(std::ostream
&f
, int x
)
69 f
.put((x
& 0x7f) | 0x80);
81 pool
<SigBit
> input_bits
, output_bits
, external_bits
;
82 dict
<SigBit
, SigBit
> not_map
, alias_map
;
83 dict
<SigBit
, pair
<SigBit
, SigBit
>> and_map
;
84 vector
<SigBit
> ci_bits
, co_bits
;
85 dict
<SigBit
, std::pair
<int,int>> ff_bits
;
86 dict
<SigBit
, float> arrival_times
;
88 vector
<pair
<int, int>> aig_gates
;
89 vector
<int> aig_outputs
;
90 int aig_m
= 0, aig_i
= 0, aig_l
= 0, aig_o
= 0, aig_a
= 0;
92 dict
<SigBit
, int> aig_map
;
93 dict
<SigBit
, int> ordered_outputs
;
95 vector
<Cell
*> box_list
;
97 int mkgate(int a0
, int a1
)
100 aig_gates
.push_back(a0
> a1
? make_pair(a0
, a1
) : make_pair(a1
, a0
));
104 int bit2aig(SigBit bit
)
106 auto it
= aig_map
.find(bit
);
107 if (it
!= aig_map
.end()) {
108 log_assert(it
->second
>= 0);
112 // NB: Cannot use iterator returned from aig_map.insert()
113 // since this function is called recursively
116 if (not_map
.count(bit
)) {
117 a
= bit2aig(not_map
.at(bit
)) ^ 1;
119 if (and_map
.count(bit
)) {
120 auto args
= and_map
.at(bit
);
121 int a0
= bit2aig(args
.first
);
122 int a1
= bit2aig(args
.second
);
125 if (alias_map
.count(bit
)) {
126 a
= bit2aig(alias_map
.at(bit
));
129 if (bit
== State::Sx
|| bit
== State::Sz
) {
130 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
131 a
= aig_map
.at(State::S0
);
139 XAigerWriter(Module
*module
, bool holes_mode
=false) : module(module
), sigmap(module
)
141 pool
<SigBit
> undriven_bits
;
142 pool
<SigBit
> unused_bits
;
143 pool
<SigBit
> inout_bits
;
145 // promote public wires
146 for (auto wire
: module
->wires())
147 if (wire
->name
[0] == '\\')
150 // promote input wires
151 for (auto wire
: module
->wires())
152 if (wire
->port_input
)
155 // promote keep wires
156 for (auto wire
: module
->wires())
157 if (wire
->get_bool_attribute(ID::keep
))
160 for (auto wire
: module
->wires())
161 for (int i
= 0; i
< GetSize(wire
); i
++)
163 SigBit
wirebit(wire
, i
);
164 SigBit bit
= sigmap(wirebit
);
166 if (bit
.wire
== nullptr) {
167 if (wire
->port_output
) {
168 aig_map
[wirebit
] = (bit
== State::S1
) ? 1 : 0;
170 output_bits
.insert(wirebit
);
171 //external_bits.insert(wirebit);
176 undriven_bits
.insert(bit
);
177 unused_bits
.insert(bit
);
179 if (wire
->port_input
)
180 input_bits
.insert(bit
);
182 if (wire
->port_output
) {
184 alias_map
[wirebit
] = bit
;
186 output_bits
.insert(wirebit
);
188 external_bits
.insert(wirebit
);
191 if (wire
->port_input
&& wire
->port_output
)
192 inout_bits
.insert(wirebit
);
195 // TODO: Speed up toposort -- ultimately we care about
196 // box ordering, but not individual AIG cells
197 dict
<SigBit
, pool
<IdString
>> bit_drivers
, bit_users
;
198 TopoSort
<IdString
, RTLIL::sort_by_id_str
> toposort
;
199 bool abc9_box_seen
= false;
200 std::vector
<Cell
*> flop_boxes
;
202 for (auto cell
: module
->selected_cells()) {
203 if (cell
->type
== "$_NOT_")
205 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
206 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
207 unused_bits
.erase(A
);
208 undriven_bits
.erase(Y
);
211 toposort
.node(cell
->name
);
212 bit_users
[A
].insert(cell
->name
);
213 bit_drivers
[Y
].insert(cell
->name
);
218 if (cell
->type
== "$_AND_")
220 SigBit A
= sigmap(cell
->getPort("\\A").as_bit());
221 SigBit B
= sigmap(cell
->getPort("\\B").as_bit());
222 SigBit Y
= sigmap(cell
->getPort("\\Y").as_bit());
223 unused_bits
.erase(A
);
224 unused_bits
.erase(B
);
225 undriven_bits
.erase(Y
);
226 and_map
[Y
] = make_pair(A
, B
);
228 toposort
.node(cell
->name
);
229 bit_users
[A
].insert(cell
->name
);
230 bit_users
[B
].insert(cell
->name
);
231 bit_drivers
[Y
].insert(cell
->name
);
236 log_assert(!holes_mode
);
238 if (cell
->type
== "$__ABC9_FF_")
240 SigBit D
= sigmap(cell
->getPort("\\D").as_bit());
241 SigBit Q
= sigmap(cell
->getPort("\\Q").as_bit());
242 unused_bits
.erase(D
);
243 undriven_bits
.erase(Q
);
245 auto r
= ff_bits
.insert(std::make_pair(D
, std::make_pair(0, 2)));
246 log_assert(r
.second
);
250 RTLIL::Module
* inst_module
= module
->design
->module(cell
->type
);
252 bool abc9_box
= inst_module
->attributes
.count("\\abc9_box_id") && !cell
->get_bool_attribute("\\abc9_keep");
254 for (const auto &conn
: cell
->connections()) {
255 auto port_wire
= inst_module
->wire(conn
.first
);
257 if (port_wire
->port_output
) {
259 auto it
= port_wire
->attributes
.find("\\abc9_arrival");
260 if (it
!= port_wire
->attributes
.end()) {
261 if (it
->second
.flags
!= 0)
262 log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire
), log_id(cell
->type
));
263 arrival
= it
->second
.as_int();
266 for (auto bit
: sigmap(conn
.second
))
267 arrival_times
[bit
] = arrival
;
271 // Ignore inout for the sake of topographical ordering
272 if (port_wire
->port_input
&& !port_wire
->port_output
)
273 for (auto bit
: sigmap(conn
.second
))
274 bit_users
[bit
].insert(cell
->name
);
275 if (port_wire
->port_output
)
276 for (auto bit
: sigmap(conn
.second
))
277 bit_drivers
[bit
].insert(cell
->name
);
282 abc9_box_seen
= true;
284 toposort
.node(cell
->name
);
286 if (inst_module
->attributes
.count("\\abc9_flop"))
287 flop_boxes
.push_back(cell
);
292 bool cell_known
= inst_module
|| cell
->known();
293 for (const auto &c
: cell
->connections()) {
294 if (c
.second
.is_fully_const()) continue;
295 auto port_wire
= inst_module
? inst_module
->wire(c
.first
) : nullptr;
296 auto is_input
= (port_wire
&& port_wire
->port_input
) || !cell_known
|| cell
->input(c
.first
);
297 auto is_output
= (port_wire
&& port_wire
->port_output
) || !cell_known
|| cell
->output(c
.first
);
298 if (!is_input
&& !is_output
)
299 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c
.first
), log_id(cell
), log_id(cell
->type
));
302 for (auto b
: c
.second
) {
305 if (!w
->port_output
|| !cell_known
) {
306 SigBit I
= sigmap(b
);
310 output_bits
.insert(b
);
312 external_bits
.insert(b
);
318 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
322 dict
<IdString
, std::pair
<IdString
,int>> flop_q
;
323 for (auto cell
: flop_boxes
) {
324 auto r
= flop_q
.insert(std::make_pair(cell
->type
, std::make_pair(IdString(), 0)));
327 for (const auto &conn
: cell
->connections()) {
328 const SigSpec
&rhs
= conn
.second
;
331 if (!ff_bits
.count(rhs
))
333 r
.first
->second
.first
= conn
.first
;
334 Module
*inst_module
= module
->design
->module(cell
->type
);
335 Wire
*wire
= inst_module
->wire(conn
.first
);
337 auto jt
= wire
->attributes
.find("\\abc9_arrival");
338 if (jt
!= wire
->attributes
.end()) {
339 if (jt
->second
.flags
!= 0)
340 log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire
), log_id(cell
->type
));
341 r
.first
->second
.second
= jt
->second
.as_int();
344 log_assert(d
== sigmap(d
));
349 d
= cell
->getPort(r
.first
->second
.first
);
351 auto &rhs
= ff_bits
.at(d
);
353 auto it
= cell
->attributes
.find(ID(abc9_mergeability
));
354 log_assert(it
!= cell
->attributes
.end());
355 rhs
.first
= it
->second
.as_int();
356 cell
->attributes
.erase(it
);
358 it
= cell
->attributes
.find(ID(abc9_init
));
359 log_assert(it
!= cell
->attributes
.end());
360 log_assert(GetSize(it
->second
) == 1);
361 if (it
->second
[0] == State::S1
)
363 else if (it
->second
[0] == State::S0
)
366 log_assert(it
->second
[0] == State::Sx
);
369 cell
->attributes
.erase(it
);
371 auto arrival
= r
.first
->second
.second
;
373 arrival_times
[d
] = arrival
;
376 for (auto &it
: bit_users
)
377 if (bit_drivers
.count(it
.first
))
378 for (auto driver_cell
: bit_drivers
.at(it
.first
))
379 for (auto user_cell
: it
.second
)
380 toposort
.edge(driver_cell
, user_cell
);
383 toposort
.analyze_loops
= true;
385 bool no_loops
YS_ATTRIBUTE(unused
) = toposort
.sort();
388 for (auto &it
: toposort
.loops
) {
389 log(" loop %d\n", i
++);
390 for (auto cell_name
: it
) {
391 auto cell
= module
->cell(cell_name
);
393 log("\t%s (%s @ %s)\n", log_id(cell
), log_id(cell
->type
), cell
->get_src_attribute().c_str());
397 log_assert(no_loops
);
399 for (auto cell_name
: toposort
.sorted
) {
400 RTLIL::Cell
*cell
= module
->cell(cell_name
);
403 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
404 if (!box_module
|| !box_module
->attributes
.count("\\abc9_box_id")
405 || cell
->get_bool_attribute("\\abc9_keep"))
408 bool blackbox
= box_module
->get_blackbox_attribute(true /* ignore_wb */);
410 // Fully pad all unused input connections of this box cell with S0
411 // Fully pad all undriven output connections of this box cell with anonymous wires
412 // NB: Assume box_module->ports are sorted alphabetically
413 // (as RTLIL::Module::fixup_ports() would do)
414 for (const auto &port_name
: box_module
->ports
) {
415 RTLIL::Wire
* w
= box_module
->wire(port_name
);
417 auto it
= cell
->connections_
.find(port_name
);
420 if (it
!= cell
->connections_
.end()) {
421 if (GetSize(it
->second
) < GetSize(w
))
422 it
->second
.append(RTLIL::SigSpec(State::S0
, GetSize(w
)-GetSize(it
->second
)));
426 rhs
= RTLIL::SigSpec(State::S0
, GetSize(w
));
427 cell
->setPort(port_name
, rhs
);
430 for (auto b
: rhs
.bits()) {
431 SigBit I
= sigmap(b
);
436 alias_map
[b
] = State::S0
;
440 co_bits
.emplace_back(b
);
441 unused_bits
.erase(I
);
444 if (w
->port_output
) {
446 auto it
= cell
->connections_
.find(w
->name
);
447 if (it
!= cell
->connections_
.end()) {
448 if (GetSize(it
->second
) < GetSize(w
))
449 it
->second
.append(module
->addWire(NEW_ID
, GetSize(w
)-GetSize(it
->second
)));
453 Wire
*wire
= module
->addWire(NEW_ID
, GetSize(w
));
455 wire
->set_bool_attribute(ID(abc9_padding
));
457 cell
->setPort(port_name
, rhs
);
460 for (const auto &b
: rhs
.bits()) {
461 ci_bits
.emplace_back(b
);
462 SigBit O
= sigmap(b
);
466 undriven_bits
.erase(O
);
471 // Connect <cell>.$abc9_currQ (inserted by abc9_map.v) as an input to the flop box
472 if (box_module
->get_bool_attribute("\\abc9_flop")) {
473 SigSpec rhs
= module
->wire(stringf("%s.$abc9_currQ", cell
->name
.c_str()));
475 log_error("'%s.$abc9_currQ' is not a wire present in module '%s'.\n", log_id(cell
), log_id(module
));
478 SigBit I
= sigmap(b
);
483 alias_map
[b
] = State::S0
;
487 co_bits
.emplace_back(b
);
488 unused_bits
.erase(I
);
492 box_list
.emplace_back(cell
);
495 // TODO: Free memory from toposort, bit_drivers, bit_users
499 for (auto cell
: module
->cells())
500 if (!module
->selected(cell
))
501 for (auto &conn
: cell
->connections())
502 if (cell
->input(conn
.first
))
503 for (auto wirebit
: conn
.second
)
504 if (sigmap(wirebit
).wire
)
505 external_bits
.insert(wirebit
);
507 // For all bits consumed outside of the selected cells,
508 // but driven from a selected cell, then add it as
510 for (auto wirebit
: external_bits
) {
511 SigBit bit
= sigmap(wirebit
);
514 if (!undriven_bits
.count(bit
)) {
516 alias_map
[wirebit
] = bit
;
517 output_bits
.insert(wirebit
);
521 for (auto bit
: input_bits
)
522 undriven_bits
.erase(sigmap(bit
));
523 for (auto bit
: output_bits
)
524 unused_bits
.erase(sigmap(bit
));
525 for (auto bit
: unused_bits
)
526 undriven_bits
.erase(bit
);
528 // Make all undriven bits a primary input
530 for (auto bit
: undriven_bits
) {
531 input_bits
.insert(bit
);
532 undriven_bits
.erase(bit
);
536 struct sort_by_port_id
{
537 bool operator()(const RTLIL::SigBit
& a
, const RTLIL::SigBit
& b
) const {
538 return a
.wire
->port_id
< b
.wire
->port_id
;
541 input_bits
.sort(sort_by_port_id());
542 output_bits
.sort(sort_by_port_id());
552 aig_map
[State::S0
] = 0;
553 aig_map
[State::S1
] = 1;
555 for (auto bit
: input_bits
) {
557 log_assert(!aig_map
.count(bit
));
558 aig_map
[bit
] = 2*aig_m
;
561 for (const auto &i
: ff_bits
) {
562 const SigBit
&bit
= i
.first
;
564 log_assert(!aig_map
.count(bit
));
565 aig_map
[bit
] = 2*aig_m
;
568 dict
<SigBit
, int> ff_aig_map
;
569 for (auto &bit
: ci_bits
) {
571 auto r
= aig_map
.insert(std::make_pair(bit
, 2*aig_m
));
573 ff_aig_map
[bit
] = 2*aig_m
;
576 for (auto bit
: co_bits
) {
577 ordered_outputs
[bit
] = aig_o
++;
578 aig_outputs
.push_back(bit2aig(bit
));
581 for (auto bit
: output_bits
) {
582 ordered_outputs
[bit
] = aig_o
++;
583 aig_outputs
.push_back(bit2aig(bit
));
586 for (auto &i
: ff_bits
) {
587 const SigBit
&bit
= i
.first
;
589 aig_outputs
.push_back(ff_aig_map
.at(bit
));
593 void write_aiger(std::ostream
&f
, bool ascii_mode
)
596 int aig_obcj
= aig_obc
;
597 int aig_obcjf
= aig_obcj
;
599 log_assert(aig_m
== aig_i
+ aig_l
+ aig_a
);
600 log_assert(aig_obcjf
== GetSize(aig_outputs
));
602 f
<< stringf("%s %d %d %d %d %d", ascii_mode
? "aag" : "aig", aig_m
, aig_i
, aig_l
, aig_o
, aig_a
);
607 for (int i
= 0; i
< aig_i
; i
++)
608 f
<< stringf("%d\n", 2*i
+2);
610 for (int i
= 0; i
< aig_obc
; i
++)
611 f
<< stringf("%d\n", aig_outputs
.at(i
));
613 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
616 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
617 f
<< stringf("%d\n", aig_outputs
.at(i
));
619 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
620 f
<< stringf("%d\n", aig_outputs
.at(i
));
622 for (int i
= 0; i
< aig_a
; i
++)
623 f
<< stringf("%d %d %d\n", 2*(aig_i
+aig_l
+i
)+2, aig_gates
.at(i
).first
, aig_gates
.at(i
).second
);
627 for (int i
= 0; i
< aig_obc
; i
++)
628 f
<< stringf("%d\n", aig_outputs
.at(i
));
630 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
633 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
634 f
<< stringf("%d\n", aig_outputs
.at(i
));
636 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
637 f
<< stringf("%d\n", aig_outputs
.at(i
));
639 for (int i
= 0; i
< aig_a
; i
++) {
640 int lhs
= 2*(aig_i
+aig_l
+i
)+2;
641 int rhs0
= aig_gates
.at(i
).first
;
642 int rhs1
= aig_gates
.at(i
).second
;
643 int delta0
= lhs
- rhs0
;
644 int delta1
= rhs0
- rhs1
;
645 aiger_encode(f
, delta0
);
646 aiger_encode(f
, delta1
);
652 auto write_buffer
= [](std::stringstream
&buffer
, int i32
) {
653 int32_t i32_be
= to_big_endian(i32
);
654 buffer
.write(reinterpret_cast<const char*>(&i32_be
), sizeof(i32_be
));
656 std::stringstream h_buffer
;
657 auto write_h_buffer
= std::bind(write_buffer
, std::ref(h_buffer
), std::placeholders::_1
);
659 log_debug("ciNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
) + GetSize(ci_bits
));
660 write_h_buffer(input_bits
.size() + ff_bits
.size() + ci_bits
.size());
661 log_debug("coNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
) + GetSize(co_bits
));
662 write_h_buffer(output_bits
.size() + GetSize(ff_bits
) + GetSize(co_bits
));
663 log_debug("piNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
));
664 write_h_buffer(input_bits
.size() + ff_bits
.size());
665 log_debug("poNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
));
666 write_h_buffer(output_bits
.size() + ff_bits
.size());
667 log_debug("boxNum = %d\n", GetSize(box_list
));
668 write_h_buffer(box_list
.size());
670 auto write_buffer_float
= [](std::stringstream
&buffer
, float f32
) {
671 buffer
.write(reinterpret_cast<const char*>(&f32
), sizeof(f32
));
673 std::stringstream i_buffer
;
674 auto write_i_buffer
= std::bind(write_buffer_float
, std::ref(i_buffer
), std::placeholders::_1
);
675 for (auto bit
: input_bits
)
676 write_i_buffer(arrival_times
.at(bit
, 0));
677 //std::stringstream o_buffer;
678 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
679 //for (auto bit : output_bits)
680 // write_o_buffer(0);
682 if (!box_list
.empty() || !ff_bits
.empty()) {
683 RTLIL::Module
*holes_module
= module
->design
->addModule("$__holes__");
684 log_assert(holes_module
);
686 dict
<IdString
, Cell
*> cell_cache
;
690 for (auto cell
: box_list
) {
691 RTLIL::Module
* orig_box_module
= module
->design
->module(cell
->type
);
692 log_assert(orig_box_module
);
693 IdString derived_name
= orig_box_module
->derive(module
->design
, cell
->parameters
);
694 RTLIL::Module
* box_module
= module
->design
->module(derived_name
);
695 if (box_module
->has_processes())
696 Pass::call_on_module(module
->design
, box_module
, "proc");
698 int box_inputs
= 0, box_outputs
= 0;
699 auto r
= cell_cache
.insert(std::make_pair(derived_name
, nullptr));
700 Cell
*holes_cell
= r
.first
->second
;
701 if (r
.second
&& box_module
->get_bool_attribute("\\whitebox")) {
702 holes_cell
= holes_module
->addCell(cell
->name
, cell
->type
);
703 holes_cell
->parameters
= cell
->parameters
;
704 r
.first
->second
= holes_cell
;
706 // Since Module::derive() will create a new module, there
707 // is a chance that the ports will be alphabetically ordered
708 // again, which is a problem when carry-chains are involved.
709 // Inherit the port ordering from the original module here...
710 // (and set the port_id below, when iterating through those)
711 log_assert(GetSize(box_module
->ports
) == GetSize(orig_box_module
->ports
));
712 box_module
->ports
= orig_box_module
->ports
;
715 // NB: Assume box_module->ports are sorted alphabetically
716 // (as RTLIL::Module::fixup_ports() would do)
718 for (const auto &port_name
: box_module
->ports
) {
719 RTLIL::Wire
*w
= box_module
->wire(port_name
);
722 w
->port_id
= box_port_id
++;
723 RTLIL::Wire
*holes_wire
;
724 RTLIL::SigSpec port_sig
;
726 for (int i
= 0; i
< GetSize(w
); i
++) {
728 holes_wire
= holes_module
->wire(stringf("\\i%d", box_inputs
));
730 holes_wire
= holes_module
->addWire(stringf("\\i%d", box_inputs
));
731 holes_wire
->port_input
= true;
732 holes_wire
->port_id
= port_id
++;
733 holes_module
->ports
.push_back(holes_wire
->name
);
736 port_sig
.append(holes_wire
);
738 if (w
->port_output
) {
739 box_outputs
+= GetSize(w
);
740 for (int i
= 0; i
< GetSize(w
); i
++) {
742 holes_wire
= holes_module
->addWire(stringf("$abc%s.%s", cell
->name
.c_str(), log_id(w
->name
)));
744 holes_wire
= holes_module
->addWire(stringf("$abc%s.%s[%d]", cell
->name
.c_str(), log_id(w
->name
), i
));
745 holes_wire
->port_output
= true;
746 holes_wire
->port_id
= port_id
++;
747 holes_module
->ports
.push_back(holes_wire
->name
);
749 port_sig
.append(holes_wire
);
751 holes_module
->connect(holes_wire
, State::S0
);
754 if (!port_sig
.empty()) {
756 holes_cell
->setPort(w
->name
, port_sig
);
758 holes_module
->connect(holes_cell
->getPort(w
->name
), port_sig
);
762 // For flops only, create an extra 1-bit input that drives a new wire
763 // called "<cell>.$abc9_currQ" that is used below
764 if (box_module
->get_bool_attribute("\\abc9_flop")) {
765 log_assert(holes_cell
);
768 Wire
*holes_wire
= holes_module
->wire(stringf("\\i%d", box_inputs
));
770 holes_wire
= holes_module
->addWire(stringf("\\i%d", box_inputs
));
771 holes_wire
->port_input
= true;
772 holes_wire
->port_id
= port_id
++;
773 holes_module
->ports
.push_back(holes_wire
->name
);
775 Wire
*w
= holes_module
->addWire(stringf("%s.$abc9_currQ", cell
->name
.c_str()));
776 holes_module
->connect(w
, holes_wire
);
779 write_h_buffer(box_inputs
);
780 write_h_buffer(box_outputs
);
781 write_h_buffer(box_module
->attributes
.at("\\abc9_box_id").as_int());
782 write_h_buffer(box_count
++);
785 std::stringstream r_buffer
;
786 auto write_r_buffer
= std::bind(write_buffer
, std::ref(r_buffer
), std::placeholders::_1
);
787 log_debug("flopNum = %d\n", GetSize(ff_bits
));
788 write_r_buffer(ff_bits
.size());
790 std::stringstream s_buffer
;
791 auto write_s_buffer
= std::bind(write_buffer
, std::ref(s_buffer
), std::placeholders::_1
);
792 write_s_buffer(ff_bits
.size());
794 for (const auto &i
: ff_bits
) {
795 const SigBit
&bit
= i
.first
;
796 int mergeability
= i
.second
.first
;
797 log_assert(mergeability
> 0);
798 write_r_buffer(mergeability
);
799 int init
= i
.second
.second
;
800 write_s_buffer(init
);
801 write_i_buffer(arrival_times
.at(bit
, 0));
806 std::string buffer_str
= r_buffer
.str();
807 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
808 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
809 f
.write(buffer_str
.data(), buffer_str
.size());
812 buffer_str
= s_buffer
.str();
813 buffer_size_be
= to_big_endian(buffer_str
.size());
814 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
815 f
.write(buffer_str
.data(), buffer_str
.size());
820 // NB: fixup_ports() will sort ports by name
821 //holes_module->fixup_ports();
822 holes_module
->check();
824 // Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
825 // since boxes may contain parameters in which case `flatten` would have
826 // created a new $paramod ...
827 Pass::call_on_module(holes_module
->design
, holes_module
, "flatten -wb; techmap; aigmap");
829 dict
<SigSig
, SigSig
> replace
;
830 for (auto it
= holes_module
->cells_
.begin(); it
!= holes_module
->cells_
.end(); ) {
831 auto cell
= it
->second
;
832 if (cell
->type
.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
833 "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
834 SigBit D
= cell
->getPort("\\D");
835 SigBit Q
= cell
->getPort("\\Q");
836 // Remove the DFF cell from what needs to be a combinatorial box
837 it
= holes_module
->cells_
.erase(it
);
839 if (GetSize(Q
.wire
) == 1)
840 port
= holes_module
->wire(stringf("$abc%s", Q
.wire
->name
.c_str()));
842 port
= holes_module
->wire(stringf("$abc%s[%d]", Q
.wire
->name
.c_str(), Q
.offset
));
844 // Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
845 // in order to extract the combinatorial control logic that feeds the box
846 // (i.e. clock enable, synchronous reset, etc.)
847 replace
.insert(std::make_pair(SigSig(port
,Q
), SigSig(port
,D
)));
848 // Since `flatten` above would have created wires named "<cell>.Q",
849 // extract the pre-techmap cell name
850 auto pos
= Q
.wire
->name
.str().rfind(".");
851 log_assert(pos
!= std::string::npos
);
852 IdString driver
= Q
.wire
->name
.substr(0, pos
);
853 // And drive the signal that was previously driven by "DFF.Q" (typically
854 // used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
855 // wire (which itself is driven an input port) we inserted above
856 Wire
*currQ
= holes_module
->wire(stringf("%s.$abc9_currQ", driver
.c_str()));
858 holes_module
->connect(Q
, currQ
);
861 else if (!cell
->type
.in("$_NOT_", "$_AND_"))
862 log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
866 for (auto &conn
: holes_module
->connections_
) {
867 auto it
= replace
.find(conn
);
868 if (it
!= replace
.end())
872 // Move into a new (temporary) design so that "clean" will only
873 // operate (and run checks on) this one module
874 RTLIL::Design
*holes_design
= new RTLIL::Design
;
875 module
->design
->modules_
.erase(holes_module
->name
);
876 holes_design
->add(holes_module
);
877 Pass::call(holes_design
, "opt -purge");
879 std::stringstream a_buffer
;
880 XAigerWriter
writer(holes_module
, true /* holes_mode */);
881 writer
.write_aiger(a_buffer
, false /*ascii_mode*/);
885 std::string buffer_str
= a_buffer
.str();
886 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
887 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
888 f
.write(buffer_str
.data(), buffer_str
.size());
895 std::string buffer_str
= h_buffer
.str();
896 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
897 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
898 f
.write(buffer_str
.data(), buffer_str
.size());
901 buffer_str
= i_buffer
.str();
902 buffer_size_be
= to_big_endian(buffer_str
.size());
903 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
904 f
.write(buffer_str
.data(), buffer_str
.size());
906 //buffer_str = o_buffer.str();
907 //buffer_size_be = to_big_endian(buffer_str.size());
908 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
909 //f.write(buffer_str.data(), buffer_str.size());
911 f
<< stringf("Generated by %s\n", yosys_version_str
);
913 module
->design
->scratchpad_set_int("write_xaiger.num_ands", and_map
.size());
914 module
->design
->scratchpad_set_int("write_xaiger.num_wires", aig_map
.size());
915 module
->design
->scratchpad_set_int("write_xaiger.num_inputs", input_bits
.size());
916 module
->design
->scratchpad_set_int("write_xaiger.num_outputs", output_bits
.size());
919 void write_map(std::ostream
&f
, bool verbose_map
)
921 dict
<int, string
> input_lines
;
922 dict
<int, string
> output_lines
;
923 dict
<int, string
> wire_lines
;
925 for (auto wire
: module
->wires())
927 //if (!verbose_map && wire->name[0] == '$')
930 SigSpec sig
= sigmap(wire
);
932 for (int i
= 0; i
< GetSize(wire
); i
++)
934 RTLIL::SigBit
b(wire
, i
);
935 if (input_bits
.count(b
)) {
936 int a
= aig_map
.at(b
);
937 log_assert((a
& 1) == 0);
938 input_lines
[a
] += stringf("input %d %d %s\n", (a
>> 1)-1, i
, log_id(wire
));
941 if (output_bits
.count(b
)) {
942 int o
= ordered_outputs
.at(b
);
944 output_lines
[o
] += stringf("output %d %d %s %d\n", o
- GetSize(co_bits
), i
, log_id(wire
), init
);
949 if (aig_map
.count(sig
[i
]) == 0)
952 int a
= aig_map
.at(sig
[i
]);
953 wire_lines
[a
] += stringf("wire %d %d %s\n", a
, i
, log_id(wire
));
959 for (auto &it
: input_lines
)
961 log_assert(input_lines
.size() == input_bits
.size());
964 for (auto cell
: box_list
)
965 f
<< stringf("box %d %d %s\n", box_count
++, 0, log_id(cell
->name
));
968 for (auto &it
: output_lines
)
970 log_assert(output_lines
.size() == output_bits
.size());
973 for (auto &it
: wire_lines
)
978 struct XAigerBackend
: public Backend
{
979 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
980 void help() YS_OVERRIDE
982 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
984 log(" write_xaiger [options] [filename]\n");
986 log("Write the current design to an XAIGER file. The design must be flattened and\n");
987 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
990 log(" write ASCII version of AIGER format\n");
992 log(" -map <filename>\n");
993 log(" write an extra file with port and box symbols\n");
995 log(" -vmap <filename>\n");
996 log(" like -map, but more verbose\n");
999 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1001 bool ascii_mode
= false;
1002 bool verbose_map
= false;
1003 std::string map_filename
;
1005 log_header(design
, "Executing XAIGER backend.\n");
1008 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1010 if (args
[argidx
] == "-ascii") {
1014 if (map_filename
.empty() && args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
1015 map_filename
= args
[++argidx
];
1018 if (map_filename
.empty() && args
[argidx
] == "-vmap" && argidx
+1 < args
.size()) {
1019 map_filename
= args
[++argidx
];
1025 extra_args(f
, filename
, args
, argidx
, !ascii_mode
);
1027 Module
*top_module
= design
->top_module();
1029 if (top_module
== nullptr)
1030 log_error("Can't find top module in current design!\n");
1032 XAigerWriter
writer(top_module
);
1033 writer
.write_aiger(*f
, ascii_mode
);
1035 if (!map_filename
.empty()) {
1037 mapf
.open(map_filename
.c_str(), std::ofstream::trunc
);
1039 log_error("Can't open file `%s' for writing: %s\n", map_filename
.c_str(), strerror(errno
));
1040 writer
.write_map(mapf
, verbose_map
);
1045 PRIVATE_NAMESPACE_END