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f49ecbedabda1d85be52b5184ab653ec824e5fd6
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50
51 USING_YOSYS_NAMESPACE
52 PRIVATE_NAMESPACE_BEGIN
53
54 inline int32_t to_big_endian(int32_t i32) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
56 return bswap32(i32);
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
58 return i32;
59 #else
60 #error "Unknown endianness"
61 #endif
62 }
63
64 void aiger_encode(std::ostream &f, int x)
65 {
66 log_assert(x >= 0);
67
68 while (x & ~0x7f) {
69 f.put((x & 0x7f) | 0x80);
70 x = x >> 7;
71 }
72
73 f.put(x);
74 }
75
76 struct XAigerWriter
77 {
78 Module *module;
79 SigMap sigmap;
80
81 pool<SigBit> input_bits, output_bits;
82 dict<SigBit, SigBit> not_map, alias_map;
83 dict<SigBit, pair<SigBit, SigBit>> and_map;
84 vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
85 vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
86
87 vector<pair<int, int>> aig_gates;
88 vector<int> aig_outputs;
89 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
90
91 dict<SigBit, int> aig_map;
92 dict<SigBit, int> ordered_outputs;
93
94 vector<Cell*> box_list;
95 bool omode = false;
96
97 int mkgate(int a0, int a1)
98 {
99 aig_m++, aig_a++;
100 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
101 return 2*aig_m;
102 }
103
104 int bit2aig(SigBit bit)
105 {
106 auto it = aig_map.find(bit);
107 if (it != aig_map.end()) {
108 log_assert(it->second >= 0);
109 return it->second;
110 }
111
112 // NB: Cannot use iterator returned from aig_map.insert()
113 // since this function is called recursively
114
115 int a = -1;
116 if (not_map.count(bit)) {
117 a = bit2aig(not_map.at(bit)) ^ 1;
118 } else
119 if (and_map.count(bit)) {
120 auto args = and_map.at(bit);
121 int a0 = bit2aig(args.first);
122 int a1 = bit2aig(args.second);
123 a = mkgate(a0, a1);
124 } else
125 if (alias_map.count(bit)) {
126 a = bit2aig(alias_map.at(bit));
127 }
128
129 if (bit == State::Sx || bit == State::Sz) {
130 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
131 a = aig_map.at(State::S0);
132 }
133
134 log_assert(a >= 0);
135 aig_map[bit] = a;
136 return a;
137 }
138
139 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
140 {
141 pool<SigBit> undriven_bits;
142 pool<SigBit> unused_bits;
143 pool<SigBit> keep_bits;
144
145 // promote public wires
146 for (auto wire : module->wires())
147 if (wire->name[0] == '\\')
148 sigmap.add(wire);
149
150 // promote input wires
151 for (auto wire : module->wires())
152 if (wire->port_input)
153 sigmap.add(wire);
154
155 // promote output wires
156 for (auto wire : module->wires())
157 if (wire->port_output)
158 sigmap.add(wire);
159
160 for (auto wire : module->wires())
161 {
162 bool keep = wire->attributes.count("\\keep");
163
164 for (int i = 0; i < GetSize(wire); i++)
165 {
166 SigBit wirebit(wire, i);
167 SigBit bit = sigmap(wirebit);
168
169 if (bit.wire) {
170 undriven_bits.insert(bit);
171 unused_bits.insert(bit);
172 }
173
174 if (keep)
175 keep_bits.insert(bit);
176
177 if (wire->port_input || keep) {
178 if (bit != wirebit)
179 alias_map[bit] = wirebit;
180 input_bits.insert(wirebit);
181 }
182
183 if (wire->port_output || keep) {
184 if (bit != RTLIL::Sx) {
185 if (bit != wirebit)
186 alias_map[wirebit] = bit;
187 output_bits.insert(wirebit);
188 }
189 else
190 log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
191 }
192 }
193 }
194
195 for (auto bit : input_bits)
196 undriven_bits.erase(sigmap(bit));
197 for (auto bit : output_bits)
198 if (!bit.wire->port_input)
199 unused_bits.erase(bit);
200
201 // TODO: Speed up toposort -- ultimately we care about
202 // box ordering, but not individual AIG cells
203 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
204 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
205 bool abc_box_seen = false;
206
207 for (auto cell : module->selected_cells()) {
208 if (cell->type == "$_NOT_")
209 {
210 SigBit A = sigmap(cell->getPort("\\A").as_bit());
211 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
212 unused_bits.erase(A);
213 undriven_bits.erase(Y);
214 not_map[Y] = A;
215 if (!holes_mode) {
216 toposort.node(cell->name);
217 bit_users[A].insert(cell->name);
218 bit_drivers[Y].insert(cell->name);
219 }
220 continue;
221 }
222
223 if (cell->type == "$_AND_")
224 {
225 SigBit A = sigmap(cell->getPort("\\A").as_bit());
226 SigBit B = sigmap(cell->getPort("\\B").as_bit());
227 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
228 unused_bits.erase(A);
229 unused_bits.erase(B);
230 undriven_bits.erase(Y);
231 and_map[Y] = make_pair(A, B);
232 if (!holes_mode) {
233 toposort.node(cell->name);
234 bit_users[A].insert(cell->name);
235 bit_users[B].insert(cell->name);
236 bit_drivers[Y].insert(cell->name);
237 }
238 continue;
239 }
240
241 log_assert(!holes_mode);
242
243 RTLIL::Module* inst_module = module->design->module(cell->type);
244 if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
245 abc_box_seen = true;
246
247 if (!holes_mode) {
248 toposort.node(cell->name);
249 for (const auto &conn : cell->connections()) {
250 if (cell->input(conn.first)) {
251 // Ignore inout for the sake of topographical ordering
252 if (cell->output(conn.first)) continue;
253 for (auto bit : sigmap(conn.second))
254 bit_users[bit].insert(cell->name);
255 }
256
257 if (cell->output(conn.first))
258 for (auto bit : sigmap(conn.second))
259 bit_drivers[bit].insert(cell->name);
260 }
261 }
262 }
263 else {
264 bool cell_known = cell->known();
265 for (const auto &c : cell->connections()) {
266 if (c.second.is_fully_const()) continue;
267 auto is_input = !cell_known || cell->input(c.first);
268 auto is_output = !cell_known || cell->output(c.first);
269 if (!is_input && !is_output)
270 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
271
272 if (is_input) {
273 for (auto b : c.second.bits()) {
274 Wire *w = b.wire;
275 if (!w) continue;
276 if (!w->port_output || !cell_known) {
277 SigBit I = sigmap(b);
278 if (I != b)
279 alias_map[b] = I;
280 output_bits.insert(b);
281 unused_bits.erase(b);
282
283 if (!cell_known)
284 keep_bits.insert(b);
285 }
286 }
287 }
288 if (is_output) {
289 for (auto b : c.second.bits()) {
290 Wire *w = b.wire;
291 if (!w) continue;
292 input_bits.insert(b);
293 SigBit O = sigmap(b);
294 if (O != b)
295 alias_map[O] = b;
296 undriven_bits.erase(O);
297 }
298 }
299 }
300 }
301
302 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
303 }
304
305 if (abc_box_seen) {
306 for (auto &it : bit_users)
307 if (bit_drivers.count(it.first))
308 for (auto driver_cell : bit_drivers.at(it.first))
309 for (auto user_cell : it.second)
310 toposort.edge(driver_cell, user_cell);
311
312 #if 0
313 toposort.analyze_loops = true;
314 #endif
315 bool no_loops = toposort.sort();
316 #if 0
317 unsigned i = 0;
318 for (auto &it : toposort.loops) {
319 log(" loop %d\n", i++);
320 for (auto cell_name : it) {
321 auto cell = module->cell(cell_name);
322 log_assert(cell);
323 log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
324 }
325 }
326 #endif
327 log_assert(no_loops);
328
329 pool<IdString> seen_boxes;
330 for (auto cell_name : toposort.sorted) {
331 RTLIL::Cell *cell = module->cell(cell_name);
332 log_assert(cell);
333
334 RTLIL::Module* box_module = module->design->module(cell->type);
335 if (!box_module || !box_module->attributes.count("\\abc_box_id"))
336 continue;
337
338 if (seen_boxes.insert(cell->type).second) {
339 auto it = box_module->attributes.find("\\abc_carry");
340 if (it != box_module->attributes.end()) {
341 RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
342 auto carry_in_out = it->second.decode_string();
343 auto pos = carry_in_out.find(',');
344 if (pos == std::string::npos)
345 log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
346 auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
347 carry_in = box_module->wire(carry_in_name);
348 if (!carry_in || !carry_in->port_input)
349 log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
350
351 auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
352 carry_out = box_module->wire(carry_out_name);
353 if (!carry_out || !carry_out->port_output)
354 log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
355
356 auto &ports = box_module->ports;
357 for (auto jt = ports.begin(); jt != ports.end(); ) {
358 RTLIL::Wire* w = box_module->wire(*jt);
359 log_assert(w);
360 if (w == carry_in || w == carry_out) {
361 jt = ports.erase(jt);
362 continue;
363 }
364 if (w->port_id > carry_in->port_id)
365 --w->port_id;
366 if (w->port_id > carry_out->port_id)
367 --w->port_id;
368 log_assert(w->port_input || w->port_output);
369 log_assert(ports[w->port_id-1] == w->name);
370 ++jt;
371 }
372 ports.push_back(carry_in->name);
373 carry_in->port_id = ports.size();
374 ports.push_back(carry_out->name);
375 carry_out->port_id = ports.size();
376 }
377 }
378
379 // Fully pad all unused input connections of this box cell with S0
380 // Fully pad all undriven output connections of this box cell with anonymous wires
381 // NB: Assume box_module->ports are sorted alphabetically
382 // (as RTLIL::Module::fixup_ports() would do)
383 for (const auto &port_name : box_module->ports) {
384 RTLIL::Wire* w = box_module->wire(port_name);
385 log_assert(w);
386 auto it = cell->connections_.find(port_name);
387 if (w->port_input) {
388 RTLIL::SigSpec rhs;
389 if (it != cell->connections_.end()) {
390 if (GetSize(it->second) < GetSize(w))
391 it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
392 rhs = it->second;
393 }
394 else {
395 rhs = RTLIL::SigSpec(State::S0, GetSize(w));
396 cell->setPort(port_name, rhs);
397 }
398
399 int offset = 0;
400 for (auto b : rhs.bits()) {
401 SigBit I = sigmap(b);
402 if (b == RTLIL::Sx)
403 b = State::S0;
404 else if (I != b) {
405 if (I == RTLIL::Sx)
406 alias_map[b] = State::S0;
407 else
408 alias_map[b] = I;
409 }
410 co_bits.emplace_back(b, cell, port_name, offset++, 0);
411 unused_bits.erase(b);
412 }
413 }
414 if (w->port_output) {
415 RTLIL::SigSpec rhs;
416 auto it = cell->connections_.find(w->name);
417 if (it != cell->connections_.end()) {
418 if (GetSize(it->second) < GetSize(w))
419 it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
420 rhs = it->second;
421 }
422 else {
423 rhs = module->addWire(NEW_ID, GetSize(w));
424 cell->setPort(port_name, rhs);
425 }
426
427 int offset = 0;
428 for (const auto &b : rhs.bits()) {
429 ci_bits.emplace_back(b, cell, port_name, offset++);
430 SigBit O = sigmap(b);
431 if (O != b)
432 alias_map[O] = b;
433 undriven_bits.erase(O);
434
435 auto jt = input_bits.find(b);
436 if (jt != input_bits.end()) {
437 log_assert(keep_bits.count(O));
438 input_bits.erase(b);
439 }
440 }
441 }
442 }
443 box_list.emplace_back(cell);
444 }
445
446 // TODO: Free memory from toposort, bit_drivers, bit_users
447 }
448
449 for (auto bit : input_bits) {
450 if (!output_bits.count(bit))
451 continue;
452 RTLIL::Wire *wire = bit.wire;
453 // If encountering an inout port, or a keep-ed wire, then create a new wire
454 // with $inout.out suffix, make it a PO driven by the existing inout, and
455 // inherit existing inout's drivers
456 if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
457 || keep_bits.count(bit)) {
458 RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
459 RTLIL::Wire *new_wire = module->wire(wire_name);
460 if (!new_wire)
461 new_wire = module->addWire(wire_name, GetSize(wire));
462 SigBit new_bit(new_wire, bit.offset);
463 module->connect(new_bit, bit);
464 if (not_map.count(bit)) {
465 auto a = not_map.at(bit);
466 not_map[new_bit] = a;
467 }
468 else if (and_map.count(bit)) {
469 auto a = and_map.at(bit);
470 and_map[new_bit] = a;
471 }
472 else if (alias_map.count(bit)) {
473 auto a = alias_map.at(bit);
474 alias_map[new_bit] = a;
475 }
476 else
477 alias_map[new_bit] = bit;
478 output_bits.erase(bit);
479 output_bits.insert(new_bit);
480 }
481 }
482
483 for (auto bit : unused_bits)
484 undriven_bits.erase(bit);
485
486 if (!undriven_bits.empty() && !holes_mode) {
487 undriven_bits.sort();
488 for (auto bit : undriven_bits) {
489 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
490 input_bits.insert(bit);
491 }
492 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
493 }
494
495 if (holes_mode) {
496 struct sort_by_port_id {
497 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
498 return a.wire->port_id < b.wire->port_id;
499 }
500 };
501 input_bits.sort(sort_by_port_id());
502 output_bits.sort(sort_by_port_id());
503 }
504 else {
505 input_bits.sort();
506 output_bits.sort();
507 }
508
509 not_map.sort();
510 and_map.sort();
511
512 aig_map[State::S0] = 0;
513 aig_map[State::S1] = 1;
514
515 for (auto bit : input_bits) {
516 aig_m++, aig_i++;
517 log_assert(!aig_map.count(bit));
518 aig_map[bit] = 2*aig_m;
519 }
520
521 for (auto &c : ci_bits) {
522 RTLIL::SigBit bit = std::get<0>(c);
523 aig_m++, aig_i++;
524 aig_map[bit] = 2*aig_m;
525 }
526
527 for (auto &c : co_bits) {
528 RTLIL::SigBit bit = std::get<0>(c);
529 std::get<4>(c) = ordered_outputs[bit] = aig_o++;
530 aig_outputs.push_back(bit2aig(bit));
531 }
532
533 for (auto bit : output_bits) {
534 ordered_outputs[bit] = aig_o++;
535 aig_outputs.push_back(bit2aig(bit));
536 }
537
538 if (output_bits.empty()) {
539 aig_o++;
540 aig_outputs.push_back(0);
541 omode = true;
542 }
543 }
544
545 void write_aiger(std::ostream &f, bool ascii_mode)
546 {
547 int aig_obc = aig_o;
548 int aig_obcj = aig_obc;
549 int aig_obcjf = aig_obcj;
550
551 log_assert(aig_m == aig_i + aig_l + aig_a);
552 log_assert(aig_obcjf == GetSize(aig_outputs));
553
554 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
555 f << stringf("\n");
556
557 if (ascii_mode)
558 {
559 for (int i = 0; i < aig_i; i++)
560 f << stringf("%d\n", 2*i+2);
561
562 for (int i = 0; i < aig_obc; i++)
563 f << stringf("%d\n", aig_outputs.at(i));
564
565 for (int i = aig_obc; i < aig_obcj; i++)
566 f << stringf("1\n");
567
568 for (int i = aig_obc; i < aig_obcj; i++)
569 f << stringf("%d\n", aig_outputs.at(i));
570
571 for (int i = aig_obcj; i < aig_obcjf; i++)
572 f << stringf("%d\n", aig_outputs.at(i));
573
574 for (int i = 0; i < aig_a; i++)
575 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
576 }
577 else
578 {
579 for (int i = 0; i < aig_obc; i++)
580 f << stringf("%d\n", aig_outputs.at(i));
581
582 for (int i = aig_obc; i < aig_obcj; i++)
583 f << stringf("1\n");
584
585 for (int i = aig_obc; i < aig_obcj; i++)
586 f << stringf("%d\n", aig_outputs.at(i));
587
588 for (int i = aig_obcj; i < aig_obcjf; i++)
589 f << stringf("%d\n", aig_outputs.at(i));
590
591 for (int i = 0; i < aig_a; i++) {
592 int lhs = 2*(aig_i+aig_l+i)+2;
593 int rhs0 = aig_gates.at(i).first;
594 int rhs1 = aig_gates.at(i).second;
595 int delta0 = lhs - rhs0;
596 int delta1 = rhs0 - rhs1;
597 aiger_encode(f, delta0);
598 aiger_encode(f, delta1);
599 }
600 }
601
602 f << "c";
603
604 if (!box_list.empty()) {
605 auto write_buffer = [](std::stringstream &buffer, int i32) {
606 int32_t i32_be = to_big_endian(i32);
607 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
608 };
609
610 std::stringstream h_buffer;
611 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
612 write_h_buffer(1);
613 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ci_bits));
614 write_h_buffer(input_bits.size() + ci_bits.size());
615 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(co_bits));
616 write_h_buffer(output_bits.size() + co_bits.size());
617 log_debug("piNum = %d\n", GetSize(input_bits));
618 write_h_buffer(input_bits.size());
619 log_debug("poNum = %d\n", GetSize(output_bits));
620 write_h_buffer(output_bits.size());
621 log_debug("boxNum = %d\n", GetSize(box_list));
622 write_h_buffer(box_list.size());
623
624 RTLIL::Module *holes_module = module->design->addModule("$__holes__");
625 log_assert(holes_module);
626
627 int port_id = 1;
628 int box_count = 0;
629 for (auto cell : box_list) {
630 RTLIL::Module* box_module = module->design->module(cell->type);
631 int box_inputs = 0, box_outputs = 0;
632 Cell *holes_cell = nullptr;
633 if (box_module->get_bool_attribute("\\whitebox")) {
634 holes_cell = holes_module->addCell(cell->name, cell->type);
635 holes_cell->parameters = cell->parameters;
636 }
637
638 // NB: Assume box_module->ports are sorted alphabetically
639 // (as RTLIL::Module::fixup_ports() would do)
640 for (const auto &port_name : box_module->ports) {
641 RTLIL::Wire *w = box_module->wire(port_name);
642 log_assert(w);
643 RTLIL::Wire *holes_wire;
644 RTLIL::SigSpec port_wire;
645 if (w->port_input) {
646 for (int i = 0; i < GetSize(w); i++) {
647 box_inputs++;
648 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
649 if (!holes_wire) {
650 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
651 holes_wire->port_input = true;
652 holes_wire->port_id = port_id++;
653 holes_module->ports.push_back(holes_wire->name);
654 }
655 if (holes_cell)
656 port_wire.append(holes_wire);
657 }
658 if (!port_wire.empty())
659 holes_cell->setPort(w->name, port_wire);
660 }
661 if (w->port_output) {
662 box_outputs += GetSize(w);
663 for (int i = 0; i < GetSize(w); i++) {
664 if (GetSize(w) == 1)
665 holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
666 else
667 holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
668 holes_wire->port_output = true;
669 holes_wire->port_id = port_id++;
670 holes_module->ports.push_back(holes_wire->name);
671 if (holes_cell)
672 port_wire.append(holes_wire);
673 else
674 holes_module->connect(holes_wire, State::S0);
675 }
676 if (!port_wire.empty())
677 holes_cell->setPort(w->name, port_wire);
678 }
679 }
680
681 write_h_buffer(box_inputs);
682 write_h_buffer(box_outputs);
683 write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
684 write_h_buffer(box_count++);
685 }
686
687 f << "h";
688 std::string buffer_str = h_buffer.str();
689 int32_t buffer_size_be = to_big_endian(buffer_str.size());
690 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
691 f.write(buffer_str.data(), buffer_str.size());
692
693 std::stringstream r_buffer;
694 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
695 write_r_buffer(0);
696
697 f << "r";
698 buffer_str = r_buffer.str();
699 buffer_size_be = to_big_endian(buffer_str.size());
700 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
701 f.write(buffer_str.data(), buffer_str.size());
702
703 if (holes_module) {
704 log_push();
705
706 // NB: fixup_ports() will sort ports by name
707 //holes_module->fixup_ports();
708 holes_module->check();
709
710 holes_module->design->selection_stack.emplace_back(false);
711 RTLIL::Selection& sel = holes_module->design->selection_stack.back();
712 sel.select(holes_module);
713
714 // TODO: Should not need to opt_merge if we only instantiate
715 // each box type once...
716 Pass::call(holes_module->design, "opt_merge -share_all");
717
718 Pass::call(holes_module->design, "flatten -wb");
719
720 // TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
721 // instead of per write_xaiger call
722 Pass::call(holes_module->design, "techmap");
723 Pass::call(holes_module->design, "aigmap");
724 for (auto cell : holes_module->cells())
725 if (!cell->type.in("$_NOT_", "$_AND_"))
726 log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
727
728 holes_module->design->selection_stack.pop_back();
729
730 // Move into a new (temporary) design so that "clean" will only
731 // operate (and run checks on) this one module
732 RTLIL::Design *holes_design = new RTLIL::Design;
733 holes_module->design->modules_.erase(holes_module->name);
734 holes_design->add(holes_module);
735 Pass::call(holes_design, "clean -purge");
736
737 std::stringstream a_buffer;
738 XAigerWriter writer(holes_module, true /* holes_mode */);
739 writer.write_aiger(a_buffer, false /*ascii_mode*/);
740
741 delete holes_design;
742
743 f << "a";
744 std::string buffer_str = a_buffer.str();
745 int32_t buffer_size_be = to_big_endian(buffer_str.size());
746 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
747 f.write(buffer_str.data(), buffer_str.size());
748
749 log_pop();
750 }
751 }
752
753 f << stringf("Generated by %s\n", yosys_version_str);
754 }
755
756 void write_map(std::ostream &f, bool verbose_map)
757 {
758 dict<int, string> input_lines;
759 dict<int, string> output_lines;
760 dict<int, string> wire_lines;
761
762 for (auto wire : module->wires())
763 {
764 //if (!verbose_map && wire->name[0] == '$')
765 // continue;
766
767 SigSpec sig = sigmap(wire);
768
769 for (int i = 0; i < GetSize(wire); i++)
770 {
771 RTLIL::SigBit b(wire, i);
772 if (input_bits.count(b)) {
773 int a = aig_map.at(b);
774 log_assert((a & 1) == 0);
775 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
776 }
777
778 if (output_bits.count(b)) {
779 int o = ordered_outputs.at(b);
780 output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), i, log_id(wire));
781 continue;
782 }
783
784 if (verbose_map) {
785 if (aig_map.count(sig[i]) == 0)
786 continue;
787
788 int a = aig_map.at(sig[i]);
789 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
790 }
791 }
792 }
793
794 input_lines.sort();
795 for (auto &it : input_lines)
796 f << it.second;
797 log_assert(input_lines.size() == input_bits.size());
798
799 int box_count = 0;
800 for (auto cell : box_list)
801 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
802
803 output_lines.sort();
804 for (auto &it : output_lines)
805 f << it.second;
806 log_assert(output_lines.size() == output_bits.size());
807 if (omode && output_bits.empty())
808 f << "output " << output_lines.size() << " 0 $__dummy__\n";
809
810 wire_lines.sort();
811 for (auto &it : wire_lines)
812 f << it.second;
813 }
814 };
815
816 struct XAigerBackend : public Backend {
817 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
818 void help() YS_OVERRIDE
819 {
820 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
821 log("\n");
822 log(" write_xaiger [options] [filename]\n");
823 log("\n");
824 log("Write the current design to an XAIGER file. The design must be flattened and\n");
825 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
826 log("\n");
827 log(" -ascii\n");
828 log(" write ASCII version of AIGER format\n");
829 log("\n");
830 log(" -map <filename>\n");
831 log(" write an extra file with port and latch symbols\n");
832 log("\n");
833 log(" -vmap <filename>\n");
834 log(" like -map, but more verbose\n");
835 log("\n");
836 }
837 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
838 {
839 bool ascii_mode = false;
840 bool verbose_map = false;
841 std::string map_filename;
842
843 log_header(design, "Executing XAIGER backend.\n");
844
845 size_t argidx;
846 for (argidx = 1; argidx < args.size(); argidx++)
847 {
848 if (args[argidx] == "-ascii") {
849 ascii_mode = true;
850 continue;
851 }
852 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
853 map_filename = args[++argidx];
854 continue;
855 }
856 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
857 map_filename = args[++argidx];
858 verbose_map = true;
859 continue;
860 }
861 break;
862 }
863 extra_args(f, filename, args, argidx);
864
865 Module *top_module = design->top_module();
866
867 if (top_module == nullptr)
868 log_error("Can't find top module in current design!\n");
869
870 XAigerWriter writer(top_module);
871 writer.write_aiger(*f, ascii_mode);
872
873 if (!map_filename.empty()) {
874 std::ofstream mapf;
875 mapf.open(map_filename.c_str(), std::ofstream::trunc);
876 if (mapf.fail())
877 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
878 writer.write_map(mapf, verbose_map);
879 }
880 }
881 } XAigerBackend;
882
883 PRIVATE_NAMESPACE_END