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xaiger: add check for $__ABC9_DELAY model
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
51
52 USING_YOSYS_NAMESPACE
53 PRIVATE_NAMESPACE_BEGIN
54
55 inline int32_t to_big_endian(int32_t i32) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 return bswap32(i32);
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
59 return i32;
60 #else
61 #error "Unknown endianness"
62 #endif
63 }
64
65 void aiger_encode(std::ostream &f, int x)
66 {
67 log_assert(x >= 0);
68
69 while (x & ~0x7f) {
70 f.put((x & 0x7f) | 0x80);
71 x = x >> 7;
72 }
73
74 f.put(x);
75 }
76
77 struct XAigerWriter
78 {
79 Module *module;
80 SigMap sigmap;
81
82 pool<SigBit> input_bits, output_bits;
83 dict<SigBit, SigBit> not_map, alias_map;
84 dict<SigBit, pair<SigBit, SigBit>> and_map;
85 vector<SigBit> ci_bits, co_bits;
86 dict<SigBit, Cell*> ff_bits;
87 dict<SigBit, float> arrival_times;
88
89 vector<pair<int, int>> aig_gates;
90 vector<int> aig_outputs;
91 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
92
93 dict<SigBit, int> aig_map;
94 dict<SigBit, int> ordered_outputs;
95
96 vector<Cell*> box_list;
97
98 int mkgate(int a0, int a1)
99 {
100 aig_m++, aig_a++;
101 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
102 return 2*aig_m;
103 }
104
105 int bit2aig(SigBit bit)
106 {
107 auto it = aig_map.find(bit);
108 if (it != aig_map.end()) {
109 log_assert(it->second >= 0);
110 return it->second;
111 }
112
113 // NB: Cannot use iterator returned from aig_map.insert()
114 // since this function is called recursively
115
116 int a = -1;
117 if (not_map.count(bit)) {
118 a = bit2aig(not_map.at(bit)) ^ 1;
119 } else
120 if (and_map.count(bit)) {
121 auto args = and_map.at(bit);
122 int a0 = bit2aig(args.first);
123 int a1 = bit2aig(args.second);
124 a = mkgate(a0, a1);
125 } else
126 if (alias_map.count(bit)) {
127 a = bit2aig(alias_map.at(bit));
128 }
129
130 if (bit == State::Sx || bit == State::Sz) {
131 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
132 a = aig_map.at(State::S0);
133 }
134
135 log_assert(a >= 0);
136 aig_map[bit] = a;
137 return a;
138 }
139
140 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
141 {
142 pool<SigBit> undriven_bits;
143 pool<SigBit> unused_bits;
144
145 // promote public wires
146 for (auto wire : module->wires())
147 if (wire->name[0] == '\\')
148 sigmap.add(wire);
149
150 // promote input wires
151 for (auto wire : module->wires())
152 if (wire->port_input)
153 sigmap.add(wire);
154
155 // promote keep wires
156 for (auto wire : module->wires())
157 if (wire->get_bool_attribute(ID::keep))
158 sigmap.add(wire);
159
160 for (auto wire : module->wires())
161 for (int i = 0; i < GetSize(wire); i++)
162 {
163 SigBit wirebit(wire, i);
164 SigBit bit = sigmap(wirebit);
165
166 if (bit.wire == nullptr) {
167 if (wire->port_output) {
168 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
169 output_bits.insert(wirebit);
170 }
171 continue;
172 }
173
174 undriven_bits.insert(bit);
175 unused_bits.insert(bit);
176
177 bool scc = wire->attributes.count(ID::abc9_scc);
178 if (wire->port_input || scc)
179 input_bits.insert(bit);
180
181 bool keep = wire->get_bool_attribute(ID::keep);
182 if (wire->port_output || keep || scc) {
183 if (bit != wirebit)
184 alias_map[wirebit] = bit;
185 output_bits.insert(wirebit);
186 }
187 }
188
189 TimingInfo timing;
190
191 for (auto cell : module->cells()) {
192 if (!cell->has_keep_attr()) {
193 if (cell->type == ID($_NOT_))
194 {
195 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
196 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
197 unused_bits.erase(A);
198 undriven_bits.erase(Y);
199 not_map[Y] = A;
200 continue;
201 }
202
203 if (cell->type == ID($_AND_))
204 {
205 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
206 SigBit B = sigmap(cell->getPort(ID::B).as_bit());
207 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
208 unused_bits.erase(A);
209 unused_bits.erase(B);
210 undriven_bits.erase(Y);
211 and_map[Y] = make_pair(A, B);
212 continue;
213 }
214
215 if (cell->type == ID($__ABC9_FF_) &&
216 // The presence of an abc9_mergeability attribute indicates
217 // that we do want to pass this flop to ABC
218 cell->attributes.count(ID::abc9_mergeability))
219 {
220 SigBit D = sigmap(cell->getPort(ID::D).as_bit());
221 SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
222 unused_bits.erase(D);
223 undriven_bits.erase(Q);
224 alias_map[Q] = D;
225 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
226 log_assert(r.second);
227 continue;
228 }
229
230 if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
231 continue;
232 }
233
234 RTLIL::Module* inst_module = module->design->module(cell->type);
235 if (inst_module) {
236 IdString derived_type = inst_module->derive(module->design, cell->parameters);
237 inst_module = module->design->module(derived_type);
238 log_assert(inst_module);
239
240 bool abc9_flop = false;
241 if (!cell->has_keep_attr()) {
242 auto it = cell->attributes.find(ID::abc9_box_seq);
243 if (it != cell->attributes.end()) {
244 int abc9_box_seq = it->second.as_int();
245 if (GetSize(box_list) <= abc9_box_seq)
246 box_list.resize(abc9_box_seq+1);
247 box_list[abc9_box_seq] = cell;
248 // Only flop boxes may have arrival times
249 // (all others are combinatorial)
250 abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
251 if (!abc9_flop)
252 continue;
253 }
254 }
255
256 if (!timing.count(derived_type))
257 timing.setup_module(inst_module);
258 auto &t = timing.at(derived_type).arrival;
259 for (const auto &conn : cell->connections()) {
260 auto port_wire = inst_module->wire(conn.first);
261 if (!port_wire->port_output)
262 continue;
263
264 for (int i = 0; i < GetSize(conn.second); i++) {
265 auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
266 if (d == 0)
267 continue;
268
269 #ifndef NDEBUG
270 if (ys_debug(1)) {
271 static std::set<std::tuple<IdString,IdString,int>> seen;
272 if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
273 log_id(cell->type), log_id(conn.first), i, d);
274 }
275 #endif
276 arrival_times[conn.second[i]] = d;
277 }
278 }
279
280 if (abc9_flop)
281 continue;
282 }
283 else {
284 if (cell->type == ID($__ABC9_DELAY))
285 log_error("Cell type '%s' not recognised. Check that '+/abc9_model.v' has been read.\n", cell->type.c_str());
286 }
287
288 bool cell_known = inst_module || cell->known();
289 for (const auto &c : cell->connections()) {
290 if (c.second.is_fully_const()) continue;
291 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
292 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
293 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
294 if (!is_input && !is_output)
295 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
296
297 if (is_input)
298 for (auto b : c.second) {
299 Wire *w = b.wire;
300 if (!w) continue;
301 // Do not add as PO if bit is already a PI
302 if (input_bits.count(b))
303 continue;
304 if (!w->port_output || !cell_known) {
305 SigBit I = sigmap(b);
306 if (I != b)
307 alias_map[b] = I;
308 output_bits.insert(b);
309 }
310 }
311 }
312
313 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
314 }
315
316 dict<IdString, std::vector<IdString>> box_ports;
317 for (auto cell : box_list) {
318 log_assert(cell);
319
320 RTLIL::Module* box_module = module->design->module(cell->type);
321 log_assert(box_module);
322 log_assert(box_module->attributes.count(ID::abc9_box_id) || box_module->get_bool_attribute(ID::abc9_flop));
323
324 auto r = box_ports.insert(cell->type);
325 if (r.second) {
326 // Make carry in the last PI, and carry out the last PO
327 // since ABC requires it this way
328 IdString carry_in, carry_out;
329 for (const auto &port_name : box_module->ports) {
330 auto w = box_module->wire(port_name);
331 log_assert(w);
332 if (w->get_bool_attribute(ID::abc9_carry)) {
333 if (w->port_input) {
334 if (carry_in != IdString())
335 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
336 carry_in = port_name;
337 }
338 if (w->port_output) {
339 if (carry_out != IdString())
340 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
341 carry_out = port_name;
342 }
343 }
344 else
345 r.first->second.push_back(port_name);
346 }
347
348 if (carry_in != IdString() && carry_out == IdString())
349 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
350 if (carry_in == IdString() && carry_out != IdString())
351 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
352 if (carry_in != IdString()) {
353 r.first->second.push_back(carry_in);
354 r.first->second.push_back(carry_out);
355 }
356 }
357
358 for (auto port_name : r.first->second) {
359 auto w = box_module->wire(port_name);
360 log_assert(w);
361 auto rhs = cell->connections_.at(port_name, SigSpec());
362 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
363 if (w->port_input)
364 for (auto b : rhs) {
365 SigBit I = sigmap(b);
366 if (b == RTLIL::Sx)
367 b = State::S0;
368 else if (I != b) {
369 if (I == RTLIL::Sx)
370 alias_map[b] = State::S0;
371 else
372 alias_map[b] = I;
373 }
374 co_bits.emplace_back(b);
375 unused_bits.erase(I);
376 }
377 if (w->port_output)
378 for (const auto &b : rhs) {
379 SigBit O = sigmap(b);
380 if (O != b)
381 alias_map[O] = b;
382 ci_bits.emplace_back(b);
383 undriven_bits.erase(O);
384 }
385 }
386
387 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
388 if (box_module->get_bool_attribute(ID::abc9_flop)) {
389 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
390 if (rhs.empty())
391 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
392
393 for (auto b : rhs) {
394 SigBit I = sigmap(b);
395 if (b == RTLIL::Sx)
396 b = State::S0;
397 else if (I != b) {
398 if (I == RTLIL::Sx)
399 alias_map[b] = State::S0;
400 else
401 alias_map[b] = I;
402 }
403 co_bits.emplace_back(b);
404 unused_bits.erase(I);
405 }
406 }
407 }
408
409 for (auto bit : input_bits)
410 undriven_bits.erase(bit);
411 for (auto bit : output_bits)
412 unused_bits.erase(sigmap(bit));
413 for (auto bit : unused_bits)
414 undriven_bits.erase(bit);
415
416 // Make all undriven bits a primary input
417 for (auto bit : undriven_bits) {
418 input_bits.insert(bit);
419 undriven_bits.erase(bit);
420 }
421
422 if (holes_mode) {
423 struct sort_by_port_id {
424 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
425 return a.wire->port_id < b.wire->port_id ||
426 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
427 }
428 };
429 input_bits.sort(sort_by_port_id());
430 output_bits.sort(sort_by_port_id());
431 }
432
433 aig_map[State::S0] = 0;
434 aig_map[State::S1] = 1;
435
436 for (const auto &bit : input_bits) {
437 aig_m++, aig_i++;
438 log_assert(!aig_map.count(bit));
439 aig_map[bit] = 2*aig_m;
440 }
441
442 for (const auto &i : ff_bits) {
443 const Cell *cell = i.second;
444 const SigBit &q = sigmap(cell->getPort(ID::Q));
445 aig_m++, aig_i++;
446 log_assert(!aig_map.count(q));
447 aig_map[q] = 2*aig_m;
448 }
449
450 for (auto &bit : ci_bits) {
451 aig_m++, aig_i++;
452 // 1'bx may exist here due to a box output
453 // that has been padded to its full width
454 if (bit == State::Sx)
455 continue;
456 log_assert(!aig_map.count(bit));
457 aig_map[bit] = 2*aig_m;
458 }
459
460 for (auto bit : co_bits) {
461 ordered_outputs[bit] = aig_o++;
462 aig_outputs.push_back(bit2aig(bit));
463 }
464
465 for (const auto &bit : output_bits) {
466 ordered_outputs[bit] = aig_o++;
467 int aig;
468 // Unlike bit2aig() which checks aig_map first for
469 // inout/scc bits, since aig_map will point to
470 // the PI, first attempt to find the NOT/AND driver
471 // before resorting to an aig_map lookup (which
472 // could be another PO)
473 if (input_bits.count(bit)) {
474 if (not_map.count(bit)) {
475 aig = bit2aig(not_map.at(bit)) ^ 1;
476 } else if (and_map.count(bit)) {
477 auto args = and_map.at(bit);
478 int a0 = bit2aig(args.first);
479 int a1 = bit2aig(args.second);
480 aig = mkgate(a0, a1);
481 }
482 else
483 aig = aig_map.at(bit);
484 }
485 else
486 aig = bit2aig(bit);
487 aig_outputs.push_back(aig);
488 }
489
490 for (auto &i : ff_bits) {
491 const SigBit &d = i.first;
492 aig_o++;
493 aig_outputs.push_back(aig_map.at(d));
494 }
495 }
496
497 void write_aiger(std::ostream &f, bool ascii_mode)
498 {
499 int aig_obc = aig_o;
500 int aig_obcj = aig_obc;
501 int aig_obcjf = aig_obcj;
502
503 log_assert(aig_m == aig_i + aig_l + aig_a);
504 log_assert(aig_obcjf == GetSize(aig_outputs));
505
506 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
507 f << stringf("\n");
508
509 if (ascii_mode)
510 {
511 for (int i = 0; i < aig_i; i++)
512 f << stringf("%d\n", 2*i+2);
513
514 for (int i = 0; i < aig_obc; i++)
515 f << stringf("%d\n", aig_outputs.at(i));
516
517 for (int i = aig_obc; i < aig_obcj; i++)
518 f << stringf("1\n");
519
520 for (int i = aig_obc; i < aig_obcj; i++)
521 f << stringf("%d\n", aig_outputs.at(i));
522
523 for (int i = aig_obcj; i < aig_obcjf; i++)
524 f << stringf("%d\n", aig_outputs.at(i));
525
526 for (int i = 0; i < aig_a; i++)
527 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
528 }
529 else
530 {
531 for (int i = 0; i < aig_obc; i++)
532 f << stringf("%d\n", aig_outputs.at(i));
533
534 for (int i = aig_obc; i < aig_obcj; i++)
535 f << stringf("1\n");
536
537 for (int i = aig_obc; i < aig_obcj; i++)
538 f << stringf("%d\n", aig_outputs.at(i));
539
540 for (int i = aig_obcj; i < aig_obcjf; i++)
541 f << stringf("%d\n", aig_outputs.at(i));
542
543 for (int i = 0; i < aig_a; i++) {
544 int lhs = 2*(aig_i+aig_l+i)+2;
545 int rhs0 = aig_gates.at(i).first;
546 int rhs1 = aig_gates.at(i).second;
547 int delta0 = lhs - rhs0;
548 int delta1 = rhs0 - rhs1;
549 aiger_encode(f, delta0);
550 aiger_encode(f, delta1);
551 }
552 }
553
554 f << "c";
555
556 auto write_buffer = [](std::stringstream &buffer, int i32) {
557 int32_t i32_be = to_big_endian(i32);
558 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
559 };
560 std::stringstream h_buffer;
561 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
562 write_h_buffer(1);
563 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
564 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
565 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
566 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
567 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
568 write_h_buffer(input_bits.size() + ff_bits.size());
569 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
570 write_h_buffer(output_bits.size() + ff_bits.size());
571 log_debug("boxNum = %d\n", GetSize(box_list));
572 write_h_buffer(box_list.size());
573
574 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
575 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
576 };
577 std::stringstream i_buffer;
578 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
579 for (auto bit : input_bits)
580 write_i_buffer(arrival_times.at(bit, 0));
581 //std::stringstream o_buffer;
582 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
583 //for (auto bit : output_bits)
584 // write_o_buffer(0);
585
586 if (!box_list.empty() || !ff_bits.empty()) {
587 dict<IdString, std::tuple<int,int,int>> cell_cache;
588
589 int box_count = 0;
590 for (auto cell : box_list) {
591 log_assert(cell);
592
593 RTLIL::Module* box_module = module->design->module(cell->type);
594 log_assert(box_module);
595
596 IdString derived_type = box_module->derive(box_module->design, cell->parameters);
597 box_module = box_module->design->module(derived_type);
598 log_assert(box_module);
599
600 auto r = cell_cache.insert(derived_type);
601 auto &v = r.first->second;
602 if (r.second) {
603 int box_inputs = 0, box_outputs = 0;
604 for (auto port_name : box_module->ports) {
605 RTLIL::Wire *w = box_module->wire(port_name);
606 log_assert(w);
607 if (w->port_input)
608 box_inputs += GetSize(w);
609 if (w->port_output)
610 box_outputs += GetSize(w);
611 }
612
613 // For flops only, create an extra 1-bit input that drives a new wire
614 // called "<cell>.abc9_ff.Q" that is used below
615 if (box_module->get_bool_attribute(ID::abc9_flop))
616 box_inputs++;
617
618 std::get<0>(v) = box_inputs;
619 std::get<1>(v) = box_outputs;
620 std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
621 }
622
623 write_h_buffer(std::get<0>(v));
624 write_h_buffer(std::get<1>(v));
625 write_h_buffer(std::get<2>(v));
626 write_h_buffer(box_count++);
627 }
628
629 std::stringstream r_buffer;
630 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
631 log_debug("flopNum = %d\n", GetSize(ff_bits));
632 write_r_buffer(ff_bits.size());
633
634 std::stringstream s_buffer;
635 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
636 write_s_buffer(ff_bits.size());
637
638 for (const auto &i : ff_bits) {
639 const SigBit &d = i.first;
640 const Cell *cell = i.second;
641
642 int mergeability = cell->attributes.at(ID::abc9_mergeability).as_int();
643 log_assert(mergeability > 0);
644 write_r_buffer(mergeability);
645
646 Const init = cell->attributes.at(ID::abc9_init, State::Sx);
647 log_assert(GetSize(init) == 1);
648 if (init == State::S1)
649 write_s_buffer(1);
650 else if (init == State::S0)
651 write_s_buffer(0);
652 else {
653 log_assert(init == State::Sx);
654 write_s_buffer(0);
655 }
656
657 // Use arrival time from output of flop box
658 write_i_buffer(arrival_times.at(d, 0));
659 //write_o_buffer(0);
660 }
661
662 f << "r";
663 std::string buffer_str = r_buffer.str();
664 int32_t buffer_size_be = to_big_endian(buffer_str.size());
665 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
666 f.write(buffer_str.data(), buffer_str.size());
667
668 f << "s";
669 buffer_str = s_buffer.str();
670 buffer_size_be = to_big_endian(buffer_str.size());
671 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
672 f.write(buffer_str.data(), buffer_str.size());
673
674 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
675 if (holes_module) {
676 std::stringstream a_buffer;
677 XAigerWriter writer(holes_module, true /* holes_mode */);
678 writer.write_aiger(a_buffer, false /*ascii_mode*/);
679
680 f << "a";
681 std::string buffer_str = a_buffer.str();
682 int32_t buffer_size_be = to_big_endian(buffer_str.size());
683 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
684 f.write(buffer_str.data(), buffer_str.size());
685 }
686 }
687
688 f << "h";
689 std::string buffer_str = h_buffer.str();
690 int32_t buffer_size_be = to_big_endian(buffer_str.size());
691 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
692 f.write(buffer_str.data(), buffer_str.size());
693
694 f << "i";
695 buffer_str = i_buffer.str();
696 buffer_size_be = to_big_endian(buffer_str.size());
697 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
698 f.write(buffer_str.data(), buffer_str.size());
699 //f << "o";
700 //buffer_str = o_buffer.str();
701 //buffer_size_be = to_big_endian(buffer_str.size());
702 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
703 //f.write(buffer_str.data(), buffer_str.size());
704
705 f << stringf("Generated by %s\n", yosys_version_str);
706
707 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
708 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
709 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
710 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
711 }
712
713 void write_map(std::ostream &f)
714 {
715 dict<int, string> input_lines;
716 dict<int, string> output_lines;
717
718 for (auto wire : module->wires())
719 {
720 SigSpec sig = sigmap(wire);
721
722 for (int i = 0; i < GetSize(wire); i++)
723 {
724 RTLIL::SigBit b(wire, i);
725 if (input_bits.count(b)) {
726 int a = aig_map.at(b);
727 log_assert((a & 1) == 0);
728 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
729 }
730
731 if (output_bits.count(b)) {
732 int o = ordered_outputs.at(b);
733 int init = 2;
734 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
735 continue;
736 }
737 }
738 }
739
740 input_lines.sort();
741 for (auto &it : input_lines)
742 f << it.second;
743 log_assert(input_lines.size() == input_bits.size());
744
745 int box_count = 0;
746 for (auto cell : box_list)
747 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
748
749 output_lines.sort();
750 for (auto &it : output_lines)
751 f << it.second;
752 log_assert(output_lines.size() == output_bits.size());
753 }
754 };
755
756 struct XAigerBackend : public Backend {
757 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
758 void help() YS_OVERRIDE
759 {
760 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
761 log("\n");
762 log(" write_xaiger [options] [filename]\n");
763 log("\n");
764 log("Write the top module (according to the (* top *) attribute or if only one module\n");
765 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
766 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
767 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
768 log("module, if it exists.\n");
769 log("\n");
770 log(" -ascii\n");
771 log(" write ASCII version of AIGER format\n");
772 log("\n");
773 log(" -map <filename>\n");
774 log(" write an extra file with port and box symbols\n");
775 log("\n");
776 }
777 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
778 {
779 bool ascii_mode = false;
780 std::string map_filename;
781
782 log_header(design, "Executing XAIGER backend.\n");
783
784 size_t argidx;
785 for (argidx = 1; argidx < args.size(); argidx++)
786 {
787 if (args[argidx] == "-ascii") {
788 ascii_mode = true;
789 continue;
790 }
791 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
792 map_filename = args[++argidx];
793 continue;
794 }
795 break;
796 }
797 extra_args(f, filename, args, argidx, !ascii_mode);
798
799 Module *top_module = design->top_module();
800
801 if (top_module == nullptr)
802 log_error("Can't find top module in current design!\n");
803
804 if (!design->selected_whole_module(top_module))
805 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
806
807 if (!top_module->processes.empty())
808 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
809 if (!top_module->memories.empty())
810 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
811
812 XAigerWriter writer(top_module);
813 writer.write_aiger(*f, ascii_mode);
814
815 if (!map_filename.empty()) {
816 std::ofstream mapf;
817 mapf.open(map_filename.c_str(), std::ofstream::trunc);
818 if (mapf.fail())
819 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
820 writer.write_map(mapf);
821 }
822 }
823 } XAigerBackend;
824
825 PRIVATE_NAMESPACE_END