xilinx: improve specify functionality
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50
51 USING_YOSYS_NAMESPACE
52 PRIVATE_NAMESPACE_BEGIN
53
54 inline int32_t to_big_endian(int32_t i32) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
56 return bswap32(i32);
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
58 return i32;
59 #else
60 #error "Unknown endianness"
61 #endif
62 }
63
64 void aiger_encode(std::ostream &f, int x)
65 {
66 log_assert(x >= 0);
67
68 while (x & ~0x7f) {
69 f.put((x & 0x7f) | 0x80);
70 x = x >> 7;
71 }
72
73 f.put(x);
74 }
75
76 struct XAigerWriter
77 {
78 Module *module;
79 SigMap sigmap;
80
81 pool<SigBit> input_bits, output_bits;
82 dict<SigBit, SigBit> not_map, alias_map;
83 dict<SigBit, pair<SigBit, SigBit>> and_map;
84 vector<SigBit> ci_bits, co_bits;
85 dict<SigBit, Cell*> ff_bits;
86 dict<SigBit, float> arrival_times;
87
88 vector<pair<int, int>> aig_gates;
89 vector<int> aig_outputs;
90 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
91
92 dict<SigBit, int> aig_map;
93 dict<SigBit, int> ordered_outputs;
94
95 vector<Cell*> box_list;
96
97 int mkgate(int a0, int a1)
98 {
99 aig_m++, aig_a++;
100 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
101 return 2*aig_m;
102 }
103
104 int bit2aig(SigBit bit)
105 {
106 auto it = aig_map.find(bit);
107 if (it != aig_map.end()) {
108 log_assert(it->second >= 0);
109 return it->second;
110 }
111
112 // NB: Cannot use iterator returned from aig_map.insert()
113 // since this function is called recursively
114
115 int a = -1;
116 if (not_map.count(bit)) {
117 a = bit2aig(not_map.at(bit)) ^ 1;
118 } else
119 if (and_map.count(bit)) {
120 auto args = and_map.at(bit);
121 int a0 = bit2aig(args.first);
122 int a1 = bit2aig(args.second);
123 a = mkgate(a0, a1);
124 } else
125 if (alias_map.count(bit)) {
126 a = bit2aig(alias_map.at(bit));
127 }
128
129 if (bit == State::Sx || bit == State::Sz) {
130 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
131 a = aig_map.at(State::S0);
132 }
133
134 log_assert(a >= 0);
135 aig_map[bit] = a;
136 return a;
137 }
138
139 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
140 {
141 pool<SigBit> undriven_bits;
142 pool<SigBit> unused_bits;
143
144 // promote public wires
145 for (auto wire : module->wires())
146 if (wire->name[0] == '\\')
147 sigmap.add(wire);
148
149 // promote input wires
150 for (auto wire : module->wires())
151 if (wire->port_input)
152 sigmap.add(wire);
153
154 // promote keep wires
155 for (auto wire : module->wires())
156 if (wire->get_bool_attribute(ID::keep))
157 sigmap.add(wire);
158
159 for (auto wire : module->wires())
160 for (int i = 0; i < GetSize(wire); i++)
161 {
162 SigBit wirebit(wire, i);
163 SigBit bit = sigmap(wirebit);
164
165 if (bit.wire == nullptr) {
166 if (wire->port_output) {
167 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
168 output_bits.insert(wirebit);
169 }
170 continue;
171 }
172
173 undriven_bits.insert(bit);
174 unused_bits.insert(bit);
175
176 bool keep = wire->get_bool_attribute(ID::keep);
177 if (wire->port_input || keep)
178 input_bits.insert(bit);
179
180 if (wire->port_output || keep) {
181 if (bit != wirebit)
182 alias_map[wirebit] = bit;
183 output_bits.insert(wirebit);
184 }
185 }
186
187 dict<IdString,dict<IdString,std::vector<int>>> arrivals_cache;
188 for (auto cell : module->cells()) {
189 RTLIL::Module* inst_module = module->design->module(cell->type);
190 if (!cell->has_keep_attr()) {
191 if (cell->type == "$_NOT_")
192 {
193 SigBit A = sigmap(cell->getPort("\\A").as_bit());
194 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
195 unused_bits.erase(A);
196 undriven_bits.erase(Y);
197 not_map[Y] = A;
198 continue;
199 }
200
201 if (cell->type == "$_AND_")
202 {
203 SigBit A = sigmap(cell->getPort("\\A").as_bit());
204 SigBit B = sigmap(cell->getPort("\\B").as_bit());
205 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
206 unused_bits.erase(A);
207 unused_bits.erase(B);
208 undriven_bits.erase(Y);
209 and_map[Y] = make_pair(A, B);
210 continue;
211 }
212
213 if (cell->type == "$__ABC9_FF_" &&
214 // The presence of an abc9_mergeability attribute indicates
215 // that we do want to pass this flop to ABC
216 cell->attributes.count("\\abc9_mergeability"))
217 {
218 SigBit D = sigmap(cell->getPort("\\D").as_bit());
219 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
220 unused_bits.erase(D);
221 undriven_bits.erase(Q);
222 alias_map[Q] = D;
223 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
224 log_assert(r.second);
225 if (input_bits.erase(Q))
226 log_assert(Q.wire->attributes.count(ID::keep));
227 continue;
228 }
229
230 if (cell->type.in("$specify2", "$specify3", "$specrule"))
231 continue;
232
233 if (inst_module) {
234 bool abc9_flop = false;
235 auto it = cell->attributes.find("\\abc9_box_seq");
236 if (it != cell->attributes.end()) {
237 int abc9_box_seq = it->second.as_int();
238 if (GetSize(box_list) <= abc9_box_seq)
239 box_list.resize(abc9_box_seq+1);
240 box_list[abc9_box_seq] = cell;
241 // Only flop boxes may have arrival times
242 // (all others are combinatorial)
243 abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
244 if (!abc9_flop)
245 continue;
246 }
247
248 auto &cell_arrivals = arrivals_cache[cell->type];
249 for (const auto &conn : cell->connections()) {
250 auto port_wire = inst_module->wire(conn.first);
251 if (!port_wire->port_output)
252 continue;
253
254 auto r = cell_arrivals.insert(conn.first);
255 auto &arrivals = r.first->second;
256 if (r.second) {
257 auto it = port_wire->attributes.find("\\abc9_arrival");
258 if (it == port_wire->attributes.end())
259 continue;
260 if (it->second.flags == 0)
261 arrivals.emplace_back(it->second.as_int());
262 else
263 for (const auto &tok : split_tokens(it->second.decode_string()))
264 arrivals.push_back(atoi(tok.c_str()));
265 }
266
267 if (arrivals.empty())
268 continue;
269
270 if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
271 log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
272 GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
273
274 auto jt = arrivals.begin();
275 #ifndef NDEBUG
276 if (ys_debug(1)) {
277 static std::set<std::pair<IdString,IdString>> seen;
278 if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt);
279 }
280 #endif
281 for (auto bit : sigmap(conn.second)) {
282 arrival_times[bit] = *jt;
283 if (arrivals.size() > 1)
284 jt++;
285 }
286 }
287
288 if (abc9_flop)
289 continue;
290 }
291 }
292
293 bool cell_known = inst_module || cell->known();
294 for (const auto &c : cell->connections()) {
295 if (c.second.is_fully_const()) continue;
296 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
297 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
298 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
299 if (!is_input && !is_output)
300 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
301
302 if (is_input)
303 for (auto b : c.second) {
304 Wire *w = b.wire;
305 if (!w) continue;
306 // Do not add as PO if bit is already a PI
307 if (input_bits.count(b))
308 continue;
309 if (!w->port_output || !cell_known) {
310 SigBit I = sigmap(b);
311 if (I != b)
312 alias_map[b] = I;
313 output_bits.insert(b);
314 }
315 }
316 }
317
318 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
319 }
320
321 dict<IdString, std::vector<IdString>> box_ports;
322 for (auto cell : box_list) {
323 log_assert(cell);
324
325 RTLIL::Module* box_module = module->design->module(cell->type);
326 log_assert(box_module);
327 log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
328
329 auto r = box_ports.insert(cell->type);
330 if (r.second) {
331 // Make carry in the last PI, and carry out the last PO
332 // since ABC requires it this way
333 IdString carry_in, carry_out;
334 for (const auto &port_name : box_module->ports) {
335 auto w = box_module->wire(port_name);
336 log_assert(w);
337 if (w->get_bool_attribute("\\abc9_carry")) {
338 if (w->port_input) {
339 if (carry_in != IdString())
340 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
341 carry_in = port_name;
342 }
343 if (w->port_output) {
344 if (carry_out != IdString())
345 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
346 carry_out = port_name;
347 }
348 }
349 else
350 r.first->second.push_back(port_name);
351 }
352
353 if (carry_in != IdString() && carry_out == IdString())
354 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
355 if (carry_in == IdString() && carry_out != IdString())
356 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
357 if (carry_in != IdString()) {
358 r.first->second.push_back(carry_in);
359 r.first->second.push_back(carry_out);
360 }
361 }
362
363 for (auto port_name : r.first->second) {
364 auto w = box_module->wire(port_name);
365 log_assert(w);
366 auto rhs = cell->connections_.at(port_name, SigSpec());
367 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
368 if (w->port_input)
369 for (auto b : rhs) {
370 SigBit I = sigmap(b);
371 if (b == RTLIL::Sx)
372 b = State::S0;
373 else if (I != b) {
374 if (I == RTLIL::Sx)
375 alias_map[b] = State::S0;
376 else
377 alias_map[b] = I;
378 }
379 co_bits.emplace_back(b);
380 unused_bits.erase(I);
381 }
382 if (w->port_output)
383 for (const auto &b : rhs) {
384 SigBit O = sigmap(b);
385 if (O != b)
386 alias_map[O] = b;
387 ci_bits.emplace_back(b);
388 undriven_bits.erase(O);
389 // If PI and CI, then must be a (* keep *) wire
390 if (input_bits.erase(O)) {
391 log_assert(output_bits.count(O));
392 log_assert(O.wire->get_bool_attribute(ID::keep));
393 }
394 }
395 }
396
397 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
398 if (box_module->get_bool_attribute("\\abc9_flop")) {
399 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
400 if (rhs.empty())
401 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
402
403 for (auto b : rhs) {
404 SigBit I = sigmap(b);
405 if (b == RTLIL::Sx)
406 b = State::S0;
407 else if (I != b) {
408 if (I == RTLIL::Sx)
409 alias_map[b] = State::S0;
410 else
411 alias_map[b] = I;
412 }
413 co_bits.emplace_back(b);
414 unused_bits.erase(I);
415 }
416 }
417 }
418
419 for (auto bit : input_bits)
420 undriven_bits.erase(bit);
421 for (auto bit : output_bits)
422 unused_bits.erase(sigmap(bit));
423 for (auto bit : unused_bits)
424 undriven_bits.erase(bit);
425
426 // Make all undriven bits a primary input
427 for (auto bit : undriven_bits) {
428 input_bits.insert(bit);
429 undriven_bits.erase(bit);
430 }
431
432 if (holes_mode) {
433 struct sort_by_port_id {
434 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
435 return a.wire->port_id < b.wire->port_id ||
436 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
437 }
438 };
439 input_bits.sort(sort_by_port_id());
440 output_bits.sort(sort_by_port_id());
441 }
442
443 aig_map[State::S0] = 0;
444 aig_map[State::S1] = 1;
445
446 for (const auto &bit : input_bits) {
447 aig_m++, aig_i++;
448 log_assert(!aig_map.count(bit));
449 aig_map[bit] = 2*aig_m;
450 }
451
452 for (const auto &i : ff_bits) {
453 const Cell *cell = i.second;
454 const SigBit &q = sigmap(cell->getPort("\\Q"));
455 aig_m++, aig_i++;
456 log_assert(!aig_map.count(q));
457 aig_map[q] = 2*aig_m;
458 }
459
460 for (auto &bit : ci_bits) {
461 aig_m++, aig_i++;
462 // 1'bx may exist here due to a box output
463 // that has been padded to its full width
464 if (bit == State::Sx)
465 continue;
466 log_assert(!aig_map.count(bit));
467 aig_map[bit] = 2*aig_m;
468 }
469
470 for (auto bit : co_bits) {
471 ordered_outputs[bit] = aig_o++;
472 aig_outputs.push_back(bit2aig(bit));
473 }
474
475 for (const auto &bit : output_bits) {
476 ordered_outputs[bit] = aig_o++;
477 int aig;
478 // Unlike bit2aig() which checks aig_map first, for
479 // inout/keep bits, since aig_map will point to
480 // the PI, first attempt to find the NOT/AND driver
481 // before resorting to an aig_map lookup (which
482 // could be another PO)
483 if (input_bits.count(bit)) {
484 if (not_map.count(bit)) {
485 aig = bit2aig(not_map.at(bit)) ^ 1;
486 } else if (and_map.count(bit)) {
487 auto args = and_map.at(bit);
488 int a0 = bit2aig(args.first);
489 int a1 = bit2aig(args.second);
490 aig = mkgate(a0, a1);
491 }
492 else
493 aig = aig_map.at(bit);
494 }
495 else
496 aig = bit2aig(bit);
497 aig_outputs.push_back(aig);
498 }
499
500 for (auto &i : ff_bits) {
501 const SigBit &d = i.first;
502 aig_o++;
503 aig_outputs.push_back(aig_map.at(d));
504 }
505 }
506
507 void write_aiger(std::ostream &f, bool ascii_mode)
508 {
509 int aig_obc = aig_o;
510 int aig_obcj = aig_obc;
511 int aig_obcjf = aig_obcj;
512
513 log_assert(aig_m == aig_i + aig_l + aig_a);
514 log_assert(aig_obcjf == GetSize(aig_outputs));
515
516 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
517 f << stringf("\n");
518
519 if (ascii_mode)
520 {
521 for (int i = 0; i < aig_i; i++)
522 f << stringf("%d\n", 2*i+2);
523
524 for (int i = 0; i < aig_obc; i++)
525 f << stringf("%d\n", aig_outputs.at(i));
526
527 for (int i = aig_obc; i < aig_obcj; i++)
528 f << stringf("1\n");
529
530 for (int i = aig_obc; i < aig_obcj; i++)
531 f << stringf("%d\n", aig_outputs.at(i));
532
533 for (int i = aig_obcj; i < aig_obcjf; i++)
534 f << stringf("%d\n", aig_outputs.at(i));
535
536 for (int i = 0; i < aig_a; i++)
537 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
538 }
539 else
540 {
541 for (int i = 0; i < aig_obc; i++)
542 f << stringf("%d\n", aig_outputs.at(i));
543
544 for (int i = aig_obc; i < aig_obcj; i++)
545 f << stringf("1\n");
546
547 for (int i = aig_obc; i < aig_obcj; i++)
548 f << stringf("%d\n", aig_outputs.at(i));
549
550 for (int i = aig_obcj; i < aig_obcjf; i++)
551 f << stringf("%d\n", aig_outputs.at(i));
552
553 for (int i = 0; i < aig_a; i++) {
554 int lhs = 2*(aig_i+aig_l+i)+2;
555 int rhs0 = aig_gates.at(i).first;
556 int rhs1 = aig_gates.at(i).second;
557 int delta0 = lhs - rhs0;
558 int delta1 = rhs0 - rhs1;
559 aiger_encode(f, delta0);
560 aiger_encode(f, delta1);
561 }
562 }
563
564 f << "c";
565
566 auto write_buffer = [](std::stringstream &buffer, int i32) {
567 int32_t i32_be = to_big_endian(i32);
568 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
569 };
570 std::stringstream h_buffer;
571 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
572 write_h_buffer(1);
573 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
574 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
575 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
576 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
577 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
578 write_h_buffer(input_bits.size() + ff_bits.size());
579 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
580 write_h_buffer(output_bits.size() + ff_bits.size());
581 log_debug("boxNum = %d\n", GetSize(box_list));
582 write_h_buffer(box_list.size());
583
584 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
585 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
586 };
587 std::stringstream i_buffer;
588 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
589 for (auto bit : input_bits)
590 write_i_buffer(arrival_times.at(bit, 0));
591 //std::stringstream o_buffer;
592 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
593 //for (auto bit : output_bits)
594 // write_o_buffer(0);
595
596 if (!box_list.empty() || !ff_bits.empty()) {
597 dict<IdString, std::tuple<int,int,int>> cell_cache;
598
599 int box_count = 0;
600 for (auto cell : box_list) {
601 log_assert(cell);
602
603 RTLIL::Module* box_module = module->design->module(cell->type);
604 log_assert(box_module);
605
606 IdString derived_type = box_module->derive(box_module->design, cell->parameters);
607 box_module = box_module->design->module(derived_type);
608 log_assert(box_module);
609
610 auto r = cell_cache.insert(derived_type);
611 auto &v = r.first->second;
612 if (r.second) {
613 int box_inputs = 0, box_outputs = 0;
614 for (auto port_name : box_module->ports) {
615 RTLIL::Wire *w = box_module->wire(port_name);
616 log_assert(w);
617 if (w->port_input)
618 box_inputs += GetSize(w);
619 if (w->port_output)
620 box_outputs += GetSize(w);
621 }
622
623 // For flops only, create an extra 1-bit input that drives a new wire
624 // called "<cell>.abc9_ff.Q" that is used below
625 if (box_module->get_bool_attribute("\\abc9_flop"))
626 box_inputs++;
627
628 std::get<0>(v) = box_inputs;
629 std::get<1>(v) = box_outputs;
630 std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
631 }
632
633 write_h_buffer(std::get<0>(v));
634 write_h_buffer(std::get<1>(v));
635 write_h_buffer(std::get<2>(v));
636 write_h_buffer(box_count++);
637 }
638
639 std::stringstream r_buffer;
640 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
641 log_debug("flopNum = %d\n", GetSize(ff_bits));
642 write_r_buffer(ff_bits.size());
643
644 std::stringstream s_buffer;
645 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
646 write_s_buffer(ff_bits.size());
647
648 for (const auto &i : ff_bits) {
649 const SigBit &d = i.first;
650 const Cell *cell = i.second;
651
652 int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
653 log_assert(mergeability > 0);
654 write_r_buffer(mergeability);
655
656 Const init = cell->attributes.at(ID(abc9_init), State::Sx);
657 log_assert(GetSize(init) == 1);
658 if (init == State::S1)
659 write_s_buffer(1);
660 else if (init == State::S0)
661 write_s_buffer(0);
662 else {
663 log_assert(init == State::Sx);
664 write_s_buffer(0);
665 }
666
667 write_i_buffer(arrival_times.at(d, 0));
668 //write_o_buffer(0);
669 }
670
671 f << "r";
672 std::string buffer_str = r_buffer.str();
673 int32_t buffer_size_be = to_big_endian(buffer_str.size());
674 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
675 f.write(buffer_str.data(), buffer_str.size());
676
677 f << "s";
678 buffer_str = s_buffer.str();
679 buffer_size_be = to_big_endian(buffer_str.size());
680 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
681 f.write(buffer_str.data(), buffer_str.size());
682
683 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
684 if (holes_module) {
685 std::stringstream a_buffer;
686 XAigerWriter writer(holes_module, true /* holes_mode */);
687 writer.write_aiger(a_buffer, false /*ascii_mode*/);
688
689 f << "a";
690 std::string buffer_str = a_buffer.str();
691 int32_t buffer_size_be = to_big_endian(buffer_str.size());
692 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
693 f.write(buffer_str.data(), buffer_str.size());
694 }
695 }
696
697 f << "h";
698 std::string buffer_str = h_buffer.str();
699 int32_t buffer_size_be = to_big_endian(buffer_str.size());
700 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
701 f.write(buffer_str.data(), buffer_str.size());
702
703 f << "i";
704 buffer_str = i_buffer.str();
705 buffer_size_be = to_big_endian(buffer_str.size());
706 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
707 f.write(buffer_str.data(), buffer_str.size());
708 //f << "o";
709 //buffer_str = o_buffer.str();
710 //buffer_size_be = to_big_endian(buffer_str.size());
711 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
712 //f.write(buffer_str.data(), buffer_str.size());
713
714 f << stringf("Generated by %s\n", yosys_version_str);
715
716 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
717 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
718 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
719 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
720 }
721
722 void write_map(std::ostream &f)
723 {
724 dict<int, string> input_lines;
725 dict<int, string> output_lines;
726
727 for (auto wire : module->wires())
728 {
729 SigSpec sig = sigmap(wire);
730
731 for (int i = 0; i < GetSize(wire); i++)
732 {
733 RTLIL::SigBit b(wire, i);
734 if (input_bits.count(b)) {
735 int a = aig_map.at(b);
736 log_assert((a & 1) == 0);
737 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
738 }
739
740 if (output_bits.count(b)) {
741 int o = ordered_outputs.at(b);
742 int init = 2;
743 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
744 continue;
745 }
746 }
747 }
748
749 input_lines.sort();
750 for (auto &it : input_lines)
751 f << it.second;
752 log_assert(input_lines.size() == input_bits.size());
753
754 int box_count = 0;
755 for (auto cell : box_list)
756 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
757
758 output_lines.sort();
759 for (auto &it : output_lines)
760 f << it.second;
761 log_assert(output_lines.size() == output_bits.size());
762 }
763 };
764
765 struct XAigerBackend : public Backend {
766 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
767 void help() YS_OVERRIDE
768 {
769 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
770 log("\n");
771 log(" write_xaiger [options] [filename]\n");
772 log("\n");
773 log("Write the top module (according to the (* top *) attribute or if only one module\n");
774 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
775 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
776 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
777 log("module, if it exists.\n");
778 log("\n");
779 log(" -ascii\n");
780 log(" write ASCII version of AIGER format\n");
781 log("\n");
782 log(" -map <filename>\n");
783 log(" write an extra file with port and box symbols\n");
784 log("\n");
785 }
786 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
787 {
788 bool ascii_mode = false;
789 std::string map_filename;
790
791 log_header(design, "Executing XAIGER backend.\n");
792
793 size_t argidx;
794 for (argidx = 1; argidx < args.size(); argidx++)
795 {
796 if (args[argidx] == "-ascii") {
797 ascii_mode = true;
798 continue;
799 }
800 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
801 map_filename = args[++argidx];
802 continue;
803 }
804 break;
805 }
806 extra_args(f, filename, args, argidx, !ascii_mode);
807
808 Module *top_module = design->top_module();
809
810 if (top_module == nullptr)
811 log_error("Can't find top module in current design!\n");
812
813 if (!design->selected_whole_module(top_module))
814 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
815
816 if (!top_module->processes.empty())
817 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
818 if (!top_module->memories.empty())
819 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
820
821 XAigerWriter writer(top_module);
822 writer.write_aiger(*f, ascii_mode);
823
824 if (!map_filename.empty()) {
825 std::ofstream mapf;
826 mapf.open(map_filename.c_str(), std::ofstream::trunc);
827 if (mapf.fail())
828 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
829 writer.write_map(mapf);
830 }
831 }
832 } XAigerBackend;
833
834 PRIVATE_NAMESPACE_END