projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge pull request #1716 from zeldin/ecp5_fix
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
51
52 USING_YOSYS_NAMESPACE
53 PRIVATE_NAMESPACE_BEGIN
54
55 inline int32_t to_big_endian(int32_t i32) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 return bswap32(i32);
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
59 return i32;
60 #else
61 #error "Unknown endianness"
62 #endif
63 }
64
65 void aiger_encode(std::ostream &f, int x)
66 {
67 log_assert(x >= 0);
68
69 while (x & ~0x7f) {
70 f.put((x & 0x7f) | 0x80);
71 x = x >> 7;
72 }
73
74 f.put(x);
75 }
76
77 struct XAigerWriter
78 {
79 Module *module;
80 SigMap sigmap;
81
82 pool<SigBit> input_bits, output_bits;
83 dict<SigBit, SigBit> not_map, alias_map;
84 dict<SigBit, pair<SigBit, SigBit>> and_map;
85 vector<SigBit> ci_bits, co_bits;
86 dict<SigBit, Cell*> ff_bits;
87 dict<SigBit, float> arrival_times;
88
89 vector<pair<int, int>> aig_gates;
90 vector<int> aig_outputs;
91 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
92
93 dict<SigBit, int> aig_map;
94 dict<SigBit, int> ordered_outputs;
95
96 vector<Cell*> box_list;
97
98 int mkgate(int a0, int a1)
99 {
100 aig_m++, aig_a++;
101 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
102 return 2*aig_m;
103 }
104
105 int bit2aig(SigBit bit)
106 {
107 auto it = aig_map.find(bit);
108 if (it != aig_map.end()) {
109 log_assert(it->second >= 0);
110 return it->second;
111 }
112
113 // NB: Cannot use iterator returned from aig_map.insert()
114 // since this function is called recursively
115
116 int a = -1;
117 if (not_map.count(bit)) {
118 a = bit2aig(not_map.at(bit)) ^ 1;
119 } else
120 if (and_map.count(bit)) {
121 auto args = and_map.at(bit);
122 int a0 = bit2aig(args.first);
123 int a1 = bit2aig(args.second);
124 a = mkgate(a0, a1);
125 } else
126 if (alias_map.count(bit)) {
127 a = bit2aig(alias_map.at(bit));
128 }
129
130 if (bit == State::Sx || bit == State::Sz) {
131 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
132 a = aig_map.at(State::S0);
133 }
134
135 log_assert(a >= 0);
136 aig_map[bit] = a;
137 return a;
138 }
139
140 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
141 {
142 pool<SigBit> undriven_bits;
143 pool<SigBit> unused_bits;
144
145 // promote public wires
146 for (auto wire : module->wires())
147 if (wire->name[0] == '\\')
148 sigmap.add(wire);
149
150 // promote input wires
151 for (auto wire : module->wires())
152 if (wire->port_input)
153 sigmap.add(wire);
154
155 // promote keep wires
156 for (auto wire : module->wires())
157 if (wire->get_bool_attribute(ID::keep))
158 sigmap.add(wire);
159
160 for (auto wire : module->wires())
161 for (int i = 0; i < GetSize(wire); i++)
162 {
163 SigBit wirebit(wire, i);
164 SigBit bit = sigmap(wirebit);
165
166 if (bit.wire == nullptr) {
167 if (wire->port_output) {
168 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
169 output_bits.insert(wirebit);
170 }
171 continue;
172 }
173
174 undriven_bits.insert(bit);
175 unused_bits.insert(bit);
176
177 bool keep = wire->get_bool_attribute(ID::keep);
178 if (wire->port_input || keep)
179 input_bits.insert(bit);
180
181 if (wire->port_output || keep) {
182 if (bit != wirebit)
183 alias_map[wirebit] = bit;
184 output_bits.insert(wirebit);
185 }
186 }
187
188 TimingInfo timing;
189
190 for (auto cell : module->cells()) {
191 if (!cell->has_keep_attr()) {
192 if (cell->type == "$_NOT_")
193 {
194 SigBit A = sigmap(cell->getPort("\\A").as_bit());
195 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
196 unused_bits.erase(A);
197 undriven_bits.erase(Y);
198 not_map[Y] = A;
199 continue;
200 }
201
202 if (cell->type == "$_AND_")
203 {
204 SigBit A = sigmap(cell->getPort("\\A").as_bit());
205 SigBit B = sigmap(cell->getPort("\\B").as_bit());
206 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
207 unused_bits.erase(A);
208 unused_bits.erase(B);
209 undriven_bits.erase(Y);
210 and_map[Y] = make_pair(A, B);
211 continue;
212 }
213
214 if (cell->type == "$__ABC9_FF_" &&
215 // The presence of an abc9_mergeability attribute indicates
216 // that we do want to pass this flop to ABC
217 cell->attributes.count("\\abc9_mergeability"))
218 {
219 SigBit D = sigmap(cell->getPort("\\D").as_bit());
220 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
221 unused_bits.erase(D);
222 undriven_bits.erase(Q);
223 alias_map[Q] = D;
224 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
225 log_assert(r.second);
226 if (input_bits.erase(Q))
227 log_assert(Q.wire->attributes.count(ID::keep));
228 continue;
229 }
230
231 if (cell->type.in("$specify2", "$specify3", "$specrule"))
232 continue;
233 }
234
235 RTLIL::Module* inst_module = module->design->module(cell->type);
236 if (inst_module) {
237 IdString derived_type = inst_module->derive(module->design, cell->parameters);
238 inst_module = module->design->module(derived_type);
239 log_assert(inst_module);
240
241 bool abc9_flop = false;
242 if (!cell->has_keep_attr()) {
243 auto it = cell->attributes.find("\\abc9_box_seq");
244 if (it != cell->attributes.end()) {
245 int abc9_box_seq = it->second.as_int();
246 if (GetSize(box_list) <= abc9_box_seq)
247 box_list.resize(abc9_box_seq+1);
248 box_list[abc9_box_seq] = cell;
249 // Only flop boxes may have arrival times
250 // (all others are combinatorial)
251 abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
252 if (!abc9_flop)
253 continue;
254 }
255 }
256
257 if (!timing.count(derived_type))
258 timing.setup_module(inst_module);
259 auto &t = timing.at(derived_type).arrival;
260 for (const auto &conn : cell->connections()) {
261 auto port_wire = inst_module->wire(conn.first);
262 if (!port_wire->port_output)
263 continue;
264
265 for (int i = 0; i < GetSize(conn.second); i++) {
266 auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
267 if (d == 0)
268 continue;
269
270 #ifndef NDEBUG
271 if (ys_debug(1)) {
272 static std::set<std::tuple<IdString,IdString,int>> seen;
273 if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
274 log_id(cell->type), log_id(conn.first), i, d);
275 }
276 #endif
277 arrival_times[conn.second[i]] = d;
278 }
279 }
280
281 if (abc9_flop)
282 continue;
283 }
284
285 bool cell_known = inst_module || cell->known();
286 for (const auto &c : cell->connections()) {
287 if (c.second.is_fully_const()) continue;
288 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
289 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
290 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
291 if (!is_input && !is_output)
292 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
293
294 if (is_input)
295 for (auto b : c.second) {
296 Wire *w = b.wire;
297 if (!w) continue;
298 // Do not add as PO if bit is already a PI
299 if (input_bits.count(b))
300 continue;
301 if (!w->port_output || !cell_known) {
302 SigBit I = sigmap(b);
303 if (I != b)
304 alias_map[b] = I;
305 output_bits.insert(b);
306 }
307 }
308 }
309
310 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
311 }
312
313 dict<IdString, std::vector<IdString>> box_ports;
314 for (auto cell : box_list) {
315 log_assert(cell);
316
317 RTLIL::Module* box_module = module->design->module(cell->type);
318 log_assert(box_module);
319 log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
320
321 auto r = box_ports.insert(cell->type);
322 if (r.second) {
323 // Make carry in the last PI, and carry out the last PO
324 // since ABC requires it this way
325 IdString carry_in, carry_out;
326 for (const auto &port_name : box_module->ports) {
327 auto w = box_module->wire(port_name);
328 log_assert(w);
329 if (w->get_bool_attribute("\\abc9_carry")) {
330 if (w->port_input) {
331 if (carry_in != IdString())
332 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
333 carry_in = port_name;
334 }
335 if (w->port_output) {
336 if (carry_out != IdString())
337 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
338 carry_out = port_name;
339 }
340 }
341 else
342 r.first->second.push_back(port_name);
343 }
344
345 if (carry_in != IdString() && carry_out == IdString())
346 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
347 if (carry_in == IdString() && carry_out != IdString())
348 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
349 if (carry_in != IdString()) {
350 r.first->second.push_back(carry_in);
351 r.first->second.push_back(carry_out);
352 }
353 }
354
355 for (auto port_name : r.first->second) {
356 auto w = box_module->wire(port_name);
357 log_assert(w);
358 auto rhs = cell->connections_.at(port_name, SigSpec());
359 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
360 if (w->port_input)
361 for (auto b : rhs) {
362 SigBit I = sigmap(b);
363 if (b == RTLIL::Sx)
364 b = State::S0;
365 else if (I != b) {
366 if (I == RTLIL::Sx)
367 alias_map[b] = State::S0;
368 else
369 alias_map[b] = I;
370 }
371 co_bits.emplace_back(b);
372 unused_bits.erase(I);
373 }
374 if (w->port_output)
375 for (const auto &b : rhs) {
376 SigBit O = sigmap(b);
377 if (O != b)
378 alias_map[O] = b;
379 ci_bits.emplace_back(b);
380 undriven_bits.erase(O);
381 // If PI and CI, then must be a (* keep *) wire
382 if (input_bits.erase(O)) {
383 log_assert(output_bits.count(O));
384 log_assert(O.wire->get_bool_attribute(ID::keep));
385 }
386 }
387 }
388
389 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
390 if (box_module->get_bool_attribute("\\abc9_flop")) {
391 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
392 if (rhs.empty())
393 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
394
395 for (auto b : rhs) {
396 SigBit I = sigmap(b);
397 if (b == RTLIL::Sx)
398 b = State::S0;
399 else if (I != b) {
400 if (I == RTLIL::Sx)
401 alias_map[b] = State::S0;
402 else
403 alias_map[b] = I;
404 }
405 co_bits.emplace_back(b);
406 unused_bits.erase(I);
407 }
408 }
409 }
410
411 for (auto bit : input_bits)
412 undriven_bits.erase(bit);
413 for (auto bit : output_bits)
414 unused_bits.erase(sigmap(bit));
415 for (auto bit : unused_bits)
416 undriven_bits.erase(bit);
417
418 // Make all undriven bits a primary input
419 for (auto bit : undriven_bits) {
420 input_bits.insert(bit);
421 undriven_bits.erase(bit);
422 }
423
424 if (holes_mode) {
425 struct sort_by_port_id {
426 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
427 return a.wire->port_id < b.wire->port_id ||
428 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
429 }
430 };
431 input_bits.sort(sort_by_port_id());
432 output_bits.sort(sort_by_port_id());
433 }
434
435 aig_map[State::S0] = 0;
436 aig_map[State::S1] = 1;
437
438 for (const auto &bit : input_bits) {
439 aig_m++, aig_i++;
440 log_assert(!aig_map.count(bit));
441 aig_map[bit] = 2*aig_m;
442 }
443
444 for (const auto &i : ff_bits) {
445 const Cell *cell = i.second;
446 const SigBit &q = sigmap(cell->getPort("\\Q"));
447 aig_m++, aig_i++;
448 log_assert(!aig_map.count(q));
449 aig_map[q] = 2*aig_m;
450 }
451
452 for (auto &bit : ci_bits) {
453 aig_m++, aig_i++;
454 // 1'bx may exist here due to a box output
455 // that has been padded to its full width
456 if (bit == State::Sx)
457 continue;
458 log_assert(!aig_map.count(bit));
459 aig_map[bit] = 2*aig_m;
460 }
461
462 for (auto bit : co_bits) {
463 ordered_outputs[bit] = aig_o++;
464 aig_outputs.push_back(bit2aig(bit));
465 }
466
467 for (const auto &bit : output_bits) {
468 ordered_outputs[bit] = aig_o++;
469 int aig;
470 // Unlike bit2aig() which checks aig_map first, for
471 // inout/keep bits, since aig_map will point to
472 // the PI, first attempt to find the NOT/AND driver
473 // before resorting to an aig_map lookup (which
474 // could be another PO)
475 if (input_bits.count(bit)) {
476 if (not_map.count(bit)) {
477 aig = bit2aig(not_map.at(bit)) ^ 1;
478 } else if (and_map.count(bit)) {
479 auto args = and_map.at(bit);
480 int a0 = bit2aig(args.first);
481 int a1 = bit2aig(args.second);
482 aig = mkgate(a0, a1);
483 }
484 else
485 aig = aig_map.at(bit);
486 }
487 else
488 aig = bit2aig(bit);
489 aig_outputs.push_back(aig);
490 }
491
492 for (auto &i : ff_bits) {
493 const SigBit &d = i.first;
494 aig_o++;
495 aig_outputs.push_back(aig_map.at(d));
496 }
497 }
498
499 void write_aiger(std::ostream &f, bool ascii_mode)
500 {
501 int aig_obc = aig_o;
502 int aig_obcj = aig_obc;
503 int aig_obcjf = aig_obcj;
504
505 log_assert(aig_m == aig_i + aig_l + aig_a);
506 log_assert(aig_obcjf == GetSize(aig_outputs));
507
508 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
509 f << stringf("\n");
510
511 if (ascii_mode)
512 {
513 for (int i = 0; i < aig_i; i++)
514 f << stringf("%d\n", 2*i+2);
515
516 for (int i = 0; i < aig_obc; i++)
517 f << stringf("%d\n", aig_outputs.at(i));
518
519 for (int i = aig_obc; i < aig_obcj; i++)
520 f << stringf("1\n");
521
522 for (int i = aig_obc; i < aig_obcj; i++)
523 f << stringf("%d\n", aig_outputs.at(i));
524
525 for (int i = aig_obcj; i < aig_obcjf; i++)
526 f << stringf("%d\n", aig_outputs.at(i));
527
528 for (int i = 0; i < aig_a; i++)
529 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
530 }
531 else
532 {
533 for (int i = 0; i < aig_obc; i++)
534 f << stringf("%d\n", aig_outputs.at(i));
535
536 for (int i = aig_obc; i < aig_obcj; i++)
537 f << stringf("1\n");
538
539 for (int i = aig_obc; i < aig_obcj; i++)
540 f << stringf("%d\n", aig_outputs.at(i));
541
542 for (int i = aig_obcj; i < aig_obcjf; i++)
543 f << stringf("%d\n", aig_outputs.at(i));
544
545 for (int i = 0; i < aig_a; i++) {
546 int lhs = 2*(aig_i+aig_l+i)+2;
547 int rhs0 = aig_gates.at(i).first;
548 int rhs1 = aig_gates.at(i).second;
549 int delta0 = lhs - rhs0;
550 int delta1 = rhs0 - rhs1;
551 aiger_encode(f, delta0);
552 aiger_encode(f, delta1);
553 }
554 }
555
556 f << "c";
557
558 auto write_buffer = [](std::stringstream &buffer, int i32) {
559 int32_t i32_be = to_big_endian(i32);
560 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
561 };
562 std::stringstream h_buffer;
563 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
564 write_h_buffer(1);
565 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
566 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
567 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
568 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
569 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
570 write_h_buffer(input_bits.size() + ff_bits.size());
571 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
572 write_h_buffer(output_bits.size() + ff_bits.size());
573 log_debug("boxNum = %d\n", GetSize(box_list));
574 write_h_buffer(box_list.size());
575
576 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
577 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
578 };
579 std::stringstream i_buffer;
580 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
581 for (auto bit : input_bits)
582 write_i_buffer(arrival_times.at(bit, 0));
583 //std::stringstream o_buffer;
584 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
585 //for (auto bit : output_bits)
586 // write_o_buffer(0);
587
588 if (!box_list.empty() || !ff_bits.empty()) {
589 dict<IdString, std::tuple<int,int,int>> cell_cache;
590
591 int box_count = 0;
592 for (auto cell : box_list) {
593 log_assert(cell);
594
595 RTLIL::Module* box_module = module->design->module(cell->type);
596 log_assert(box_module);
597
598 IdString derived_type = box_module->derive(box_module->design, cell->parameters);
599 box_module = box_module->design->module(derived_type);
600 log_assert(box_module);
601
602 auto r = cell_cache.insert(derived_type);
603 auto &v = r.first->second;
604 if (r.second) {
605 int box_inputs = 0, box_outputs = 0;
606 for (auto port_name : box_module->ports) {
607 RTLIL::Wire *w = box_module->wire(port_name);
608 log_assert(w);
609 if (w->port_input)
610 box_inputs += GetSize(w);
611 if (w->port_output)
612 box_outputs += GetSize(w);
613 }
614
615 // For flops only, create an extra 1-bit input that drives a new wire
616 // called "<cell>.abc9_ff.Q" that is used below
617 if (box_module->get_bool_attribute("\\abc9_flop"))
618 box_inputs++;
619
620 std::get<0>(v) = box_inputs;
621 std::get<1>(v) = box_outputs;
622 std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
623 }
624
625 write_h_buffer(std::get<0>(v));
626 write_h_buffer(std::get<1>(v));
627 write_h_buffer(std::get<2>(v));
628 write_h_buffer(box_count++);
629 }
630
631 std::stringstream r_buffer;
632 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
633 log_debug("flopNum = %d\n", GetSize(ff_bits));
634 write_r_buffer(ff_bits.size());
635
636 std::stringstream s_buffer;
637 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
638 write_s_buffer(ff_bits.size());
639
640 for (const auto &i : ff_bits) {
641 const SigBit &d = i.first;
642 const Cell *cell = i.second;
643
644 int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
645 log_assert(mergeability > 0);
646 write_r_buffer(mergeability);
647
648 Const init = cell->attributes.at(ID(abc9_init), State::Sx);
649 log_assert(GetSize(init) == 1);
650 if (init == State::S1)
651 write_s_buffer(1);
652 else if (init == State::S0)
653 write_s_buffer(0);
654 else {
655 log_assert(init == State::Sx);
656 write_s_buffer(0);
657 }
658
659 // Use arrival time from output of flop box
660 write_i_buffer(arrival_times.at(d, 0));
661 //write_o_buffer(0);
662 }
663
664 f << "r";
665 std::string buffer_str = r_buffer.str();
666 int32_t buffer_size_be = to_big_endian(buffer_str.size());
667 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
668 f.write(buffer_str.data(), buffer_str.size());
669
670 f << "s";
671 buffer_str = s_buffer.str();
672 buffer_size_be = to_big_endian(buffer_str.size());
673 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
674 f.write(buffer_str.data(), buffer_str.size());
675
676 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
677 if (holes_module) {
678 std::stringstream a_buffer;
679 XAigerWriter writer(holes_module, true /* holes_mode */);
680 writer.write_aiger(a_buffer, false /*ascii_mode*/);
681
682 f << "a";
683 std::string buffer_str = a_buffer.str();
684 int32_t buffer_size_be = to_big_endian(buffer_str.size());
685 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
686 f.write(buffer_str.data(), buffer_str.size());
687 }
688 }
689
690 f << "h";
691 std::string buffer_str = h_buffer.str();
692 int32_t buffer_size_be = to_big_endian(buffer_str.size());
693 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
694 f.write(buffer_str.data(), buffer_str.size());
695
696 f << "i";
697 buffer_str = i_buffer.str();
698 buffer_size_be = to_big_endian(buffer_str.size());
699 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
700 f.write(buffer_str.data(), buffer_str.size());
701 //f << "o";
702 //buffer_str = o_buffer.str();
703 //buffer_size_be = to_big_endian(buffer_str.size());
704 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
705 //f.write(buffer_str.data(), buffer_str.size());
706
707 f << stringf("Generated by %s\n", yosys_version_str);
708
709 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
710 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
711 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
712 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
713 }
714
715 void write_map(std::ostream &f)
716 {
717 dict<int, string> input_lines;
718 dict<int, string> output_lines;
719
720 for (auto wire : module->wires())
721 {
722 SigSpec sig = sigmap(wire);
723
724 for (int i = 0; i < GetSize(wire); i++)
725 {
726 RTLIL::SigBit b(wire, i);
727 if (input_bits.count(b)) {
728 int a = aig_map.at(b);
729 log_assert((a & 1) == 0);
730 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
731 }
732
733 if (output_bits.count(b)) {
734 int o = ordered_outputs.at(b);
735 int init = 2;
736 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
737 continue;
738 }
739 }
740 }
741
742 input_lines.sort();
743 for (auto &it : input_lines)
744 f << it.second;
745 log_assert(input_lines.size() == input_bits.size());
746
747 int box_count = 0;
748 for (auto cell : box_list)
749 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
750
751 output_lines.sort();
752 for (auto &it : output_lines)
753 f << it.second;
754 log_assert(output_lines.size() == output_bits.size());
755 }
756 };
757
758 struct XAigerBackend : public Backend {
759 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
760 void help() YS_OVERRIDE
761 {
762 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
763 log("\n");
764 log(" write_xaiger [options] [filename]\n");
765 log("\n");
766 log("Write the top module (according to the (* top *) attribute or if only one module\n");
767 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
768 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
769 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
770 log("module, if it exists.\n");
771 log("\n");
772 log(" -ascii\n");
773 log(" write ASCII version of AIGER format\n");
774 log("\n");
775 log(" -map <filename>\n");
776 log(" write an extra file with port and box symbols\n");
777 log("\n");
778 }
779 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
780 {
781 bool ascii_mode = false;
782 std::string map_filename;
783
784 log_header(design, "Executing XAIGER backend.\n");
785
786 size_t argidx;
787 for (argidx = 1; argidx < args.size(); argidx++)
788 {
789 if (args[argidx] == "-ascii") {
790 ascii_mode = true;
791 continue;
792 }
793 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
794 map_filename = args[++argidx];
795 continue;
796 }
797 break;
798 }
799 extra_args(f, filename, args, argidx, !ascii_mode);
800
801 Module *top_module = design->top_module();
802
803 if (top_module == nullptr)
804 log_error("Can't find top module in current design!\n");
805
806 if (!design->selected_whole_module(top_module))
807 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
808
809 if (!top_module->processes.empty())
810 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
811 if (!top_module->memories.empty())
812 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
813
814 XAigerWriter writer(top_module);
815 writer.write_aiger(*f, ascii_mode);
816
817 if (!map_filename.empty()) {
818 std::ofstream mapf;
819 mapf.open(map_filename.c_str(), std::ofstream::trunc);
820 if (mapf.fail())
821 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
822 writer.write_map(mapf);
823 }
824 }
825 } XAigerBackend;
826
827 PRIVATE_NAMESPACE_END