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Merge pull request #2063 from boqwxp/techmapped-firrtl
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
51
52 USING_YOSYS_NAMESPACE
53 PRIVATE_NAMESPACE_BEGIN
54
55 inline int32_t to_big_endian(int32_t i32) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 return bswap32(i32);
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
59 return i32;
60 #else
61 #error "Unknown endianness"
62 #endif
63 }
64
65 void aiger_encode(std::ostream &f, int x)
66 {
67 log_assert(x >= 0);
68
69 while (x & ~0x7f) {
70 f.put((x & 0x7f) | 0x80);
71 x = x >> 7;
72 }
73
74 f.put(x);
75 }
76
77 struct XAigerWriter
78 {
79 Design *design;
80 Module *module;
81 SigMap sigmap;
82
83 dict<SigBit, State> init_map;
84 pool<SigBit> input_bits, output_bits;
85 dict<SigBit, SigBit> not_map, alias_map;
86 dict<SigBit, pair<SigBit, SigBit>> and_map;
87 vector<SigBit> ci_bits, co_bits;
88 dict<SigBit, Cell*> ff_bits;
89 dict<SigBit, float> arrival_times;
90
91 vector<pair<int, int>> aig_gates;
92 vector<int> aig_outputs;
93 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
94
95 dict<SigBit, int> aig_map;
96 dict<SigBit, int> ordered_outputs;
97
98 vector<Cell*> box_list;
99
100 int mkgate(int a0, int a1)
101 {
102 aig_m++, aig_a++;
103 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
104 return 2*aig_m;
105 }
106
107 int bit2aig(SigBit bit)
108 {
109 auto it = aig_map.find(bit);
110 if (it != aig_map.end()) {
111 log_assert(it->second >= 0);
112 return it->second;
113 }
114
115 // NB: Cannot use iterator returned from aig_map.insert()
116 // since this function is called recursively
117
118 int a = -1;
119 if (not_map.count(bit)) {
120 a = bit2aig(not_map.at(bit)) ^ 1;
121 } else
122 if (and_map.count(bit)) {
123 auto args = and_map.at(bit);
124 int a0 = bit2aig(args.first);
125 int a1 = bit2aig(args.second);
126 a = mkgate(a0, a1);
127 } else
128 if (alias_map.count(bit)) {
129 a = bit2aig(alias_map.at(bit));
130 }
131
132 if (bit == State::Sx || bit == State::Sz) {
133 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
134 a = aig_map.at(State::S0);
135 }
136
137 log_assert(a >= 0);
138 aig_map[bit] = a;
139 return a;
140 }
141
142 XAigerWriter(Module *module, bool dff_mode) : design(module->design), module(module), sigmap(module)
143 {
144 pool<SigBit> undriven_bits;
145 pool<SigBit> unused_bits;
146
147 // promote public wires
148 for (auto wire : module->wires())
149 if (wire->name[0] == '\\')
150 sigmap.add(wire);
151
152 // promote input wires
153 for (auto wire : module->wires())
154 if (wire->port_input)
155 sigmap.add(wire);
156
157 // promote keep wires
158 for (auto wire : module->wires())
159 if (wire->get_bool_attribute(ID::keep))
160 sigmap.add(wire);
161
162 for (auto wire : module->wires()) {
163 auto it = wire->attributes.find(ID::init);
164 for (int i = 0; i < GetSize(wire); i++)
165 {
166 SigBit wirebit(wire, i);
167 SigBit bit = sigmap(wirebit);
168
169 if (bit.wire == nullptr) {
170 if (wire->port_output) {
171 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
172 output_bits.insert(wirebit);
173 }
174 continue;
175 }
176
177 undriven_bits.insert(bit);
178 unused_bits.insert(bit);
179
180 bool keep = wire->get_bool_attribute(ID::abc9_keep);
181 if (wire->port_input || keep)
182 input_bits.insert(bit);
183
184 keep = keep || wire->get_bool_attribute(ID::keep);
185 if (wire->port_output || keep) {
186 if (bit != wirebit)
187 alias_map[wirebit] = bit;
188 output_bits.insert(wirebit);
189 }
190
191 if (it != wire->attributes.end()) {
192 auto s = it->second[i];
193 if (s != State::Sx) {
194 auto r = init_map.insert(std::make_pair(bit, it->second[i]));
195 if (!r.second && r.first->second != it->second[i])
196 log_error("Bit '%s' has a conflicting (* init *) value.\n", log_signal(bit));
197 }
198 }
199 }
200 }
201
202 TimingInfo timing;
203
204 for (auto cell : module->cells()) {
205 if (!cell->has_keep_attr()) {
206 if (cell->type == ID($_NOT_))
207 {
208 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
209 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
210 unused_bits.erase(A);
211 undriven_bits.erase(Y);
212 not_map[Y] = A;
213 continue;
214 }
215
216 if (cell->type == ID($_AND_))
217 {
218 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
219 SigBit B = sigmap(cell->getPort(ID::B).as_bit());
220 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
221 unused_bits.erase(A);
222 unused_bits.erase(B);
223 undriven_bits.erase(Y);
224 and_map[Y] = make_pair(A, B);
225 continue;
226 }
227
228 if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
229 {
230 SigBit D = sigmap(cell->getPort(ID::D).as_bit());
231 SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
232 unused_bits.erase(D);
233 undriven_bits.erase(Q);
234 alias_map[Q] = D;
235 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
236 log_assert(r.second);
237 continue;
238 }
239
240 if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
241 continue;
242 }
243
244 RTLIL::Module* inst_module = design->module(cell->type);
245 if (inst_module && inst_module->get_blackbox_attribute()) {
246 bool abc9_flop = false;
247
248 auto it = cell->attributes.find(ID::abc9_box_seq);
249 if (it != cell->attributes.end()) {
250 log_assert(!cell->has_keep_attr());
251 log_assert(cell->parameters.empty());
252 int abc9_box_seq = it->second.as_int();
253 if (GetSize(box_list) <= abc9_box_seq)
254 box_list.resize(abc9_box_seq+1);
255 box_list[abc9_box_seq] = cell;
256 // Only flop boxes may have arrival times
257 // (all others are combinatorial)
258 log_assert(cell->parameters.empty());
259 abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
260 if (!abc9_flop)
261 continue;
262 }
263
264 if (!timing.count(inst_module->name))
265 timing.setup_module(inst_module);
266 auto &t = timing.at(inst_module->name).arrival;
267 for (const auto &conn : cell->connections()) {
268 auto port_wire = inst_module->wire(conn.first);
269 if (!port_wire->port_output)
270 continue;
271
272 for (int i = 0; i < GetSize(conn.second); i++) {
273 auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
274 if (d == 0)
275 continue;
276
277 #ifndef NDEBUG
278 if (ys_debug(1)) {
279 static std::set<std::tuple<IdString,IdString,int>> seen;
280 if (seen.emplace(inst_module->name, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
281 log_id(cell->type), log_id(conn.first), i, d);
282 }
283 #endif
284 arrival_times[conn.second[i]] = d;
285 }
286 }
287
288 if (abc9_flop)
289 continue;
290 }
291
292 bool cell_known = inst_module || cell->known();
293 for (const auto &c : cell->connections()) {
294 if (c.second.is_fully_const()) continue;
295 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
296 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
297 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
298 if (!is_input && !is_output)
299 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
300
301 if (is_input)
302 for (auto b : c.second) {
303 Wire *w = b.wire;
304 if (!w) continue;
305 // Do not add as PO if bit is already a PI
306 if (input_bits.count(b))
307 continue;
308 if (!w->port_output || !cell_known) {
309 SigBit I = sigmap(b);
310 if (I != b)
311 alias_map[b] = I;
312 output_bits.insert(b);
313 }
314 }
315 }
316
317 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
318 }
319
320 dict<IdString, std::vector<IdString>> box_ports;
321 for (auto cell : box_list) {
322 log_assert(cell);
323
324 RTLIL::Module* box_module = design->module(cell->type);
325 log_assert(box_module);
326 log_assert(box_module->has_attribute(ID::abc9_box_id));
327
328 auto r = box_ports.insert(cell->type);
329 if (r.second) {
330 // Make carry in the last PI, and carry out the last PO
331 // since ABC requires it this way
332 IdString carry_in, carry_out;
333 for (const auto &port_name : box_module->ports) {
334 auto w = box_module->wire(port_name);
335 log_assert(w);
336 if (w->get_bool_attribute(ID::abc9_carry)) {
337 if (w->port_input) {
338 if (carry_in != IdString())
339 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
340 carry_in = port_name;
341 }
342 if (w->port_output) {
343 if (carry_out != IdString())
344 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
345 carry_out = port_name;
346 }
347 }
348 else
349 r.first->second.push_back(port_name);
350 }
351
352 if (carry_in != IdString() && carry_out == IdString())
353 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
354 if (carry_in == IdString() && carry_out != IdString())
355 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
356 if (carry_in != IdString()) {
357 r.first->second.push_back(carry_in);
358 r.first->second.push_back(carry_out);
359 }
360 }
361
362 for (auto port_name : r.first->second) {
363 auto w = box_module->wire(port_name);
364 log_assert(w);
365 auto rhs = cell->connections_.at(port_name, SigSpec());
366 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
367 if (w->port_input)
368 for (auto b : rhs) {
369 SigBit I = sigmap(b);
370 if (b == RTLIL::Sx)
371 b = State::S0;
372 else if (I != b) {
373 if (I == RTLIL::Sx)
374 alias_map[b] = State::S0;
375 else
376 alias_map[b] = I;
377 }
378 co_bits.emplace_back(b);
379 unused_bits.erase(I);
380 }
381 if (w->port_output)
382 for (const auto &b : rhs) {
383 SigBit O = sigmap(b);
384 if (O != b)
385 alias_map[O] = b;
386 ci_bits.emplace_back(b);
387 undriven_bits.erase(O);
388 }
389 }
390 }
391
392 for (auto bit : input_bits)
393 undriven_bits.erase(bit);
394 for (auto bit : output_bits)
395 unused_bits.erase(sigmap(bit));
396 for (auto bit : unused_bits)
397 undriven_bits.erase(bit);
398
399 // Make all undriven bits a primary input
400 for (auto bit : undriven_bits) {
401 input_bits.insert(bit);
402 undriven_bits.erase(bit);
403 }
404
405 struct sort_by_port_id {
406 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
407 return a.wire->port_id < b.wire->port_id ||
408 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
409 }
410 };
411 input_bits.sort(sort_by_port_id());
412 output_bits.sort(sort_by_port_id());
413
414 aig_map[State::S0] = 0;
415 aig_map[State::S1] = 1;
416
417 for (const auto &bit : input_bits) {
418 aig_m++, aig_i++;
419 log_assert(!aig_map.count(bit));
420 aig_map[bit] = 2*aig_m;
421 }
422
423 for (const auto &i : ff_bits) {
424 const Cell *cell = i.second;
425 const SigBit &q = sigmap(cell->getPort(ID::Q));
426 aig_m++, aig_i++;
427 log_assert(!aig_map.count(q));
428 aig_map[q] = 2*aig_m;
429 }
430
431 for (auto &bit : ci_bits) {
432 aig_m++, aig_i++;
433 // 1'bx may exist here due to a box output
434 // that has been padded to its full width
435 if (bit == State::Sx)
436 continue;
437 log_assert(!aig_map.count(bit));
438 aig_map[bit] = 2*aig_m;
439 }
440
441 for (auto bit : co_bits) {
442 ordered_outputs[bit] = aig_o++;
443 aig_outputs.push_back(bit2aig(bit));
444 }
445
446 for (const auto &bit : output_bits) {
447 ordered_outputs[bit] = aig_o++;
448 int aig;
449 // Unlike bit2aig() which checks aig_map first for
450 // inout/scc bits, since aig_map will point to
451 // the PI, first attempt to find the NOT/AND driver
452 // before resorting to an aig_map lookup (which
453 // could be another PO)
454 if (input_bits.count(bit)) {
455 if (not_map.count(bit)) {
456 aig = bit2aig(not_map.at(bit)) ^ 1;
457 } else if (and_map.count(bit)) {
458 auto args = and_map.at(bit);
459 int a0 = bit2aig(args.first);
460 int a1 = bit2aig(args.second);
461 aig = mkgate(a0, a1);
462 }
463 else
464 aig = aig_map.at(bit);
465 }
466 else
467 aig = bit2aig(bit);
468 aig_outputs.push_back(aig);
469 }
470
471 for (auto &i : ff_bits) {
472 const SigBit &d = i.first;
473 aig_o++;
474 aig_outputs.push_back(aig_map.at(d));
475 }
476 }
477
478 void write_aiger(std::ostream &f, bool ascii_mode)
479 {
480 int aig_obc = aig_o;
481 int aig_obcj = aig_obc;
482 int aig_obcjf = aig_obcj;
483
484 log_assert(aig_m == aig_i + aig_l + aig_a);
485 log_assert(aig_obcjf == GetSize(aig_outputs));
486
487 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
488 f << stringf("\n");
489
490 if (ascii_mode)
491 {
492 for (int i = 0; i < aig_i; i++)
493 f << stringf("%d\n", 2*i+2);
494
495 for (int i = 0; i < aig_obc; i++)
496 f << stringf("%d\n", aig_outputs.at(i));
497
498 for (int i = aig_obc; i < aig_obcj; i++)
499 f << stringf("1\n");
500
501 for (int i = aig_obc; i < aig_obcj; i++)
502 f << stringf("%d\n", aig_outputs.at(i));
503
504 for (int i = aig_obcj; i < aig_obcjf; i++)
505 f << stringf("%d\n", aig_outputs.at(i));
506
507 for (int i = 0; i < aig_a; i++)
508 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
509 }
510 else
511 {
512 for (int i = 0; i < aig_obc; i++)
513 f << stringf("%d\n", aig_outputs.at(i));
514
515 for (int i = aig_obc; i < aig_obcj; i++)
516 f << stringf("1\n");
517
518 for (int i = aig_obc; i < aig_obcj; i++)
519 f << stringf("%d\n", aig_outputs.at(i));
520
521 for (int i = aig_obcj; i < aig_obcjf; i++)
522 f << stringf("%d\n", aig_outputs.at(i));
523
524 for (int i = 0; i < aig_a; i++) {
525 int lhs = 2*(aig_i+aig_l+i)+2;
526 int rhs0 = aig_gates.at(i).first;
527 int rhs1 = aig_gates.at(i).second;
528 int delta0 = lhs - rhs0;
529 int delta1 = rhs0 - rhs1;
530 aiger_encode(f, delta0);
531 aiger_encode(f, delta1);
532 }
533 }
534
535 f << "c";
536
537 auto write_buffer = [](std::stringstream &buffer, int i32) {
538 int32_t i32_be = to_big_endian(i32);
539 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
540 };
541 std::stringstream h_buffer;
542 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
543 write_h_buffer(1);
544 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
545 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
546 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
547 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
548 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
549 write_h_buffer(input_bits.size() + ff_bits.size());
550 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
551 write_h_buffer(output_bits.size() + ff_bits.size());
552 log_debug("boxNum = %d\n", GetSize(box_list));
553 write_h_buffer(box_list.size());
554
555 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
556 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
557 };
558 std::stringstream i_buffer;
559 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
560 for (auto bit : input_bits)
561 write_i_buffer(arrival_times.at(bit, 0));
562 //std::stringstream o_buffer;
563 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
564 //for (auto bit : output_bits)
565 // write_o_buffer(0);
566
567 if (!box_list.empty() || !ff_bits.empty()) {
568 dict<IdString, std::tuple<int,int,int>> cell_cache;
569
570 int box_count = 0;
571 for (auto cell : box_list) {
572 log_assert(cell);
573 log_assert(cell->parameters.empty());
574
575 auto r = cell_cache.insert(cell->type);
576 auto &v = r.first->second;
577 if (r.second) {
578 RTLIL::Module* box_module = design->module(cell->type);
579 log_assert(box_module);
580
581 int box_inputs = 0, box_outputs = 0;
582 for (auto port_name : box_module->ports) {
583 RTLIL::Wire *w = box_module->wire(port_name);
584 log_assert(w);
585 if (w->port_input)
586 box_inputs += GetSize(w);
587 if (w->port_output)
588 box_outputs += GetSize(w);
589 }
590
591 std::get<0>(v) = box_inputs;
592 std::get<1>(v) = box_outputs;
593 std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
594 }
595
596 write_h_buffer(std::get<0>(v));
597 write_h_buffer(std::get<1>(v));
598 write_h_buffer(std::get<2>(v));
599 write_h_buffer(box_count++);
600 }
601
602 std::stringstream r_buffer;
603 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
604 log_debug("flopNum = %d\n", GetSize(ff_bits));
605 write_r_buffer(ff_bits.size());
606
607 std::stringstream s_buffer;
608 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
609 write_s_buffer(ff_bits.size());
610
611 dict<SigSpec, int> clk_to_mergeability;
612 for (const auto &i : ff_bits) {
613 const SigBit &d = i.first;
614 const Cell *cell = i.second;
615
616 SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
617 auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1));
618 int mergeability = r.first->second;
619 log_assert(mergeability > 0);
620 write_r_buffer(mergeability);
621
622 SigBit Q = sigmap(cell->getPort(ID::Q));
623 State init = init_map.at(Q, State::Sx);
624 log_debug("Cell '%s' (type %s) has (* init *) value '%s'.\n", log_id(cell), log_id(cell->type), log_signal(init));
625 if (init == State::S1)
626 write_s_buffer(1);
627 else if (init == State::S0)
628 write_s_buffer(0);
629 else {
630 log_assert(init == State::Sx);
631 write_s_buffer(2);
632 }
633
634 // Use arrival time from output of flop box
635 write_i_buffer(arrival_times.at(d, 0));
636 //write_o_buffer(0);
637 }
638
639 f << "r";
640 std::string buffer_str = r_buffer.str();
641 int32_t buffer_size_be = to_big_endian(buffer_str.size());
642 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
643 f.write(buffer_str.data(), buffer_str.size());
644
645 f << "s";
646 buffer_str = s_buffer.str();
647 buffer_size_be = to_big_endian(buffer_str.size());
648 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
649 f.write(buffer_str.data(), buffer_str.size());
650
651 RTLIL::Design *holes_design;
652 auto it = saved_designs.find("$abc9_holes");
653 if (it != saved_designs.end())
654 holes_design = it->second;
655 else
656 holes_design = nullptr;
657 RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
658 if (holes_module) {
659 std::stringstream a_buffer;
660 XAigerWriter writer(holes_module, false /* dff_mode */);
661 writer.write_aiger(a_buffer, false /*ascii_mode*/);
662
663 f << "a";
664 std::string buffer_str = a_buffer.str();
665 int32_t buffer_size_be = to_big_endian(buffer_str.size());
666 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
667 f.write(buffer_str.data(), buffer_str.size());
668 }
669 }
670
671 f << "h";
672 std::string buffer_str = h_buffer.str();
673 int32_t buffer_size_be = to_big_endian(buffer_str.size());
674 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
675 f.write(buffer_str.data(), buffer_str.size());
676
677 f << "i";
678 buffer_str = i_buffer.str();
679 buffer_size_be = to_big_endian(buffer_str.size());
680 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
681 f.write(buffer_str.data(), buffer_str.size());
682 //f << "o";
683 //buffer_str = o_buffer.str();
684 //buffer_size_be = to_big_endian(buffer_str.size());
685 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
686 //f.write(buffer_str.data(), buffer_str.size());
687
688 f << stringf("Generated by %s\n", yosys_version_str);
689
690 design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
691 design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
692 design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
693 design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
694 }
695
696 void write_map(std::ostream &f)
697 {
698 dict<int, string> input_lines;
699 dict<int, string> output_lines;
700
701 for (auto wire : module->wires())
702 {
703 SigSpec sig = sigmap(wire);
704
705 for (int i = 0; i < GetSize(wire); i++)
706 {
707 RTLIL::SigBit b(wire, i);
708 if (input_bits.count(b)) {
709 int a = aig_map.at(b);
710 log_assert((a & 1) == 0);
711 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, wire->start_offset+i, log_id(wire));
712 }
713
714 if (output_bits.count(b)) {
715 int o = ordered_outputs.at(b);
716 output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), wire->start_offset+i, log_id(wire));
717 continue;
718 }
719 }
720 }
721
722 input_lines.sort();
723 for (auto &it : input_lines)
724 f << it.second;
725 log_assert(input_lines.size() == input_bits.size());
726
727 int box_count = 0;
728 for (auto cell : box_list)
729 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
730
731 output_lines.sort();
732 for (auto &it : output_lines)
733 f << it.second;
734 log_assert(output_lines.size() == output_bits.size());
735 }
736 };
737
738 struct XAigerBackend : public Backend {
739 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
740 void help() YS_OVERRIDE
741 {
742 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
743 log("\n");
744 log(" write_xaiger [options] [filename]\n");
745 log("\n");
746 log("Write the top module (according to the (* top *) attribute or if only one module\n");
747 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, (optionally\n");
748 log("$_DFF_N_, $_DFF_P_), or non (* abc9_box *) cells will be converted into psuedo-\n");
749 log("inputs and pseudo-outputs. Whitebox contents will be taken from the equivalent\n");
750 log("module in the '$abc9_holes' design, if it exists.\n");
751 log("\n");
752 log(" -ascii\n");
753 log(" write ASCII version of AIGER format\n");
754 log("\n");
755 log(" -map <filename>\n");
756 log(" write an extra file with port and box symbols\n");
757 log("\n");
758 log(" -dff\n");
759 log(" write $_DFF_[NP]_ cells\n");
760 log("\n");
761 }
762 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
763 {
764 bool ascii_mode = false, dff_mode = false;
765 std::string map_filename;
766
767 log_header(design, "Executing XAIGER backend.\n");
768
769 size_t argidx;
770 for (argidx = 1; argidx < args.size(); argidx++)
771 {
772 if (args[argidx] == "-ascii") {
773 ascii_mode = true;
774 continue;
775 }
776 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
777 map_filename = args[++argidx];
778 continue;
779 }
780 if (args[argidx] == "-dff") {
781 dff_mode = true;
782 continue;
783 }
784 break;
785 }
786 extra_args(f, filename, args, argidx, !ascii_mode);
787
788 Module *top_module = design->top_module();
789
790 if (top_module == nullptr)
791 log_error("Can't find top module in current design!\n");
792
793 if (!design->selected_whole_module(top_module))
794 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
795
796 if (!top_module->processes.empty())
797 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
798 if (!top_module->memories.empty())
799 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
800
801 XAigerWriter writer(top_module, dff_mode);
802 writer.write_aiger(*f, ascii_mode);
803
804 if (!map_filename.empty()) {
805 std::ofstream mapf;
806 mapf.open(map_filename.c_str(), std::ofstream::trunc);
807 if (mapf.fail())
808 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
809 writer.write_map(mapf);
810 }
811 }
812 } XAigerBackend;
813
814 PRIVATE_NAMESPACE_END