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write_xaiger to cope with unknown cells by transforming them to CI/CO
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 void aiger_encode(std::ostream &f, int x)
27 {
28 log_assert(x >= 0);
29
30 while (x & ~0x7f) {
31 f.put((x & 0x7f) | 0x80);
32 x = x >> 7;
33 }
34
35 f.put(x);
36 }
37
38 struct XAigerWriter
39 {
40 Module *module;
41 bool zinit_mode;
42 SigMap sigmap;
43
44 dict<SigBit, bool> init_map;
45 pool<SigBit> input_bits, output_bits;
46 dict<SigBit, SigBit> not_map, ff_map, alias_map;
47 dict<SigBit, pair<SigBit, SigBit>> and_map;
48 pool<SigBit> initstate_bits;
49 pool<SigBit> ci_bits, co_bits;
50 dict<IdString, unsigned> type_map;
51
52 vector<pair<int, int>> aig_gates;
53 vector<int> aig_latchin, aig_latchinit, aig_outputs;
54 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
55
56 dict<SigBit, int> aig_map;
57 dict<SigBit, int> ordered_outputs;
58 dict<SigBit, int> ordered_latches;
59
60 dict<SigBit, int> init_inputs;
61 int initstate_ff = 0;
62
63 int mkgate(int a0, int a1)
64 {
65 aig_m++, aig_a++;
66 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
67 return 2*aig_m;
68 }
69
70 int bit2aig(SigBit bit)
71 {
72 if (aig_map.count(bit) == 0)
73 {
74 aig_map[bit] = -1;
75
76 if (initstate_bits.count(bit)) {
77 log_assert(initstate_ff > 0);
78 aig_map[bit] = initstate_ff;
79 } else
80 if (not_map.count(bit)) {
81 int a = bit2aig(not_map.at(bit)) ^ 1;
82 aig_map[bit] = a;
83 } else
84 if (and_map.count(bit)) {
85 auto args = and_map.at(bit);
86 int a0 = bit2aig(args.first);
87 int a1 = bit2aig(args.second);
88 aig_map[bit] = mkgate(a0, a1);
89 } else
90 if (alias_map.count(bit)) {
91 aig_map[bit] = bit2aig(alias_map.at(bit));
92 }
93
94 if (bit == State::Sx || bit == State::Sz)
95 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
96 }
97
98 log_assert(aig_map.at(bit) >= 0);
99 return aig_map.at(bit);
100 }
101
102 XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
103 {
104 pool<SigBit> undriven_bits;
105 pool<SigBit> unused_bits;
106
107 // promote public wires
108 for (auto wire : module->wires())
109 if (wire->name[0] == '\\')
110 sigmap.add(wire);
111
112 // promote input wires
113 for (auto wire : module->wires())
114 if (wire->port_input)
115 sigmap.add(wire);
116
117 // promote output wires
118 for (auto wire : module->wires())
119 if (wire->port_output)
120 sigmap.add(wire);
121
122 for (auto wire : module->wires())
123 {
124 if (wire->attributes.count("\\init")) {
125 SigSpec initsig = sigmap(wire);
126 Const initval = wire->attributes.at("\\init");
127 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
128 if (initval[i] == State::S0 || initval[i] == State::S1)
129 init_map[initsig[i]] = initval[i] == State::S1;
130 }
131
132 for (int i = 0; i < GetSize(wire); i++)
133 {
134 SigBit wirebit(wire, i);
135 SigBit bit = sigmap(wirebit);
136
137 if (bit.wire == nullptr) {
138 if (wire->port_output) {
139 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
140 output_bits.insert(wirebit);
141 }
142 continue;
143 }
144
145 undriven_bits.insert(bit);
146 unused_bits.insert(bit);
147
148 if (wire->port_input)
149 input_bits.insert(bit);
150
151 if (wire->port_output) {
152 if (bit != wirebit)
153 alias_map[wirebit] = bit;
154 //output_bits.insert(wirebit);
155 }
156 }
157 }
158
159 for (auto bit : input_bits)
160 undriven_bits.erase(bit);
161
162 for (auto bit : output_bits)
163 unused_bits.erase(bit);
164
165 for (auto cell : module->cells())
166 {
167 if (cell->type == "$_NOT_")
168 {
169 SigBit A = sigmap(cell->getPort("\\A").as_bit());
170 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
171 if (Y.wire->port_output)
172 output_bits.insert(Y);
173 unused_bits.erase(A);
174 undriven_bits.erase(Y);
175 not_map[Y] = A;
176 continue;
177 }
178
179 if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
180 {
181 SigBit D = sigmap(cell->getPort("\\D").as_bit());
182 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
183 unused_bits.erase(D);
184 undriven_bits.erase(Q);
185 ff_map[Q] = D;
186 continue;
187 }
188
189 if (cell->type == "$_AND_")
190 {
191 SigBit A = sigmap(cell->getPort("\\A").as_bit());
192 SigBit B = sigmap(cell->getPort("\\B").as_bit());
193 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
194 if (Y.wire->port_output)
195 output_bits.insert(Y);
196 unused_bits.erase(A);
197 unused_bits.erase(B);
198 undriven_bits.erase(Y);
199 and_map[Y] = make_pair(A, B);
200 continue;
201 }
202
203 if (cell->type == "$initstate")
204 {
205 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
206 undriven_bits.erase(Y);
207 initstate_bits.insert(Y);
208 continue;
209 }
210
211 for (const auto &c : cell->connections()) {
212 if (c.second.is_fully_const()) continue;
213 SigBit b = c.second.as_bit();
214 Wire *w = b.wire;
215 if (cell->input(c.first)) {
216 SigBit I = sigmap(b);
217 if (!w->port_input)
218 co_bits.insert(I);
219 unused_bits.erase(I);
220 }
221 else if (cell->output(c.first)) {
222 SigBit O = sigmap(b);
223 if (!w->port_output)
224 ci_bits.insert(O);
225 undriven_bits.erase(O);
226 }
227 else log_abort();
228 if (!type_map.count(cell->type))
229 type_map[cell->type] = type_map.size()+1;
230 }
231 //log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
232 }
233
234 for (auto bit : unused_bits)
235 undriven_bits.erase(bit);
236
237 if (!undriven_bits.empty()) {
238 undriven_bits.sort();
239 for (auto bit : undriven_bits) {
240 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
241 input_bits.insert(bit);
242 }
243 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
244 }
245
246 init_map.sort();
247 input_bits.sort();
248 output_bits.sort();
249 not_map.sort();
250 ff_map.sort();
251 and_map.sort();
252
253 aig_map[State::S0] = 0;
254 aig_map[State::S1] = 1;
255
256 for (auto bit : ci_bits) {
257 aig_m++, aig_i++;
258 aig_map[bit] = 2*aig_m;
259 co_bits.erase(bit);
260 }
261
262 for (auto bit : input_bits) {
263 aig_m++, aig_i++;
264 aig_map[bit] = 2*aig_m;
265 }
266
267 if (imode && input_bits.empty()) {
268 aig_m++, aig_i++;
269 }
270
271 if (zinit_mode)
272 {
273 for (auto it : ff_map) {
274 if (init_map.count(it.first))
275 continue;
276 aig_m++, aig_i++;
277 init_inputs[it.first] = 2*aig_m;
278 }
279 }
280
281 for (auto it : ff_map) {
282 aig_m++, aig_l++;
283 aig_map[it.first] = 2*aig_m;
284 ordered_latches[it.first] = aig_l-1;
285 if (init_map.count(it.first) == 0)
286 aig_latchinit.push_back(2);
287 else
288 aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
289 }
290
291 if (!initstate_bits.empty() || !init_inputs.empty()) {
292 aig_m++, aig_l++;
293 initstate_ff = 2*aig_m+1;
294 aig_latchinit.push_back(0);
295 }
296
297 if (zinit_mode)
298 {
299 for (auto it : ff_map)
300 {
301 int l = ordered_latches[it.first];
302
303 if (aig_latchinit.at(l) == 1)
304 aig_map[it.first] ^= 1;
305
306 if (aig_latchinit.at(l) == 2)
307 {
308 int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
309 int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
310 aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
311 }
312 }
313 }
314
315 for (auto it : ff_map) {
316 int a = bit2aig(it.second);
317 int l = ordered_latches[it.first];
318 if (zinit_mode && aig_latchinit.at(l) == 1)
319 aig_latchin.push_back(a ^ 1);
320 else
321 aig_latchin.push_back(a);
322 }
323
324 if (!initstate_bits.empty() || !init_inputs.empty())
325 aig_latchin.push_back(1);
326
327 for (auto bit : co_bits) {
328 aig_o++;
329 ordered_outputs[bit] = aig_o-1;
330 aig_outputs.push_back(bit2aig(bit));
331 }
332
333 for (auto bit : output_bits) {
334 aig_o++;
335 ordered_outputs[bit] = aig_o-1;
336 aig_outputs.push_back(bit2aig(bit));
337 }
338
339 if (omode && output_bits.empty()) {
340 aig_o++;
341 aig_outputs.push_back(0);
342 }
343
344 if (bmode) {
345 //aig_b++;
346 aig_outputs.push_back(0);
347 }
348 }
349
350 void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
351 {
352 int aig_obc = aig_o;
353 int aig_obcj = aig_obc;
354 int aig_obcjf = aig_obcj;
355
356 log_assert(aig_m == aig_i + aig_l + aig_a);
357 log_assert(aig_l == GetSize(aig_latchin));
358 log_assert(aig_l == GetSize(aig_latchinit));
359 log_assert(aig_obcjf == GetSize(aig_outputs));
360
361 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
362 f << stringf("\n");
363
364 if (ascii_mode)
365 {
366 for (int i = 0; i < aig_i; i++)
367 f << stringf("%d\n", 2*i+2);
368
369 for (int i = 0; i < aig_l; i++) {
370 if (zinit_mode || aig_latchinit.at(i) == 0)
371 f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
372 else if (aig_latchinit.at(i) == 1)
373 f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
374 else if (aig_latchinit.at(i) == 2)
375 f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
376 }
377
378 for (int i = 0; i < aig_obc; i++)
379 f << stringf("%d\n", aig_outputs.at(i));
380
381 for (int i = aig_obc; i < aig_obcj; i++)
382 f << stringf("1\n");
383
384 for (int i = aig_obc; i < aig_obcj; i++)
385 f << stringf("%d\n", aig_outputs.at(i));
386
387 for (int i = aig_obcj; i < aig_obcjf; i++)
388 f << stringf("%d\n", aig_outputs.at(i));
389
390 for (int i = 0; i < aig_a; i++)
391 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
392 }
393 else
394 {
395 for (int i = 0; i < aig_l; i++) {
396 if (zinit_mode || aig_latchinit.at(i) == 0)
397 f << stringf("%d\n", aig_latchin.at(i));
398 else if (aig_latchinit.at(i) == 1)
399 f << stringf("%d 1\n", aig_latchin.at(i));
400 else if (aig_latchinit.at(i) == 2)
401 f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
402 }
403
404 for (int i = 0; i < aig_obc; i++)
405 f << stringf("%d\n", aig_outputs.at(i));
406
407 for (int i = aig_obc; i < aig_obcj; i++)
408 f << stringf("1\n");
409
410 for (int i = aig_obc; i < aig_obcj; i++)
411 f << stringf("%d\n", aig_outputs.at(i));
412
413 for (int i = aig_obcj; i < aig_obcjf; i++)
414 f << stringf("%d\n", aig_outputs.at(i));
415
416 for (int i = 0; i < aig_a; i++) {
417 int lhs = 2*(aig_i+aig_l+i)+2;
418 int rhs0 = aig_gates.at(i).first;
419 int rhs1 = aig_gates.at(i).second;
420 int delta0 = lhs - rhs0;
421 int delta1 = rhs0 - rhs1;
422 aiger_encode(f, delta0);
423 aiger_encode(f, delta1);
424 }
425 }
426
427 if (symbols_mode)
428 {
429 dict<string, vector<string>> symbols;
430
431 for (auto wire : module->wires())
432 {
433 if (wire->name[0] == '$')
434 continue;
435
436 SigSpec sig = sigmap(wire);
437
438 for (int i = 0; i < GetSize(wire); i++)
439 {
440 if (sig[i].wire == nullptr) {
441 if (wire->port_output)
442 sig[i] = SigBit(wire, i);
443 else
444 continue;
445 }
446
447 if (wire->port_input) {
448 int a = aig_map.at(sig[i]);
449 log_assert((a & 1) == 0);
450 if (GetSize(wire) != 1)
451 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
452 else
453 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
454 }
455
456 if (wire->port_output) {
457 int o = ordered_outputs.at(SigSpec(wire, i));
458 if (GetSize(wire) != 1)
459 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
460 else
461 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
462 }
463
464 if (init_inputs.count(sig[i])) {
465 int a = init_inputs.at(sig[i]);
466 log_assert((a & 1) == 0);
467 if (GetSize(wire) != 1)
468 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
469 else
470 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
471 }
472
473 if (ordered_latches.count(sig[i])) {
474 int l = ordered_latches.at(sig[i]);
475 const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
476 if (GetSize(wire) != 1)
477 symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
478 else
479 symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
480 }
481 }
482 }
483
484 symbols.sort();
485
486 for (auto &sym : symbols) {
487 f << sym.first;
488 std::sort(sym.second.begin(), sym.second.end());
489 for (auto &s : sym.second)
490 f << " " << s;
491 f << std::endl;
492 }
493 }
494
495 f << stringf("c\nGenerated by %s\n", yosys_version_str);
496 }
497
498 void write_map(std::ostream &f, bool verbose_map)
499 {
500 dict<int, string> input_lines;
501 dict<int, string> init_lines;
502 dict<int, string> output_lines;
503 dict<int, string> latch_lines;
504 dict<int, string> wire_lines;
505
506 for (auto wire : module->wires())
507 {
508 //if (!verbose_map && wire->name[0] == '$')
509 // continue;
510
511 SigSpec sig = sigmap(wire);
512
513 for (int i = 0; i < GetSize(wire); i++)
514 {
515 if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr)
516 continue;
517
518 int a = aig_map.at(sig[i]);
519
520 if (verbose_map)
521 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
522
523 if (wire->port_input || ci_bits.count(RTLIL::SigBit{wire, i})) {
524 log_assert((a & 1) == 0);
525 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
526 }
527
528 if (wire->port_output || co_bits.count(RTLIL::SigBit{wire, i})) {
529 int o = ordered_outputs.at(sig[i]);
530 output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
531 }
532
533 if (init_inputs.count(sig[i])) {
534 int a = init_inputs.at(sig[i]);
535 log_assert((a & 1) == 0);
536 init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
537 }
538
539 if (ordered_latches.count(sig[i])) {
540 int l = ordered_latches.at(sig[i]);
541 if (zinit_mode && (aig_latchinit.at(l) == 1))
542 latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
543 else
544 latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
545 }
546 }
547 }
548
549 input_lines.sort();
550 for (auto &it : input_lines)
551 f << it.second;
552
553 init_lines.sort();
554 for (auto &it : init_lines)
555 f << it.second;
556
557 output_lines.sort();
558 for (auto &it : output_lines)
559 f << it.second;
560
561 latch_lines.sort();
562 for (auto &it : latch_lines)
563 f << it.second;
564
565 wire_lines.sort();
566 for (auto &it : wire_lines)
567 f << it.second;
568 }
569 };
570
571 struct XAigerBackend : public Backend {
572 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
573 void help() YS_OVERRIDE
574 {
575 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
576 log("\n");
577 log(" write_xaiger [options] [filename]\n");
578 log("\n");
579 log("Write the current design to an XAIGER file. The design must be flattened and\n");
580 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
581 log("\n");
582 log(" -ascii\n");
583 log(" write ASCII version of AGIER format\n");
584 log("\n");
585 log(" -zinit\n");
586 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
587 log(" uninitialized FFs.\n");
588 log("\n");
589 log(" -symbols\n");
590 log(" include a symbol table in the generated AIGER file\n");
591 log("\n");
592 log(" -map <filename>\n");
593 log(" write an extra file with port and latch symbols\n");
594 log("\n");
595 log(" -vmap <filename>\n");
596 log(" like -map, but more verbose\n");
597 log("\n");
598 log(" -I, -O, -B\n");
599 log(" If the design contains no input/output/assert then create one\n");
600 log(" dummy input/output/bad_state pin to make the tools reading the\n");
601 log(" AIGER file happy.\n");
602 log("\n");
603 }
604 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
605 {
606 bool ascii_mode = false;
607 bool zinit_mode = false;
608 bool miter_mode = false;
609 bool symbols_mode = false;
610 bool verbose_map = false;
611 bool imode = false;
612 bool omode = false;
613 bool bmode = false;
614 std::string map_filename;
615
616 log_header(design, "Executing XAIGER backend.\n");
617
618 size_t argidx;
619 for (argidx = 1; argidx < args.size(); argidx++)
620 {
621 if (args[argidx] == "-ascii") {
622 ascii_mode = true;
623 continue;
624 }
625 if (args[argidx] == "-zinit") {
626 zinit_mode = true;
627 continue;
628 }
629 if (args[argidx] == "-symbols") {
630 symbols_mode = true;
631 continue;
632 }
633 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
634 map_filename = args[++argidx];
635 continue;
636 }
637 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
638 map_filename = args[++argidx];
639 verbose_map = true;
640 continue;
641 }
642 if (args[argidx] == "-I") {
643 imode = true;
644 continue;
645 }
646 if (args[argidx] == "-O") {
647 omode = true;
648 continue;
649 }
650 if (args[argidx] == "-B") {
651 bmode = true;
652 continue;
653 }
654 break;
655 }
656 extra_args(f, filename, args, argidx);
657
658 Module *top_module = design->top_module();
659
660 if (top_module == nullptr)
661 log_error("Can't find top module in current design!\n");
662
663 XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
664 writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
665
666 if (!map_filename.empty()) {
667 std::ofstream mapf;
668 mapf.open(map_filename.c_str(), std::ofstream::trunc);
669 if (mapf.fail())
670 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
671 writer.write_map(mapf, verbose_map);
672 }
673 }
674 } XAigerBackend;
675
676 PRIVATE_NAMESPACE_END