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Use new -wb flag for ABC flow
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/yosys.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/utils.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 void aiger_encode(std::ostream &f, int x)
30 {
31 log_assert(x >= 0);
32
33 while (x & ~0x7f) {
34 f.put((x & 0x7f) | 0x80);
35 x = x >> 7;
36 }
37
38 f.put(x);
39 }
40
41 struct XAigerWriter
42 {
43 Module *module;
44 bool zinit_mode;
45 SigMap sigmap;
46
47 dict<SigBit, bool> init_map;
48 pool<SigBit> input_bits, output_bits;
49 dict<SigBit, SigBit> not_map, ff_map, alias_map;
50 dict<SigBit, pair<SigBit, SigBit>> and_map;
51 //pool<SigBit> initstate_bits;
52 vector<std::pair<SigBit,int>> ci_bits, co_bits;
53
54 vector<pair<int, int>> aig_gates;
55 vector<int> aig_latchin, aig_latchinit, aig_outputs;
56 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
57
58 dict<SigBit, int> aig_map;
59 dict<SigBit, int> ordered_outputs;
60 dict<SigBit, int> ordered_latches;
61
62 vector<Cell*> box_list;
63
64 //dict<SigBit, int> init_inputs;
65 //int initstate_ff = 0;
66
67 int mkgate(int a0, int a1)
68 {
69 aig_m++, aig_a++;
70 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
71 return 2*aig_m;
72 }
73
74 int bit2aig(SigBit bit)
75 {
76 if (aig_map.count(bit) == 0)
77 {
78 aig_map[bit] = -1;
79
80 //if (initstate_bits.count(bit)) {
81 // log_assert(initstate_ff > 0);
82 // aig_map[bit] = initstate_ff;
83 //} else
84 if (not_map.count(bit)) {
85 int a = bit2aig(not_map.at(bit)) ^ 1;
86 aig_map[bit] = a;
87 } else
88 if (and_map.count(bit)) {
89 auto args = and_map.at(bit);
90 int a0 = bit2aig(args.first);
91 int a1 = bit2aig(args.second);
92 aig_map[bit] = mkgate(a0, a1);
93 } else
94 if (alias_map.count(bit)) {
95 aig_map[bit] = bit2aig(alias_map.at(bit));
96 }
97
98 if (bit == State::Sx || bit == State::Sz)
99 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
100 }
101
102 log_assert(aig_map.at(bit) >= 0);
103 return aig_map.at(bit);
104 }
105
106 XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool ignore_boxes=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
107 {
108 pool<SigBit> undriven_bits;
109 pool<SigBit> unused_bits;
110
111 // promote public wires
112 for (auto wire : module->wires())
113 if (wire->name[0] == '\\')
114 sigmap.add(wire);
115
116 // promote input wires
117 for (auto wire : module->wires())
118 if (wire->port_input)
119 sigmap.add(wire);
120
121 // promote output wires
122 for (auto wire : module->wires())
123 if (wire->port_output)
124 sigmap.add(wire);
125
126 for (auto wire : module->wires())
127 {
128 if (wire->attributes.count("\\init")) {
129 SigSpec initsig = sigmap(wire);
130 Const initval = wire->attributes.at("\\init");
131 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
132 if (initval[i] == State::S0 || initval[i] == State::S1)
133 init_map[initsig[i]] = initval[i] == State::S1;
134 }
135
136 for (int i = 0; i < GetSize(wire); i++)
137 {
138 SigBit wirebit(wire, i);
139 SigBit bit = sigmap(wirebit);
140
141 if (bit.wire == nullptr) {
142 if (wire->port_output) {
143 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
144 output_bits.insert(wirebit);
145 }
146 continue;
147 }
148
149 undriven_bits.insert(bit);
150 unused_bits.insert(bit);
151
152 if (wire->port_input)
153 input_bits.insert(bit);
154
155 if (wire->port_output) {
156 if (bit != wirebit)
157 alias_map[wirebit] = bit;
158 output_bits.insert(wirebit);
159 }
160 }
161 }
162
163 for (auto bit : input_bits) {
164 if (!bit.wire->port_output)
165 undriven_bits.erase(bit);
166 // Erase POs that are also PIs
167 output_bits.erase(bit);
168 }
169
170 for (auto bit : output_bits)
171 if (!bit.wire->port_input)
172 unused_bits.erase(bit);
173
174 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
175 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
176 bool abc_box_seen = false;
177
178 for (auto cell : module->cells())
179 {
180 if (!ignore_boxes) {
181 toposort.node(cell->name);
182 for (const auto &conn : cell->connections())
183 {
184 if (!cell->type.in("$_NOT_", "$_AND_")) {
185 if (yosys_celltypes.cell_known(cell->type)) {
186 if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
187 continue;
188 if (cell->type == "$memrd" && conn.first == "\\DATA")
189 continue;
190 }
191
192 RTLIL::Module* inst_module = module->design->module(cell->type);
193 log_assert(inst_module);
194 RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
195 log_assert(inst_module_port);
196
197 if (inst_module_port->attributes.count("\\abc_flop_q"))
198 continue;
199 }
200
201 if (cell->input(conn.first)) {
202 // Ignore inout for the sake of topographical ordering
203 if (cell->output(conn.first)) continue;
204 for (auto bit : sigmap(conn.second))
205 bit_users[bit].insert(cell->name);
206 }
207
208 if (cell->output(conn.first))
209 for (auto bit : sigmap(conn.second))
210 bit_drivers[bit].insert(cell->name);
211 }
212 }
213
214 if (cell->type == "$_NOT_")
215 {
216 SigBit A = sigmap(cell->getPort("\\A").as_bit());
217 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
218 unused_bits.erase(A);
219 undriven_bits.erase(Y);
220 not_map[Y] = A;
221 continue;
222 }
223
224 //if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
225 //{
226 // SigBit D = sigmap(cell->getPort("\\D").as_bit());
227 // SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
228 // unused_bits.erase(D);
229 // undriven_bits.erase(Q);
230 // ff_map[Q] = D;
231 // continue;
232 //}
233
234 if (cell->type == "$_AND_")
235 {
236 SigBit A = sigmap(cell->getPort("\\A").as_bit());
237 SigBit B = sigmap(cell->getPort("\\B").as_bit());
238 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
239 unused_bits.erase(A);
240 unused_bits.erase(B);
241 undriven_bits.erase(Y);
242 and_map[Y] = make_pair(A, B);
243 continue;
244 }
245
246 //if (cell->type == "$initstate")
247 //{
248 // SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
249 // undriven_bits.erase(Y);
250 // initstate_bits.insert(Y);
251 // continue;
252 //}
253
254 RTLIL::Module* box_module = !ignore_boxes ? module->design->module(cell->type) : nullptr;
255 if (!box_module || !box_module->attributes.count("\\abc_box_id")) {
256 for (const auto &c : cell->connections()) {
257 if (c.second.is_fully_const()) continue;
258 for (auto b : c.second.bits()) {
259 Wire *w = b.wire;
260 if (!w) continue;
261 auto is_input = cell->input(c.first);
262 auto is_output = cell->output(c.first);
263 log_assert(is_input || is_output);
264 if (is_input) {
265 if (!w->port_input) {
266 SigBit I = sigmap(b);
267 if (I != b)
268 alias_map[b] = I;
269 output_bits.insert(b);
270 unused_bits.erase(b);
271 }
272 }
273 if (is_output) {
274 SigBit O = sigmap(b);
275 input_bits.insert(O);
276 undriven_bits.erase(O);
277 }
278 }
279 }
280 }
281 else
282 abc_box_seen = true;
283
284 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
285 }
286
287 if (abc_box_seen) {
288 for (auto &it : bit_users)
289 if (bit_drivers.count(it.first))
290 for (auto driver_cell : bit_drivers.at(it.first))
291 for (auto user_cell : it.second)
292 toposort.edge(driver_cell, user_cell);
293
294 #ifndef NDEBUG
295 toposort.analyze_loops = true;
296 #endif
297 toposort.sort();
298 #ifndef NDEBUG
299 for (auto &it : toposort.loops) {
300 log(" loop");
301 for (auto cell : it)
302 log(" %s", log_id(cell));
303 log("\n");
304 }
305 #endif
306 log_assert(!toposort.found_loops);
307
308 for (auto cell_name : toposort.sorted) {
309 RTLIL::Cell *cell = module->cell(cell_name);
310 RTLIL::Module* box_module = module->design->module(cell->type);
311 if (!box_module || !box_module->attributes.count("\\abc_box_id"))
312 continue;
313
314 cell->connections_.sort(RTLIL::sort_by_id_str());
315 for (const auto &c : cell->connections()) {
316 for (auto b : c.second.bits()) {
317 auto is_input = cell->input(c.first);
318 auto is_output = cell->output(c.first);
319 log_assert(is_input || is_output);
320 if (is_input) {
321 SigBit I = sigmap(b);
322 if (I != b)
323 alias_map[b] = I;
324 co_bits.emplace_back(b, 0);
325 }
326 if (is_output) {
327 SigBit O = sigmap(b);
328 ci_bits.emplace_back(O, 0);
329 }
330 }
331 }
332
333 box_list.emplace_back(cell);
334 }
335
336 // TODO: Free memory from toposort, bit_drivers, bit_users
337 }
338
339 for (auto bit : input_bits) {
340 RTLIL::Wire *wire = bit.wire;
341 // If encountering an inout port, then create a new wire with $inout.out
342 // suffix, make it a PO driven by the existing inout, and inherit existing
343 // inout's drivers
344 if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) {
345 RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
346 if (!new_wire)
347 new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
348 SigBit new_bit(new_wire, bit.offset);
349 module->connect(new_bit, bit);
350 if (not_map.count(bit))
351 not_map[new_bit] = not_map.at(bit);
352 else if (and_map.count(bit))
353 and_map[new_bit] = and_map.at(bit);
354 else if (alias_map.count(bit))
355 alias_map[new_bit] = alias_map.at(bit);
356 output_bits.insert(new_bit);
357 }
358 }
359
360 // Do some CI/CO post-processing:
361 // Erase all POs and COs that are undriven
362 for (auto bit : undriven_bits) {
363 //co_bits.erase(bit);
364 output_bits.erase(bit);
365 }
366 // CIs cannot be undriven
367 for (const auto &c : ci_bits)
368 undriven_bits.erase(c.first);
369
370 for (auto bit : unused_bits)
371 undriven_bits.erase(bit);
372
373 if (!undriven_bits.empty()) {
374 undriven_bits.sort();
375 for (auto bit : undriven_bits) {
376 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
377 input_bits.insert(bit);
378 }
379 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
380 }
381
382 init_map.sort();
383 input_bits.sort();
384 output_bits.sort();
385 not_map.sort();
386 ff_map.sort();
387 and_map.sort();
388
389 aig_map[State::S0] = 0;
390 aig_map[State::S1] = 1;
391
392 for (auto bit : input_bits) {
393 aig_m++, aig_i++;
394 aig_map[bit] = 2*aig_m;
395 }
396
397 for (auto &c : ci_bits) {
398 aig_m++, aig_i++;
399 c.second = 2*aig_m;
400 aig_map[c.first] = c.second;
401 }
402
403 if (imode && input_bits.empty()) {
404 aig_m++, aig_i++;
405 }
406
407 //if (zinit_mode)
408 //{
409 // for (auto it : ff_map) {
410 // if (init_map.count(it.first))
411 // continue;
412 // aig_m++, aig_i++;
413 // init_inputs[it.first] = 2*aig_m;
414 // }
415 //}
416
417 for (auto it : ff_map) {
418 aig_m++, aig_l++;
419 aig_map[it.first] = 2*aig_m;
420 ordered_latches[it.first] = aig_l-1;
421 if (init_map.count(it.first) == 0)
422 aig_latchinit.push_back(2);
423 else
424 aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
425 }
426
427 //if (!initstate_bits.empty() || !init_inputs.empty()) {
428 // aig_m++, aig_l++;
429 // initstate_ff = 2*aig_m+1;
430 // aig_latchinit.push_back(0);
431 //}
432
433 //if (zinit_mode)
434 //{
435 // for (auto it : ff_map)
436 // {
437 // int l = ordered_latches[it.first];
438
439 // if (aig_latchinit.at(l) == 1)
440 // aig_map[it.first] ^= 1;
441
442 // if (aig_latchinit.at(l) == 2)
443 // {
444 // int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
445 // int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
446 // aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
447 // }
448 // }
449 //}
450
451 for (auto it : ff_map) {
452 int a = bit2aig(it.second);
453 int l = ordered_latches[it.first];
454 if (zinit_mode && aig_latchinit.at(l) == 1)
455 aig_latchin.push_back(a ^ 1);
456 else
457 aig_latchin.push_back(a);
458 }
459
460 //if (!initstate_bits.empty() || !init_inputs.empty())
461 // aig_latchin.push_back(1);
462
463 for (auto &c : co_bits) {
464 RTLIL::SigBit bit = c.first;
465 c.second = aig_o++;
466 ordered_outputs[bit] = c.second;
467 aig_outputs.push_back(bit2aig(bit));
468 }
469
470 for (auto bit : output_bits) {
471 ordered_outputs[bit] = aig_o++;
472 aig_outputs.push_back(bit2aig(bit));
473 }
474
475 if (omode && output_bits.empty()) {
476 aig_o++;
477 aig_outputs.push_back(0);
478 }
479
480 if (bmode) {
481 //aig_b++;
482 aig_outputs.push_back(0);
483 }
484 }
485
486 void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
487 {
488 int aig_obc = aig_o;
489 int aig_obcj = aig_obc;
490 int aig_obcjf = aig_obcj;
491
492 log_assert(aig_m == aig_i + aig_l + aig_a);
493 log_assert(aig_l == GetSize(aig_latchin));
494 log_assert(aig_l == GetSize(aig_latchinit));
495 log_assert(aig_obcjf == GetSize(aig_outputs));
496
497 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
498 f << stringf("\n");
499
500 if (ascii_mode)
501 {
502 for (int i = 0; i < aig_i; i++)
503 f << stringf("%d\n", 2*i+2);
504
505 for (int i = 0; i < aig_l; i++) {
506 if (zinit_mode || aig_latchinit.at(i) == 0)
507 f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
508 else if (aig_latchinit.at(i) == 1)
509 f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
510 else if (aig_latchinit.at(i) == 2)
511 f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
512 }
513
514 for (int i = 0; i < aig_obc; i++)
515 f << stringf("%d\n", aig_outputs.at(i));
516
517 for (int i = aig_obc; i < aig_obcj; i++)
518 f << stringf("1\n");
519
520 for (int i = aig_obc; i < aig_obcj; i++)
521 f << stringf("%d\n", aig_outputs.at(i));
522
523 for (int i = aig_obcj; i < aig_obcjf; i++)
524 f << stringf("%d\n", aig_outputs.at(i));
525
526 for (int i = 0; i < aig_a; i++)
527 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
528 }
529 else
530 {
531 for (int i = 0; i < aig_l; i++) {
532 if (zinit_mode || aig_latchinit.at(i) == 0)
533 f << stringf("%d\n", aig_latchin.at(i));
534 else if (aig_latchinit.at(i) == 1)
535 f << stringf("%d 1\n", aig_latchin.at(i));
536 else if (aig_latchinit.at(i) == 2)
537 f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
538 }
539
540 for (int i = 0; i < aig_obc; i++)
541 f << stringf("%d\n", aig_outputs.at(i));
542
543 for (int i = aig_obc; i < aig_obcj; i++)
544 f << stringf("1\n");
545
546 for (int i = aig_obc; i < aig_obcj; i++)
547 f << stringf("%d\n", aig_outputs.at(i));
548
549 for (int i = aig_obcj; i < aig_obcjf; i++)
550 f << stringf("%d\n", aig_outputs.at(i));
551
552 for (int i = 0; i < aig_a; i++) {
553 int lhs = 2*(aig_i+aig_l+i)+2;
554 int rhs0 = aig_gates.at(i).first;
555 int rhs1 = aig_gates.at(i).second;
556 int delta0 = lhs - rhs0;
557 int delta1 = rhs0 - rhs1;
558 aiger_encode(f, delta0);
559 aiger_encode(f, delta1);
560 }
561 }
562
563 if (symbols_mode)
564 {
565 dict<string, vector<string>> symbols;
566
567 bool output_seen = false;
568 for (auto wire : module->wires())
569 {
570 //if (wire->name[0] == '$')
571 // continue;
572
573 SigSpec sig = sigmap(wire);
574
575 for (int i = 0; i < GetSize(wire); i++)
576 {
577 RTLIL::SigBit b(wire, i);
578 if (input_bits.count(b)) {
579 int a = aig_map.at(sig[i]);
580 log_assert((a & 1) == 0);
581 if (GetSize(wire) != 1)
582 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
583 else
584 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
585 }
586
587 if (output_bits.count(b)) {
588 int o = ordered_outputs.at(b);
589 output_seen = !miter_mode;
590 if (GetSize(wire) != 1)
591 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
592 else
593 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
594 }
595
596 //if (init_inputs.count(sig[i])) {
597 // int a = init_inputs.at(sig[i]);
598 // log_assert((a & 1) == 0);
599 // if (GetSize(wire) != 1)
600 // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
601 // else
602 // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
603 //}
604
605 if (ordered_latches.count(sig[i])) {
606 int l = ordered_latches.at(sig[i]);
607 const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
608 if (GetSize(wire) != 1)
609 symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
610 else
611 symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
612 }
613 }
614 }
615
616 if (omode && !output_seen)
617 symbols["o0"].push_back("__dummy_o__");
618
619 symbols.sort();
620
621 for (auto &sym : symbols) {
622 f << sym.first;
623 std::sort(sym.second.begin(), sym.second.end());
624 for (auto &s : sym.second)
625 f << " " << s;
626 f << std::endl;
627 }
628 }
629
630 f << "c";
631
632 if (!box_list.empty()) {
633 std::stringstream h_buffer;
634 auto write_h_buffer = [&h_buffer](int i32) {
635 // TODO: Don't assume we're on little endian
636 #ifdef _WIN32
637 int i32_be = _byteswap_ulong(i32);
638 #else
639 int i32_be = __builtin_bswap32(i32);
640 #endif
641 h_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
642 };
643 int num_outputs = output_bits.size();
644 if (omode && num_outputs == 0)
645 num_outputs = 1;
646 write_h_buffer(1);
647 write_h_buffer(input_bits.size() + ci_bits.size());
648 write_h_buffer(num_outputs + co_bits.size());
649 write_h_buffer(input_bits.size());
650 write_h_buffer(num_outputs);
651 write_h_buffer(box_list.size());
652
653 RTLIL::Module *holes_module = nullptr;
654 holes_module = module->design->addModule("\\__holes__");
655
656 for (auto cell : box_list) {
657 int box_inputs = 0, box_outputs = 0;
658 int box_id = module->design->module(cell->type)->attributes.at("\\abc_box_id").as_int();
659 Cell *holes_cell = nullptr;
660 if (holes_module && !holes_module->cell(stringf("\\u%d", box_id)))
661 holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
662 RTLIL::Wire *holes_wire;
663 // NB: cell->connections_ already sorted from before
664 for (const auto &c : cell->connections()) {
665 log_assert(c.second.size() == 1);
666 if (cell->input(c.first)) {
667 box_inputs += c.second.size();
668 if (holes_cell) {
669 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
670 if (!holes_wire) {
671 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
672 holes_wire->port_input = true;
673 }
674 holes_cell->setPort(c.first, holes_wire);
675 }
676 }
677 if (cell->output(c.first)) {
678 box_outputs += c.second.size();
679 if (holes_cell) {
680 holes_wire = holes_module->addWire(stringf("\\%s.%s", cell->type.c_str(), c.first.c_str()));
681 holes_wire->port_output = true;
682 holes_cell->setPort(c.first, holes_wire);
683 }
684 }
685 }
686 write_h_buffer(box_inputs);
687 write_h_buffer(box_outputs);
688 write_h_buffer(box_id);
689 write_h_buffer(0 /* OldBoxNum */);
690 }
691
692 f << "h";
693 std::string buffer_str = h_buffer.str();
694 // TODO: Don't assume we're on little endian
695 #ifdef _WIN32
696 int buffer_size_be = _byteswap_ulong(buffer_str.size());
697 #else
698 int buffer_size_be = __builtin_bswap32(buffer_str.size());
699 #endif
700 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
701 f.write(buffer_str.data(), buffer_str.size());
702
703 if (holes_module) {
704 holes_module->fixup_ports();
705
706 holes_module->design->selection_stack.emplace_back(false);
707 RTLIL::Selection& sel = holes_module->design->selection_stack.back();
708 sel.select(holes_module);
709
710 Pass::call(holes_module->design, "flatten -wb; aigmap");
711
712 holes_module->design->selection_stack.pop_back();
713
714 std::stringstream a_buffer;
715 XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/, true /* ignore_boxes */);
716 writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/);
717
718 f << "a";
719 std::string buffer_str = a_buffer.str();
720 // TODO: Don't assume we're on little endian
721 #ifdef _WIN32
722 int buffer_size_be = _byteswap_ulong(buffer_str.size());
723 #else
724 int buffer_size_be = __builtin_bswap32(buffer_str.size());
725 #endif
726 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
727 f.write(buffer_str.data(), buffer_str.size());
728 holes_module->design->remove(holes_module);
729 }
730 }
731
732 f << stringf("Generated by %s\n", yosys_version_str);
733 }
734
735 void write_map(std::ostream &f, bool verbose_map, bool omode)
736 {
737 dict<int, string> input_lines;
738 dict<int, string> init_lines;
739 dict<int, string> output_lines;
740 dict<int, string> latch_lines;
741 dict<int, string> wire_lines;
742
743 for (auto wire : module->wires())
744 {
745 //if (!verbose_map && wire->name[0] == '$')
746 // continue;
747
748 SigSpec sig = sigmap(wire);
749
750 for (int i = 0; i < GetSize(wire); i++)
751 {
752 RTLIL::SigBit b(wire, i);
753 if (input_bits.count(b)) {
754 int a = aig_map.at(sig[i]);
755 log_assert((a & 1) == 0);
756 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
757 }
758
759 if (output_bits.count(b)) {
760 int o = ordered_outputs.at(b);
761 output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
762 continue;
763 }
764
765 //if (init_inputs.count(sig[i])) {
766 // int a = init_inputs.at(sig[i]);
767 // log_assert((a & 1) == 0);
768 // init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
769 // continue;
770 //}
771
772 if (ordered_latches.count(sig[i])) {
773 int l = ordered_latches.at(sig[i]);
774 if (zinit_mode && (aig_latchinit.at(l) == 1))
775 latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
776 else
777 latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
778 continue;
779 }
780
781 if (verbose_map) {
782 if (aig_map.count(sig[i]) == 0)
783 continue;
784
785 int a = aig_map.at(sig[i]);
786 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
787 }
788 }
789 }
790
791 for (const auto &c : ci_bits) {
792 RTLIL::SigBit b = c.first;
793 RTLIL::Wire *wire = b.wire;
794 int i = b.offset;
795 int a = c.second;
796 log_assert((a & 1) == 0);
797 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
798 }
799
800 for (const auto &c : co_bits) {
801 RTLIL::SigBit b = c.first;
802 RTLIL::Wire *wire = b.wire;
803 int o = c.second;
804 if (wire)
805 output_lines[o] += stringf("output %d %d %s\n", o, b.offset, log_id(wire));
806 else
807 output_lines[o] += stringf("output %d %d __const%d__\n", o, 0, b.data);
808 }
809
810 input_lines.sort();
811 for (auto &it : input_lines)
812 f << it.second;
813 log_assert(input_lines.size() == input_bits.size() + ci_bits.size());
814
815 init_lines.sort();
816 for (auto &it : init_lines)
817 f << it.second;
818
819 output_lines.sort();
820 for (auto &it : output_lines)
821 f << it.second;
822 log_assert(output_lines.size() == output_bits.size() + co_bits.size());
823 if (omode && output_bits.empty())
824 f << "output " << output_lines.size() << " 0 __dummy_o__\n";
825
826 latch_lines.sort();
827 for (auto &it : latch_lines)
828 f << it.second;
829
830 wire_lines.sort();
831 for (auto &it : wire_lines)
832 f << it.second;
833 }
834 };
835
836 struct XAigerBackend : public Backend {
837 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
838 void help() YS_OVERRIDE
839 {
840 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
841 log("\n");
842 log(" write_xaiger [options] [filename]\n");
843 log("\n");
844 log("Write the current design to an XAIGER file. The design must be flattened and\n");
845 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
846 log("\n");
847 log(" -ascii\n");
848 log(" write ASCII version of AGIER format\n");
849 log("\n");
850 log(" -zinit\n");
851 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
852 log(" uninitialized FFs.\n");
853 log("\n");
854 log(" -symbols\n");
855 log(" include a symbol table in the generated AIGER file\n");
856 log("\n");
857 log(" -map <filename>\n");
858 log(" write an extra file with port and latch symbols\n");
859 log("\n");
860 log(" -vmap <filename>\n");
861 log(" like -map, but more verbose\n");
862 log("\n");
863 log(" -I, -O, -B\n");
864 log(" If the design contains no input/output/assert then create one\n");
865 log(" dummy input/output/bad_state pin to make the tools reading the\n");
866 log(" AIGER file happy.\n");
867 log("\n");
868 }
869 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
870 {
871 bool ascii_mode = false;
872 bool zinit_mode = false;
873 bool miter_mode = false;
874 bool symbols_mode = false;
875 bool verbose_map = false;
876 bool imode = false;
877 bool omode = false;
878 bool bmode = false;
879 std::string map_filename;
880
881 log_header(design, "Executing XAIGER backend.\n");
882
883 size_t argidx;
884 for (argidx = 1; argidx < args.size(); argidx++)
885 {
886 if (args[argidx] == "-ascii") {
887 ascii_mode = true;
888 continue;
889 }
890 if (args[argidx] == "-zinit") {
891 zinit_mode = true;
892 continue;
893 }
894 if (args[argidx] == "-symbols") {
895 symbols_mode = true;
896 continue;
897 }
898 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
899 map_filename = args[++argidx];
900 continue;
901 }
902 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
903 map_filename = args[++argidx];
904 verbose_map = true;
905 continue;
906 }
907 if (args[argidx] == "-I") {
908 imode = true;
909 continue;
910 }
911 if (args[argidx] == "-O") {
912 omode = true;
913 continue;
914 }
915 if (args[argidx] == "-B") {
916 bmode = true;
917 continue;
918 }
919 break;
920 }
921 extra_args(f, filename, args, argidx);
922
923 Module *top_module = design->top_module();
924
925 if (top_module == nullptr)
926 log_error("Can't find top module in current design!\n");
927
928 XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
929 writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
930
931 if (!map_filename.empty()) {
932 std::ofstream mapf;
933 mapf.open(map_filename.c_str(), std::ofstream::trunc);
934 if (mapf.fail())
935 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
936 writer.write_map(mapf, verbose_map, omode);
937 }
938 }
939 } XAigerBackend;
940
941 PRIVATE_NAMESPACE_END