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Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
51
52 USING_YOSYS_NAMESPACE
53 PRIVATE_NAMESPACE_BEGIN
54
55 inline int32_t to_big_endian(int32_t i32) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 return bswap32(i32);
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
59 return i32;
60 #else
61 #error "Unknown endianness"
62 #endif
63 }
64
65 void aiger_encode(std::ostream &f, int x)
66 {
67 log_assert(x >= 0);
68
69 while (x & ~0x7f) {
70 f.put((x & 0x7f) | 0x80);
71 x = x >> 7;
72 }
73
74 f.put(x);
75 }
76
77 struct XAigerWriter
78 {
79 Module *module;
80 SigMap sigmap;
81
82 dict<SigBit, State> init_map;
83 pool<SigBit> input_bits, output_bits;
84 dict<SigBit, SigBit> not_map, alias_map;
85 dict<SigBit, pair<SigBit, SigBit>> and_map;
86 vector<SigBit> ci_bits, co_bits;
87 dict<SigBit, Cell*> ff_bits;
88 dict<SigBit, float> arrival_times;
89
90 vector<pair<int, int>> aig_gates;
91 vector<int> aig_outputs;
92 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
93
94 dict<SigBit, int> aig_map;
95 dict<SigBit, int> ordered_outputs;
96
97 vector<Cell*> box_list;
98
99 int mkgate(int a0, int a1)
100 {
101 aig_m++, aig_a++;
102 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
103 return 2*aig_m;
104 }
105
106 int bit2aig(SigBit bit)
107 {
108 auto it = aig_map.find(bit);
109 if (it != aig_map.end()) {
110 log_assert(it->second >= 0);
111 return it->second;
112 }
113
114 // NB: Cannot use iterator returned from aig_map.insert()
115 // since this function is called recursively
116
117 int a = -1;
118 if (not_map.count(bit)) {
119 a = bit2aig(not_map.at(bit)) ^ 1;
120 } else
121 if (and_map.count(bit)) {
122 auto args = and_map.at(bit);
123 int a0 = bit2aig(args.first);
124 int a1 = bit2aig(args.second);
125 a = mkgate(a0, a1);
126 } else
127 if (alias_map.count(bit)) {
128 a = bit2aig(alias_map.at(bit));
129 }
130
131 if (bit == State::Sx || bit == State::Sz) {
132 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
133 a = aig_map.at(State::S0);
134 }
135
136 log_assert(a >= 0);
137 aig_map[bit] = a;
138 return a;
139 }
140
141 XAigerWriter(Module *module, bool dff_mode) : module(module), sigmap(module)
142 {
143 pool<SigBit> undriven_bits;
144 pool<SigBit> unused_bits;
145
146 // promote public wires
147 for (auto wire : module->wires())
148 if (wire->name[0] == '\\')
149 sigmap.add(wire);
150
151 // promote input wires
152 for (auto wire : module->wires())
153 if (wire->port_input)
154 sigmap.add(wire);
155
156 // promote keep wires
157 for (auto wire : module->wires())
158 if (wire->get_bool_attribute(ID::keep))
159 sigmap.add(wire);
160
161 for (auto wire : module->wires()) {
162 auto it = wire->attributes.find(ID::init);
163 for (int i = 0; i < GetSize(wire); i++)
164 {
165 SigBit wirebit(wire, i);
166 SigBit bit = sigmap(wirebit);
167
168 if (bit.wire == nullptr) {
169 if (wire->port_output) {
170 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
171 output_bits.insert(wirebit);
172 }
173 continue;
174 }
175
176 undriven_bits.insert(bit);
177 unused_bits.insert(bit);
178
179 bool scc = wire->attributes.count(ID::abc9_scc);
180 if (wire->port_input || scc)
181 input_bits.insert(bit);
182
183 bool keep = wire->get_bool_attribute(ID::keep);
184 if (wire->port_output || keep || scc) {
185 if (bit != wirebit)
186 alias_map[wirebit] = bit;
187 output_bits.insert(wirebit);
188 }
189
190 if (it != wire->attributes.end()) {
191 auto s = it->second[i];
192 if (s != State::Sx) {
193 auto r = init_map.insert(std::make_pair(bit, it->second[i]));
194 if (!r.second && r.first->second != it->second[i])
195 log_error("Bit '%s' has a conflicting (* init *) value.\n", log_signal(bit));
196 }
197 }
198 }
199 }
200
201 TimingInfo timing;
202
203 for (auto cell : module->cells()) {
204 if (!cell->has_keep_attr()) {
205 if (cell->type == ID($_NOT_))
206 {
207 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
208 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
209 unused_bits.erase(A);
210 undriven_bits.erase(Y);
211 not_map[Y] = A;
212 continue;
213 }
214
215 if (cell->type == ID($_AND_))
216 {
217 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
218 SigBit B = sigmap(cell->getPort(ID::B).as_bit());
219 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
220 unused_bits.erase(A);
221 unused_bits.erase(B);
222 undriven_bits.erase(Y);
223 and_map[Y] = make_pair(A, B);
224 continue;
225 }
226
227 if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
228 {
229 SigBit D = sigmap(cell->getPort(ID::D).as_bit());
230 SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
231 unused_bits.erase(D);
232 undriven_bits.erase(Q);
233 alias_map[Q] = D;
234 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
235 log_assert(r.second);
236 continue;
237 }
238
239 if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
240 continue;
241 }
242
243 RTLIL::Module* inst_module = module->design->module(cell->type);
244 if (inst_module) {
245 IdString derived_type;
246 if (cell->parameters.empty())
247 derived_type = cell->type;
248 else
249 derived_type = inst_module->derive(module->design, cell->parameters);
250 inst_module = module->design->module(derived_type);
251 log_assert(inst_module);
252
253 bool abc9_flop = false;
254 if (!cell->has_keep_attr()) {
255 auto it = cell->attributes.find(ID::abc9_box_seq);
256 if (it != cell->attributes.end()) {
257 int abc9_box_seq = it->second.as_int();
258 if (GetSize(box_list) <= abc9_box_seq)
259 box_list.resize(abc9_box_seq+1);
260 box_list[abc9_box_seq] = cell;
261 // Only flop boxes may have arrival times
262 // (all others are combinatorial)
263 abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
264 if (!abc9_flop)
265 continue;
266 }
267 }
268
269 if (!timing.count(derived_type))
270 timing.setup_module(inst_module);
271 auto &t = timing.at(derived_type).arrival;
272 for (const auto &conn : cell->connections()) {
273 auto port_wire = inst_module->wire(conn.first);
274 if (!port_wire->port_output)
275 continue;
276
277 for (int i = 0; i < GetSize(conn.second); i++) {
278 auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
279 if (d == 0)
280 continue;
281
282 #ifndef NDEBUG
283 if (ys_debug(1)) {
284 static std::set<std::tuple<IdString,IdString,int>> seen;
285 if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
286 log_id(cell->type), log_id(conn.first), i, d);
287 }
288 #endif
289 arrival_times[conn.second[i]] = d;
290 }
291 }
292
293 if (abc9_flop)
294 continue;
295 }
296
297 bool cell_known = inst_module || cell->known();
298 for (const auto &c : cell->connections()) {
299 if (c.second.is_fully_const()) continue;
300 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
301 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
302 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
303 if (!is_input && !is_output)
304 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
305
306 if (is_input)
307 for (auto b : c.second) {
308 Wire *w = b.wire;
309 if (!w) continue;
310 // Do not add as PO if bit is already a PI
311 if (input_bits.count(b))
312 continue;
313 if (!w->port_output || !cell_known) {
314 SigBit I = sigmap(b);
315 if (I != b)
316 alias_map[b] = I;
317 output_bits.insert(b);
318 }
319 }
320 }
321
322 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
323 }
324
325 dict<IdString, std::vector<IdString>> box_ports;
326 for (auto cell : box_list) {
327 log_assert(cell);
328
329 RTLIL::Module* box_module = module->design->module(cell->type);
330 log_assert(box_module);
331 log_assert(box_module->attributes.count(ID::abc9_box_id));
332
333 auto r = box_ports.insert(cell->type);
334 if (r.second) {
335 // Make carry in the last PI, and carry out the last PO
336 // since ABC requires it this way
337 IdString carry_in, carry_out;
338 for (const auto &port_name : box_module->ports) {
339 auto w = box_module->wire(port_name);
340 log_assert(w);
341 if (w->get_bool_attribute(ID::abc9_carry)) {
342 if (w->port_input) {
343 if (carry_in != IdString())
344 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
345 carry_in = port_name;
346 }
347 if (w->port_output) {
348 if (carry_out != IdString())
349 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
350 carry_out = port_name;
351 }
352 }
353 else
354 r.first->second.push_back(port_name);
355 }
356
357 if (carry_in != IdString() && carry_out == IdString())
358 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
359 if (carry_in == IdString() && carry_out != IdString())
360 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
361 if (carry_in != IdString()) {
362 r.first->second.push_back(carry_in);
363 r.first->second.push_back(carry_out);
364 }
365 }
366
367 for (auto port_name : r.first->second) {
368 auto w = box_module->wire(port_name);
369 log_assert(w);
370 auto rhs = cell->connections_.at(port_name, SigSpec());
371 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
372 if (w->port_input)
373 for (auto b : rhs) {
374 SigBit I = sigmap(b);
375 if (b == RTLIL::Sx)
376 b = State::S0;
377 else if (I != b) {
378 if (I == RTLIL::Sx)
379 alias_map[b] = State::S0;
380 else
381 alias_map[b] = I;
382 }
383 co_bits.emplace_back(b);
384 unused_bits.erase(I);
385 }
386 if (w->port_output)
387 for (const auto &b : rhs) {
388 SigBit O = sigmap(b);
389 if (O != b)
390 alias_map[O] = b;
391 ci_bits.emplace_back(b);
392 undriven_bits.erase(O);
393 }
394 }
395 }
396
397 for (auto bit : input_bits)
398 undriven_bits.erase(bit);
399 for (auto bit : output_bits)
400 unused_bits.erase(sigmap(bit));
401 for (auto bit : unused_bits)
402 undriven_bits.erase(bit);
403
404 // Make all undriven bits a primary input
405 for (auto bit : undriven_bits) {
406 input_bits.insert(bit);
407 undriven_bits.erase(bit);
408 }
409
410 struct sort_by_port_id {
411 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
412 return a.wire->port_id < b.wire->port_id ||
413 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
414 }
415 };
416 input_bits.sort(sort_by_port_id());
417 output_bits.sort(sort_by_port_id());
418
419 aig_map[State::S0] = 0;
420 aig_map[State::S1] = 1;
421
422 for (const auto &bit : input_bits) {
423 aig_m++, aig_i++;
424 log_assert(!aig_map.count(bit));
425 aig_map[bit] = 2*aig_m;
426 }
427
428 for (const auto &i : ff_bits) {
429 const Cell *cell = i.second;
430 const SigBit &q = sigmap(cell->getPort(ID::Q));
431 aig_m++, aig_i++;
432 log_assert(!aig_map.count(q));
433 aig_map[q] = 2*aig_m;
434 }
435
436 for (auto &bit : ci_bits) {
437 aig_m++, aig_i++;
438 // 1'bx may exist here due to a box output
439 // that has been padded to its full width
440 if (bit == State::Sx)
441 continue;
442 log_assert(!aig_map.count(bit));
443 aig_map[bit] = 2*aig_m;
444 }
445
446 for (auto bit : co_bits) {
447 ordered_outputs[bit] = aig_o++;
448 aig_outputs.push_back(bit2aig(bit));
449 }
450
451 for (const auto &bit : output_bits) {
452 ordered_outputs[bit] = aig_o++;
453 int aig;
454 // Unlike bit2aig() which checks aig_map first for
455 // inout/scc bits, since aig_map will point to
456 // the PI, first attempt to find the NOT/AND driver
457 // before resorting to an aig_map lookup (which
458 // could be another PO)
459 if (input_bits.count(bit)) {
460 if (not_map.count(bit)) {
461 aig = bit2aig(not_map.at(bit)) ^ 1;
462 } else if (and_map.count(bit)) {
463 auto args = and_map.at(bit);
464 int a0 = bit2aig(args.first);
465 int a1 = bit2aig(args.second);
466 aig = mkgate(a0, a1);
467 }
468 else
469 aig = aig_map.at(bit);
470 }
471 else
472 aig = bit2aig(bit);
473 aig_outputs.push_back(aig);
474 }
475
476 for (auto &i : ff_bits) {
477 const SigBit &d = i.first;
478 aig_o++;
479 aig_outputs.push_back(aig_map.at(d));
480 }
481 }
482
483 void write_aiger(std::ostream &f, bool ascii_mode)
484 {
485 int aig_obc = aig_o;
486 int aig_obcj = aig_obc;
487 int aig_obcjf = aig_obcj;
488
489 log_assert(aig_m == aig_i + aig_l + aig_a);
490 log_assert(aig_obcjf == GetSize(aig_outputs));
491
492 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
493 f << stringf("\n");
494
495 if (ascii_mode)
496 {
497 for (int i = 0; i < aig_i; i++)
498 f << stringf("%d\n", 2*i+2);
499
500 for (int i = 0; i < aig_obc; i++)
501 f << stringf("%d\n", aig_outputs.at(i));
502
503 for (int i = aig_obc; i < aig_obcj; i++)
504 f << stringf("1\n");
505
506 for (int i = aig_obc; i < aig_obcj; i++)
507 f << stringf("%d\n", aig_outputs.at(i));
508
509 for (int i = aig_obcj; i < aig_obcjf; i++)
510 f << stringf("%d\n", aig_outputs.at(i));
511
512 for (int i = 0; i < aig_a; i++)
513 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
514 }
515 else
516 {
517 for (int i = 0; i < aig_obc; i++)
518 f << stringf("%d\n", aig_outputs.at(i));
519
520 for (int i = aig_obc; i < aig_obcj; i++)
521 f << stringf("1\n");
522
523 for (int i = aig_obc; i < aig_obcj; i++)
524 f << stringf("%d\n", aig_outputs.at(i));
525
526 for (int i = aig_obcj; i < aig_obcjf; i++)
527 f << stringf("%d\n", aig_outputs.at(i));
528
529 for (int i = 0; i < aig_a; i++) {
530 int lhs = 2*(aig_i+aig_l+i)+2;
531 int rhs0 = aig_gates.at(i).first;
532 int rhs1 = aig_gates.at(i).second;
533 int delta0 = lhs - rhs0;
534 int delta1 = rhs0 - rhs1;
535 aiger_encode(f, delta0);
536 aiger_encode(f, delta1);
537 }
538 }
539
540 f << "c";
541
542 auto write_buffer = [](std::stringstream &buffer, int i32) {
543 int32_t i32_be = to_big_endian(i32);
544 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
545 };
546 std::stringstream h_buffer;
547 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
548 write_h_buffer(1);
549 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
550 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
551 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
552 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
553 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
554 write_h_buffer(input_bits.size() + ff_bits.size());
555 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
556 write_h_buffer(output_bits.size() + ff_bits.size());
557 log_debug("boxNum = %d\n", GetSize(box_list));
558 write_h_buffer(box_list.size());
559
560 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
561 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
562 };
563 std::stringstream i_buffer;
564 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
565 for (auto bit : input_bits)
566 write_i_buffer(arrival_times.at(bit, 0));
567 //std::stringstream o_buffer;
568 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
569 //for (auto bit : output_bits)
570 // write_o_buffer(0);
571
572 if (!box_list.empty() || !ff_bits.empty()) {
573 dict<IdString, std::tuple<int,int,int>> cell_cache;
574
575 int box_count = 0;
576 for (auto cell : box_list) {
577 log_assert(cell);
578
579 RTLIL::Module* box_module = module->design->module(cell->type);
580 log_assert(box_module);
581
582 IdString derived_type;
583 if (cell->parameters.empty())
584 derived_type = cell->type;
585 else
586 derived_type = box_module->derive(module->design, cell->parameters);
587 box_module = box_module->design->module(derived_type);
588 log_assert(box_module);
589
590 auto r = cell_cache.insert(derived_type);
591 auto &v = r.first->second;
592 if (r.second) {
593 int box_inputs = 0, box_outputs = 0;
594 for (auto port_name : box_module->ports) {
595 RTLIL::Wire *w = box_module->wire(port_name);
596 log_assert(w);
597 if (w->port_input)
598 box_inputs += GetSize(w);
599 if (w->port_output)
600 box_outputs += GetSize(w);
601 }
602
603 std::get<0>(v) = box_inputs;
604 std::get<1>(v) = box_outputs;
605 std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
606 }
607
608 write_h_buffer(std::get<0>(v));
609 write_h_buffer(std::get<1>(v));
610 write_h_buffer(std::get<2>(v));
611 write_h_buffer(box_count++);
612 }
613
614 std::stringstream r_buffer;
615 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
616 log_debug("flopNum = %d\n", GetSize(ff_bits));
617 write_r_buffer(ff_bits.size());
618
619 std::stringstream s_buffer;
620 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
621 write_s_buffer(ff_bits.size());
622
623 dict<SigBit, int> clk_to_mergeability;
624 for (const auto &i : ff_bits) {
625 const Cell *cell = i.second;
626 log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_)));
627
628 SigBit clock = sigmap(cell->getPort(ID::C));
629 clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size()*2+1));
630 }
631
632 for (const auto &i : ff_bits) {
633 const SigBit &d = i.first;
634 const Cell *cell = i.second;
635
636 SigBit clock = sigmap(cell->getPort(ID::C));
637 int mergeability = clk_to_mergeability.at(clock);
638 log_assert(mergeability > 0);
639 if (cell->type == ID($_DFF_N_))
640 write_r_buffer(mergeability);
641 else if (cell->type == ID($_DFF_P_))
642 write_r_buffer(mergeability+1);
643 else log_abort();
644
645 SigBit Q = sigmap(cell->getPort(ID::Q));
646 State init = init_map.at(Q, State::Sx);
647 if (init == State::S1)
648 write_s_buffer(1);
649 else if (init == State::S0)
650 write_s_buffer(0);
651 else {
652 log_assert(init == State::Sx);
653 write_s_buffer(2);
654 }
655
656 // Use arrival time from output of flop box
657 write_i_buffer(arrival_times.at(d, 0));
658 //write_o_buffer(0);
659 }
660
661 f << "r";
662 std::string buffer_str = r_buffer.str();
663 int32_t buffer_size_be = to_big_endian(buffer_str.size());
664 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
665 f.write(buffer_str.data(), buffer_str.size());
666
667 f << "s";
668 buffer_str = s_buffer.str();
669 buffer_size_be = to_big_endian(buffer_str.size());
670 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
671 f.write(buffer_str.data(), buffer_str.size());
672
673 RTLIL::Design *holes_design;
674 auto it = saved_designs.find("$abc9_holes");
675 if (it != saved_designs.end())
676 holes_design = it->second;
677 else
678 holes_design = nullptr;
679 RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
680 if (holes_module) {
681 std::stringstream a_buffer;
682 XAigerWriter writer(holes_module, false /* dff_mode */);
683 writer.write_aiger(a_buffer, false /*ascii_mode*/);
684
685 f << "a";
686 std::string buffer_str = a_buffer.str();
687 int32_t buffer_size_be = to_big_endian(buffer_str.size());
688 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
689 f.write(buffer_str.data(), buffer_str.size());
690 }
691 }
692
693 f << "h";
694 std::string buffer_str = h_buffer.str();
695 int32_t buffer_size_be = to_big_endian(buffer_str.size());
696 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
697 f.write(buffer_str.data(), buffer_str.size());
698
699 f << "i";
700 buffer_str = i_buffer.str();
701 buffer_size_be = to_big_endian(buffer_str.size());
702 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
703 f.write(buffer_str.data(), buffer_str.size());
704 //f << "o";
705 //buffer_str = o_buffer.str();
706 //buffer_size_be = to_big_endian(buffer_str.size());
707 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
708 //f.write(buffer_str.data(), buffer_str.size());
709
710 f << stringf("Generated by %s\n", yosys_version_str);
711
712 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
713 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
714 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
715 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
716 }
717
718 void write_map(std::ostream &f)
719 {
720 dict<int, string> input_lines;
721 dict<int, string> output_lines;
722
723 for (auto wire : module->wires())
724 {
725 SigSpec sig = sigmap(wire);
726
727 for (int i = 0; i < GetSize(wire); i++)
728 {
729 RTLIL::SigBit b(wire, i);
730 if (input_bits.count(b)) {
731 int a = aig_map.at(b);
732 log_assert((a & 1) == 0);
733 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, wire->start_offset+i, log_id(wire));
734 }
735
736 if (output_bits.count(b)) {
737 int o = ordered_outputs.at(b);
738 output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), wire->start_offset+i, log_id(wire));
739 continue;
740 }
741 }
742 }
743
744 input_lines.sort();
745 for (auto &it : input_lines)
746 f << it.second;
747 log_assert(input_lines.size() == input_bits.size());
748
749 int box_count = 0;
750 for (auto cell : box_list)
751 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
752
753 output_lines.sort();
754 for (auto &it : output_lines)
755 f << it.second;
756 log_assert(output_lines.size() == output_bits.size());
757 }
758 };
759
760 struct XAigerBackend : public Backend {
761 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
762 void help() YS_OVERRIDE
763 {
764 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
765 log("\n");
766 log(" write_xaiger [options] [filename]\n");
767 log("\n");
768 log("Write the top module (according to the (* top *) attribute or if only one module\n");
769 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, (optionally\n");
770 log("$_DFF_N_, $_DFF_P_), or non (* abc9_box *) cells will be converted into psuedo-\n");
771 log("inputs and pseudo-outputs. Whitebox contents will be taken from the equivalent\n");
772 log("module in the '$abc9_holes' design, if it exists.\n");
773 log("\n");
774 log(" -ascii\n");
775 log(" write ASCII version of AIGER format\n");
776 log("\n");
777 log(" -map <filename>\n");
778 log(" write an extra file with port and box symbols\n");
779 log("\n");
780 log(" -dff\n");
781 log(" write $_DFF_[NP]_ cells\n");
782 log("\n");
783 }
784 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
785 {
786 bool ascii_mode = false, dff_mode = false;
787 std::string map_filename;
788
789 log_header(design, "Executing XAIGER backend.\n");
790
791 size_t argidx;
792 for (argidx = 1; argidx < args.size(); argidx++)
793 {
794 if (args[argidx] == "-ascii") {
795 ascii_mode = true;
796 continue;
797 }
798 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
799 map_filename = args[++argidx];
800 continue;
801 }
802 if (args[argidx] == "-dff") {
803 dff_mode = true;
804 continue;
805 }
806 break;
807 }
808 extra_args(f, filename, args, argidx, !ascii_mode);
809
810 Module *top_module = design->top_module();
811
812 if (top_module == nullptr)
813 log_error("Can't find top module in current design!\n");
814
815 if (!design->selected_whole_module(top_module))
816 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
817
818 if (!top_module->processes.empty())
819 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
820 if (!top_module->memories.empty())
821 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
822
823 XAigerWriter writer(top_module, dff_mode);
824 writer.write_aiger(*f, ascii_mode);
825
826 if (!map_filename.empty()) {
827 std::ofstream mapf;
828 mapf.open(map_filename.c_str(), std::ofstream::trunc);
829 if (mapf.fail())
830 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
831 writer.write_map(mapf);
832 }
833 }
834 } XAigerBackend;
835
836 PRIVATE_NAMESPACE_END