projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge pull request #2059 from boqwxp/logger-vector-to-dict
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
51
52 USING_YOSYS_NAMESPACE
53 PRIVATE_NAMESPACE_BEGIN
54
55 inline int32_t to_big_endian(int32_t i32) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 return bswap32(i32);
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
59 return i32;
60 #else
61 #error "Unknown endianness"
62 #endif
63 }
64
65 void aiger_encode(std::ostream &f, int x)
66 {
67 log_assert(x >= 0);
68
69 while (x & ~0x7f) {
70 f.put((x & 0x7f) | 0x80);
71 x = x >> 7;
72 }
73
74 f.put(x);
75 }
76
77 struct XAigerWriter
78 {
79 Design *design;
80 Module *module;
81 SigMap sigmap;
82
83 dict<SigBit, State> init_map;
84 pool<SigBit> input_bits, output_bits;
85 dict<SigBit, SigBit> not_map, alias_map;
86 dict<SigBit, pair<SigBit, SigBit>> and_map;
87 vector<SigBit> ci_bits, co_bits;
88 dict<SigBit, Cell*> ff_bits;
89 dict<SigBit, float> arrival_times;
90
91 vector<pair<int, int>> aig_gates;
92 vector<int> aig_outputs;
93 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
94
95 dict<SigBit, int> aig_map;
96 dict<SigBit, int> ordered_outputs;
97
98 vector<Cell*> box_list;
99
100 int mkgate(int a0, int a1)
101 {
102 aig_m++, aig_a++;
103 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
104 return 2*aig_m;
105 }
106
107 int bit2aig(SigBit bit)
108 {
109 auto it = aig_map.find(bit);
110 if (it != aig_map.end()) {
111 log_assert(it->second >= 0);
112 return it->second;
113 }
114
115 // NB: Cannot use iterator returned from aig_map.insert()
116 // since this function is called recursively
117
118 int a = -1;
119 if (not_map.count(bit)) {
120 a = bit2aig(not_map.at(bit)) ^ 1;
121 } else
122 if (and_map.count(bit)) {
123 auto args = and_map.at(bit);
124 int a0 = bit2aig(args.first);
125 int a1 = bit2aig(args.second);
126 a = mkgate(a0, a1);
127 } else
128 if (alias_map.count(bit)) {
129 a = bit2aig(alias_map.at(bit));
130 }
131
132 if (bit == State::Sx || bit == State::Sz) {
133 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
134 a = aig_map.at(State::S0);
135 }
136
137 log_assert(a >= 0);
138 aig_map[bit] = a;
139 return a;
140 }
141
142 XAigerWriter(Module *module, bool dff_mode) : design(module->design), module(module), sigmap(module)
143 {
144 pool<SigBit> undriven_bits;
145 pool<SigBit> unused_bits;
146
147 // promote public wires
148 for (auto wire : module->wires())
149 if (wire->name[0] == '\\')
150 sigmap.add(wire);
151
152 // promote input wires
153 for (auto wire : module->wires())
154 if (wire->port_input)
155 sigmap.add(wire);
156
157 // promote keep wires
158 for (auto wire : module->wires())
159 if (wire->get_bool_attribute(ID::keep))
160 sigmap.add(wire);
161
162 for (auto wire : module->wires()) {
163 auto it = wire->attributes.find(ID::init);
164 for (int i = 0; i < GetSize(wire); i++)
165 {
166 SigBit wirebit(wire, i);
167 SigBit bit = sigmap(wirebit);
168
169 if (bit.wire == nullptr) {
170 if (wire->port_output) {
171 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
172 output_bits.insert(wirebit);
173 }
174 continue;
175 }
176
177 undriven_bits.insert(bit);
178 unused_bits.insert(bit);
179
180 bool keep = wire->get_bool_attribute(ID::abc9_keep);
181 if (wire->port_input || keep)
182 input_bits.insert(bit);
183
184 keep = keep || wire->get_bool_attribute(ID::keep);
185 if (wire->port_output || keep) {
186 if (bit != wirebit)
187 alias_map[wirebit] = bit;
188 output_bits.insert(wirebit);
189 }
190
191 if (it != wire->attributes.end()) {
192 auto s = it->second[i];
193 if (s != State::Sx) {
194 auto r = init_map.insert(std::make_pair(bit, it->second[i]));
195 if (!r.second && r.first->second != it->second[i])
196 log_error("Bit '%s' has a conflicting (* init *) value.\n", log_signal(bit));
197 }
198 }
199 }
200 }
201
202 TimingInfo timing;
203
204 for (auto cell : module->cells()) {
205 if (!cell->has_keep_attr()) {
206 if (cell->type == ID($_NOT_))
207 {
208 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
209 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
210 unused_bits.erase(A);
211 undriven_bits.erase(Y);
212 not_map[Y] = A;
213 continue;
214 }
215
216 if (cell->type == ID($_AND_))
217 {
218 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
219 SigBit B = sigmap(cell->getPort(ID::B).as_bit());
220 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
221 unused_bits.erase(A);
222 unused_bits.erase(B);
223 undriven_bits.erase(Y);
224 and_map[Y] = make_pair(A, B);
225 continue;
226 }
227
228 if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
229 {
230 SigBit D = sigmap(cell->getPort(ID::D).as_bit());
231 SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
232 unused_bits.erase(D);
233 undriven_bits.erase(Q);
234 alias_map[Q] = D;
235 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
236 log_assert(r.second);
237 continue;
238 }
239
240 if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
241 continue;
242 }
243
244 RTLIL::Module* inst_module = design->module(cell->type);
245 if (inst_module && inst_module->get_blackbox_attribute()) {
246 bool abc9_flop = false;
247
248 auto it = cell->attributes.find(ID::abc9_box_seq);
249 if (it != cell->attributes.end()) {
250 log_assert(!cell->has_keep_attr());
251 int abc9_box_seq = it->second.as_int();
252 if (GetSize(box_list) <= abc9_box_seq)
253 box_list.resize(abc9_box_seq+1);
254 box_list[abc9_box_seq] = cell;
255 // Only flop boxes may have arrival times
256 // (all others are combinatorial)
257 log_assert(cell->parameters.empty());
258 abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
259 if (!abc9_flop)
260 continue;
261 }
262
263 if (!cell->parameters.empty()) {
264 auto derived_type = inst_module->derive(design, cell->parameters);
265 inst_module = design->module(derived_type);
266 log_assert(inst_module);
267 log_assert(inst_module->get_blackbox_attribute());
268 }
269
270 if (!timing.count(inst_module->name))
271 timing.setup_module(inst_module);
272 auto &t = timing.at(inst_module->name).arrival;
273 for (const auto &conn : cell->connections()) {
274 auto port_wire = inst_module->wire(conn.first);
275 if (!port_wire->port_output)
276 continue;
277
278 for (int i = 0; i < GetSize(conn.second); i++) {
279 auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
280 if (d == 0)
281 continue;
282
283 #ifndef NDEBUG
284 if (ys_debug(1)) {
285 static std::set<std::tuple<IdString,IdString,int>> seen;
286 if (seen.emplace(inst_module->name, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
287 log_id(cell->type), log_id(conn.first), i, d);
288 }
289 #endif
290 arrival_times[conn.second[i]] = d;
291 }
292 }
293
294 if (abc9_flop)
295 continue;
296 }
297
298 bool cell_known = inst_module || cell->known();
299 for (const auto &c : cell->connections()) {
300 if (c.second.is_fully_const()) continue;
301 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
302 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
303 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
304 if (!is_input && !is_output)
305 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
306
307 if (is_input)
308 for (auto b : c.second) {
309 Wire *w = b.wire;
310 if (!w) continue;
311 // Do not add as PO if bit is already a PI
312 if (input_bits.count(b))
313 continue;
314 if (!w->port_output || !cell_known) {
315 SigBit I = sigmap(b);
316 if (I != b)
317 alias_map[b] = I;
318 output_bits.insert(b);
319 }
320 }
321 }
322
323 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
324 }
325
326 dict<IdString, std::vector<IdString>> box_ports;
327 for (auto cell : box_list) {
328 log_assert(cell);
329
330 RTLIL::Module* box_module = design->module(cell->type);
331 log_assert(box_module);
332 log_assert(box_module->has_attribute(ID::abc9_box_id));
333
334 auto r = box_ports.insert(cell->type);
335 if (r.second) {
336 // Make carry in the last PI, and carry out the last PO
337 // since ABC requires it this way
338 IdString carry_in, carry_out;
339 for (const auto &port_name : box_module->ports) {
340 auto w = box_module->wire(port_name);
341 log_assert(w);
342 if (w->get_bool_attribute(ID::abc9_carry)) {
343 if (w->port_input) {
344 if (carry_in != IdString())
345 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
346 carry_in = port_name;
347 }
348 if (w->port_output) {
349 if (carry_out != IdString())
350 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
351 carry_out = port_name;
352 }
353 }
354 else
355 r.first->second.push_back(port_name);
356 }
357
358 if (carry_in != IdString() && carry_out == IdString())
359 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
360 if (carry_in == IdString() && carry_out != IdString())
361 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
362 if (carry_in != IdString()) {
363 r.first->second.push_back(carry_in);
364 r.first->second.push_back(carry_out);
365 }
366 }
367
368 for (auto port_name : r.first->second) {
369 auto w = box_module->wire(port_name);
370 log_assert(w);
371 auto rhs = cell->connections_.at(port_name, SigSpec());
372 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
373 if (w->port_input)
374 for (auto b : rhs) {
375 SigBit I = sigmap(b);
376 if (b == RTLIL::Sx)
377 b = State::S0;
378 else if (I != b) {
379 if (I == RTLIL::Sx)
380 alias_map[b] = State::S0;
381 else
382 alias_map[b] = I;
383 }
384 co_bits.emplace_back(b);
385 unused_bits.erase(I);
386 }
387 if (w->port_output)
388 for (const auto &b : rhs) {
389 SigBit O = sigmap(b);
390 if (O != b)
391 alias_map[O] = b;
392 ci_bits.emplace_back(b);
393 undriven_bits.erase(O);
394 }
395 }
396 }
397
398 for (auto bit : input_bits)
399 undriven_bits.erase(bit);
400 for (auto bit : output_bits)
401 unused_bits.erase(sigmap(bit));
402 for (auto bit : unused_bits)
403 undriven_bits.erase(bit);
404
405 // Make all undriven bits a primary input
406 for (auto bit : undriven_bits) {
407 input_bits.insert(bit);
408 undriven_bits.erase(bit);
409 }
410
411 struct sort_by_port_id {
412 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
413 return a.wire->port_id < b.wire->port_id ||
414 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
415 }
416 };
417 input_bits.sort(sort_by_port_id());
418 output_bits.sort(sort_by_port_id());
419
420 aig_map[State::S0] = 0;
421 aig_map[State::S1] = 1;
422
423 for (const auto &bit : input_bits) {
424 aig_m++, aig_i++;
425 log_assert(!aig_map.count(bit));
426 aig_map[bit] = 2*aig_m;
427 }
428
429 for (const auto &i : ff_bits) {
430 const Cell *cell = i.second;
431 const SigBit &q = sigmap(cell->getPort(ID::Q));
432 aig_m++, aig_i++;
433 log_assert(!aig_map.count(q));
434 aig_map[q] = 2*aig_m;
435 }
436
437 for (auto &bit : ci_bits) {
438 aig_m++, aig_i++;
439 // 1'bx may exist here due to a box output
440 // that has been padded to its full width
441 if (bit == State::Sx)
442 continue;
443 log_assert(!aig_map.count(bit));
444 aig_map[bit] = 2*aig_m;
445 }
446
447 for (auto bit : co_bits) {
448 ordered_outputs[bit] = aig_o++;
449 aig_outputs.push_back(bit2aig(bit));
450 }
451
452 for (const auto &bit : output_bits) {
453 ordered_outputs[bit] = aig_o++;
454 int aig;
455 // Unlike bit2aig() which checks aig_map first for
456 // inout/scc bits, since aig_map will point to
457 // the PI, first attempt to find the NOT/AND driver
458 // before resorting to an aig_map lookup (which
459 // could be another PO)
460 if (input_bits.count(bit)) {
461 if (not_map.count(bit)) {
462 aig = bit2aig(not_map.at(bit)) ^ 1;
463 } else if (and_map.count(bit)) {
464 auto args = and_map.at(bit);
465 int a0 = bit2aig(args.first);
466 int a1 = bit2aig(args.second);
467 aig = mkgate(a0, a1);
468 }
469 else
470 aig = aig_map.at(bit);
471 }
472 else
473 aig = bit2aig(bit);
474 aig_outputs.push_back(aig);
475 }
476
477 for (auto &i : ff_bits) {
478 const SigBit &d = i.first;
479 aig_o++;
480 aig_outputs.push_back(aig_map.at(d));
481 }
482 }
483
484 void write_aiger(std::ostream &f, bool ascii_mode)
485 {
486 int aig_obc = aig_o;
487 int aig_obcj = aig_obc;
488 int aig_obcjf = aig_obcj;
489
490 log_assert(aig_m == aig_i + aig_l + aig_a);
491 log_assert(aig_obcjf == GetSize(aig_outputs));
492
493 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
494 f << stringf("\n");
495
496 if (ascii_mode)
497 {
498 for (int i = 0; i < aig_i; i++)
499 f << stringf("%d\n", 2*i+2);
500
501 for (int i = 0; i < aig_obc; i++)
502 f << stringf("%d\n", aig_outputs.at(i));
503
504 for (int i = aig_obc; i < aig_obcj; i++)
505 f << stringf("1\n");
506
507 for (int i = aig_obc; i < aig_obcj; i++)
508 f << stringf("%d\n", aig_outputs.at(i));
509
510 for (int i = aig_obcj; i < aig_obcjf; i++)
511 f << stringf("%d\n", aig_outputs.at(i));
512
513 for (int i = 0; i < aig_a; i++)
514 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
515 }
516 else
517 {
518 for (int i = 0; i < aig_obc; i++)
519 f << stringf("%d\n", aig_outputs.at(i));
520
521 for (int i = aig_obc; i < aig_obcj; i++)
522 f << stringf("1\n");
523
524 for (int i = aig_obc; i < aig_obcj; i++)
525 f << stringf("%d\n", aig_outputs.at(i));
526
527 for (int i = aig_obcj; i < aig_obcjf; i++)
528 f << stringf("%d\n", aig_outputs.at(i));
529
530 for (int i = 0; i < aig_a; i++) {
531 int lhs = 2*(aig_i+aig_l+i)+2;
532 int rhs0 = aig_gates.at(i).first;
533 int rhs1 = aig_gates.at(i).second;
534 int delta0 = lhs - rhs0;
535 int delta1 = rhs0 - rhs1;
536 aiger_encode(f, delta0);
537 aiger_encode(f, delta1);
538 }
539 }
540
541 f << "c";
542
543 auto write_buffer = [](std::stringstream &buffer, int i32) {
544 int32_t i32_be = to_big_endian(i32);
545 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
546 };
547 std::stringstream h_buffer;
548 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
549 write_h_buffer(1);
550 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
551 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
552 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
553 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
554 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
555 write_h_buffer(input_bits.size() + ff_bits.size());
556 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
557 write_h_buffer(output_bits.size() + ff_bits.size());
558 log_debug("boxNum = %d\n", GetSize(box_list));
559 write_h_buffer(box_list.size());
560
561 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
562 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
563 };
564 std::stringstream i_buffer;
565 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
566 for (auto bit : input_bits)
567 write_i_buffer(arrival_times.at(bit, 0));
568 //std::stringstream o_buffer;
569 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
570 //for (auto bit : output_bits)
571 // write_o_buffer(0);
572
573 if (!box_list.empty() || !ff_bits.empty()) {
574 dict<IdString, std::tuple<int,int,int>> cell_cache;
575
576 int box_count = 0;
577 for (auto cell : box_list) {
578 log_assert(cell);
579 log_assert(cell->parameters.empty());
580
581 auto r = cell_cache.insert(cell->type);
582 auto &v = r.first->second;
583 if (r.second) {
584 RTLIL::Module* box_module = design->module(cell->type);
585 log_assert(box_module);
586
587 int box_inputs = 0, box_outputs = 0;
588 for (auto port_name : box_module->ports) {
589 RTLIL::Wire *w = box_module->wire(port_name);
590 log_assert(w);
591 if (w->port_input)
592 box_inputs += GetSize(w);
593 if (w->port_output)
594 box_outputs += GetSize(w);
595 }
596
597 std::get<0>(v) = box_inputs;
598 std::get<1>(v) = box_outputs;
599 std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
600 }
601
602 write_h_buffer(std::get<0>(v));
603 write_h_buffer(std::get<1>(v));
604 write_h_buffer(std::get<2>(v));
605 write_h_buffer(box_count++);
606 }
607
608 std::stringstream r_buffer;
609 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
610 log_debug("flopNum = %d\n", GetSize(ff_bits));
611 write_r_buffer(ff_bits.size());
612
613 std::stringstream s_buffer;
614 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
615 write_s_buffer(ff_bits.size());
616
617 dict<SigSpec, int> clk_to_mergeability;
618 for (const auto &i : ff_bits) {
619 const SigBit &d = i.first;
620 const Cell *cell = i.second;
621
622 SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
623 auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1));
624 int mergeability = r.first->second;
625 log_assert(mergeability > 0);
626 write_r_buffer(mergeability);
627
628 SigBit Q = sigmap(cell->getPort(ID::Q));
629 State init = init_map.at(Q, State::Sx);
630 log_debug("Cell '%s' (type %s) has (* init *) value '%s'.\n", log_id(cell), log_id(cell->type), log_signal(init));
631 if (init == State::S1)
632 write_s_buffer(1);
633 else if (init == State::S0)
634 write_s_buffer(0);
635 else {
636 log_assert(init == State::Sx);
637 write_s_buffer(2);
638 }
639
640 // Use arrival time from output of flop box
641 write_i_buffer(arrival_times.at(d, 0));
642 //write_o_buffer(0);
643 }
644
645 f << "r";
646 std::string buffer_str = r_buffer.str();
647 int32_t buffer_size_be = to_big_endian(buffer_str.size());
648 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
649 f.write(buffer_str.data(), buffer_str.size());
650
651 f << "s";
652 buffer_str = s_buffer.str();
653 buffer_size_be = to_big_endian(buffer_str.size());
654 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
655 f.write(buffer_str.data(), buffer_str.size());
656
657 RTLIL::Design *holes_design;
658 auto it = saved_designs.find("$abc9_holes");
659 if (it != saved_designs.end())
660 holes_design = it->second;
661 else
662 holes_design = nullptr;
663 RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
664 if (holes_module) {
665 std::stringstream a_buffer;
666 XAigerWriter writer(holes_module, false /* dff_mode */);
667 writer.write_aiger(a_buffer, false /*ascii_mode*/);
668
669 f << "a";
670 std::string buffer_str = a_buffer.str();
671 int32_t buffer_size_be = to_big_endian(buffer_str.size());
672 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
673 f.write(buffer_str.data(), buffer_str.size());
674 }
675 }
676
677 f << "h";
678 std::string buffer_str = h_buffer.str();
679 int32_t buffer_size_be = to_big_endian(buffer_str.size());
680 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
681 f.write(buffer_str.data(), buffer_str.size());
682
683 f << "i";
684 buffer_str = i_buffer.str();
685 buffer_size_be = to_big_endian(buffer_str.size());
686 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
687 f.write(buffer_str.data(), buffer_str.size());
688 //f << "o";
689 //buffer_str = o_buffer.str();
690 //buffer_size_be = to_big_endian(buffer_str.size());
691 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
692 //f.write(buffer_str.data(), buffer_str.size());
693
694 f << stringf("Generated by %s\n", yosys_version_str);
695
696 design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
697 design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
698 design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
699 design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
700 }
701
702 void write_map(std::ostream &f)
703 {
704 dict<int, string> input_lines;
705 dict<int, string> output_lines;
706
707 for (auto wire : module->wires())
708 {
709 SigSpec sig = sigmap(wire);
710
711 for (int i = 0; i < GetSize(wire); i++)
712 {
713 RTLIL::SigBit b(wire, i);
714 if (input_bits.count(b)) {
715 int a = aig_map.at(b);
716 log_assert((a & 1) == 0);
717 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, wire->start_offset+i, log_id(wire));
718 }
719
720 if (output_bits.count(b)) {
721 int o = ordered_outputs.at(b);
722 output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), wire->start_offset+i, log_id(wire));
723 continue;
724 }
725 }
726 }
727
728 input_lines.sort();
729 for (auto &it : input_lines)
730 f << it.second;
731 log_assert(input_lines.size() == input_bits.size());
732
733 int box_count = 0;
734 for (auto cell : box_list)
735 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
736
737 output_lines.sort();
738 for (auto &it : output_lines)
739 f << it.second;
740 log_assert(output_lines.size() == output_bits.size());
741 }
742 };
743
744 struct XAigerBackend : public Backend {
745 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
746 void help() YS_OVERRIDE
747 {
748 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
749 log("\n");
750 log(" write_xaiger [options] [filename]\n");
751 log("\n");
752 log("Write the top module (according to the (* top *) attribute or if only one module\n");
753 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, (optionally\n");
754 log("$_DFF_N_, $_DFF_P_), or non (* abc9_box *) cells will be converted into psuedo-\n");
755 log("inputs and pseudo-outputs. Whitebox contents will be taken from the equivalent\n");
756 log("module in the '$abc9_holes' design, if it exists.\n");
757 log("\n");
758 log(" -ascii\n");
759 log(" write ASCII version of AIGER format\n");
760 log("\n");
761 log(" -map <filename>\n");
762 log(" write an extra file with port and box symbols\n");
763 log("\n");
764 log(" -dff\n");
765 log(" write $_DFF_[NP]_ cells\n");
766 log("\n");
767 }
768 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
769 {
770 bool ascii_mode = false, dff_mode = false;
771 std::string map_filename;
772
773 log_header(design, "Executing XAIGER backend.\n");
774
775 size_t argidx;
776 for (argidx = 1; argidx < args.size(); argidx++)
777 {
778 if (args[argidx] == "-ascii") {
779 ascii_mode = true;
780 continue;
781 }
782 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
783 map_filename = args[++argidx];
784 continue;
785 }
786 if (args[argidx] == "-dff") {
787 dff_mode = true;
788 continue;
789 }
790 break;
791 }
792 extra_args(f, filename, args, argidx, !ascii_mode);
793
794 Module *top_module = design->top_module();
795
796 if (top_module == nullptr)
797 log_error("Can't find top module in current design!\n");
798
799 if (!design->selected_whole_module(top_module))
800 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
801
802 if (!top_module->processes.empty())
803 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
804 if (!top_module->memories.empty())
805 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
806
807 XAigerWriter writer(top_module, dff_mode);
808 writer.write_aiger(*f, ascii_mode);
809
810 if (!map_filename.empty()) {
811 std::ofstream mapf;
812 mapf.open(map_filename.c_str(), std::ofstream::trunc);
813 if (mapf.fail())
814 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
815 writer.write_map(mapf);
816 }
817 }
818 } XAigerBackend;
819
820 PRIVATE_NAMESPACE_END