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Fix padding, remove CIs from undriven_bits before erasing undriven POs
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/yosys.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/utils.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 void aiger_encode(std::ostream &f, int x)
30 {
31 log_assert(x >= 0);
32
33 while (x & ~0x7f) {
34 f.put((x & 0x7f) | 0x80);
35 x = x >> 7;
36 }
37
38 f.put(x);
39 }
40
41 struct XAigerWriter
42 {
43 Module *module;
44 bool zinit_mode;
45 SigMap sigmap;
46
47 dict<SigBit, bool> init_map;
48 pool<SigBit> input_bits, output_bits;
49 dict<SigBit, SigBit> not_map, ff_map, alias_map;
50 dict<SigBit, pair<SigBit, SigBit>> and_map;
51 //pool<SigBit> initstate_bits;
52 vector<std::pair<SigBit,int>> ci_bits, co_bits;
53
54 vector<pair<int, int>> aig_gates;
55 vector<int> aig_latchin, aig_latchinit, aig_outputs;
56 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
57
58 dict<SigBit, int> aig_map;
59 dict<SigBit, int> ordered_outputs;
60 dict<SigBit, int> ordered_latches;
61
62 vector<Cell*> box_list;
63
64 //dict<SigBit, int> init_inputs;
65 //int initstate_ff = 0;
66
67 int mkgate(int a0, int a1)
68 {
69 aig_m++, aig_a++;
70 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
71 return 2*aig_m;
72 }
73
74 int bit2aig(SigBit bit)
75 {
76 if (aig_map.count(bit) == 0)
77 {
78 aig_map[bit] = -1;
79
80 //if (initstate_bits.count(bit)) {
81 // log_assert(initstate_ff > 0);
82 // aig_map[bit] = initstate_ff;
83 //} else
84 if (not_map.count(bit)) {
85 int a = bit2aig(not_map.at(bit)) ^ 1;
86 aig_map[bit] = a;
87 } else
88 if (and_map.count(bit)) {
89 auto args = and_map.at(bit);
90 int a0 = bit2aig(args.first);
91 int a1 = bit2aig(args.second);
92 aig_map[bit] = mkgate(a0, a1);
93 } else
94 if (alias_map.count(bit)) {
95 aig_map[bit] = bit2aig(alias_map.at(bit));
96 }
97
98 if (bit == State::Sx || bit == State::Sz)
99 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
100 }
101
102 log_assert(aig_map.at(bit) >= 0);
103 return aig_map.at(bit);
104 }
105
106 XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
107 {
108 pool<SigBit> undriven_bits;
109 pool<SigBit> unused_bits;
110
111 // promote public wires
112 for (auto wire : module->wires())
113 if (wire->name[0] == '\\')
114 sigmap.add(wire);
115
116 // promote input wires
117 for (auto wire : module->wires())
118 if (wire->port_input)
119 sigmap.add(wire);
120
121 // promote output wires
122 for (auto wire : module->wires())
123 if (wire->port_output)
124 sigmap.add(wire);
125
126 for (auto wire : module->wires())
127 {
128 if (wire->attributes.count("\\init")) {
129 SigSpec initsig = sigmap(wire);
130 Const initval = wire->attributes.at("\\init");
131 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
132 if (initval[i] == State::S0 || initval[i] == State::S1)
133 init_map[initsig[i]] = initval[i] == State::S1;
134 }
135
136 bool keep = wire->attributes.count("\\keep");
137
138 for (int i = 0; i < GetSize(wire); i++)
139 {
140 SigBit wirebit(wire, i);
141 SigBit bit = sigmap(wirebit);
142
143 if (bit.wire == nullptr) {
144 if (wire->port_output) {
145 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
146 output_bits.insert(wirebit);
147 }
148 continue;
149 }
150
151 undriven_bits.insert(bit);
152 unused_bits.insert(bit);
153
154 if (wire->port_input)
155 input_bits.insert(bit);
156 else if (keep)
157 input_bits.insert(wirebit);
158
159 if (wire->port_output || keep) {
160 if (bit != wirebit)
161 alias_map[wirebit] = bit;
162 output_bits.insert(wirebit);
163 }
164 }
165 }
166
167 for (auto bit : input_bits)
168 undriven_bits.erase(bit);
169
170 for (auto bit : output_bits)
171 if (!bit.wire->port_input)
172 unused_bits.erase(bit);
173
174 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
175 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
176 bool abc_box_seen = false;
177
178 for (auto cell : module->cells())
179 {
180 RTLIL::Module* inst_module = module->design->module(cell->type);
181 bool known_type = yosys_celltypes.cell_known(cell->type);
182
183 if (!holes_mode) {
184 toposort.node(cell->name);
185 for (const auto &conn : cell->connections())
186 {
187 if (!cell->type.in("$_NOT_", "$_AND_")) {
188 if (known_type) {
189 if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
190 continue;
191 if (cell->type == "$memrd" && conn.first == "\\DATA")
192 continue;
193 }
194
195 if (inst_module) {
196 RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
197 log_assert(inst_module_port);
198
199 if (inst_module_port->attributes.count("\\abc_flop_q"))
200 continue;
201 }
202 }
203
204 if (cell->input(conn.first)) {
205 // Ignore inout for the sake of topographical ordering
206 if (cell->output(conn.first)) continue;
207 for (auto bit : sigmap(conn.second))
208 bit_users[bit].insert(cell->name);
209 }
210
211 if (cell->output(conn.first))
212 for (auto bit : sigmap(conn.second))
213 bit_drivers[bit].insert(cell->name);
214 }
215 }
216
217 if (cell->type == "$_NOT_")
218 {
219 SigBit A = sigmap(cell->getPort("\\A").as_bit());
220 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
221 unused_bits.erase(A);
222 undriven_bits.erase(Y);
223 not_map[Y] = A;
224 continue;
225 }
226
227 //if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
228 //{
229 // SigBit D = sigmap(cell->getPort("\\D").as_bit());
230 // SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
231 // unused_bits.erase(D);
232 // undriven_bits.erase(Q);
233 // ff_map[Q] = D;
234 // continue;
235 //}
236
237 if (cell->type == "$_AND_")
238 {
239 SigBit A = sigmap(cell->getPort("\\A").as_bit());
240 SigBit B = sigmap(cell->getPort("\\B").as_bit());
241 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
242 unused_bits.erase(A);
243 unused_bits.erase(B);
244 undriven_bits.erase(Y);
245 and_map[Y] = make_pair(A, B);
246 continue;
247 }
248
249 //if (cell->type == "$initstate")
250 //{
251 // SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
252 // undriven_bits.erase(Y);
253 // initstate_bits.insert(Y);
254 // continue;
255 //}
256
257 if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
258 abc_box_seen = true;
259 }
260 else {
261 for (const auto &c : cell->connections()) {
262 if (c.second.is_fully_const()) continue;
263 for (auto b : c.second.bits()) {
264 Wire *w = b.wire;
265 if (!w) continue;
266 auto is_input = cell->input(c.first);
267 auto is_output = cell->output(c.first);
268 log_assert(is_input || is_output);
269 if (is_input) {
270 if (!w->port_input) {
271 SigBit I = sigmap(b);
272 if (I != b)
273 alias_map[b] = I;
274 output_bits.insert(b);
275 unused_bits.erase(b);
276 }
277 }
278 if (is_output) {
279 SigBit O = sigmap(b);
280 input_bits.insert(O);
281 undriven_bits.erase(O);
282 }
283 }
284 }
285 }
286
287 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
288 }
289
290 if (abc_box_seen) {
291 for (auto &it : bit_users)
292 if (bit_drivers.count(it.first))
293 for (auto driver_cell : bit_drivers.at(it.first))
294 for (auto user_cell : it.second)
295 toposort.edge(driver_cell, user_cell);
296
297 toposort.sort();
298 for (auto cell_name : toposort.sorted) {
299 RTLIL::Cell *cell = module->cell(cell_name);
300 RTLIL::Module* box_module = module->design->module(cell->type);
301 if (!box_module || !box_module->attributes.count("\\abc_box_id"))
302 continue;
303
304 // Fully pad all unused input connections of this box cell with S0
305 // Fully pad all undriven output connections of this box cell with anonymous wires
306 for (const auto w : box_module->wires()) {
307 if (w->port_input) {
308 auto it = cell->connections_.find(w->name);
309 if (it != cell->connections_.end()) {
310 if (GetSize(it->second) < GetSize(w))
311 it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second)));
312 }
313 else
314 cell->connections_[w->name] = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
315 }
316 if (w->port_output) {
317 auto it = cell->connections_.find(w->name);
318 if (it != cell->connections_.end()) {
319 if (GetSize(it->second) < GetSize(w))
320 it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
321 }
322 else
323 cell->connections_[w->name] = module->addWire(NEW_ID, GetSize(w));
324 }
325 }
326
327 // Box ordering is alphabetical
328 cell->connections_.sort(RTLIL::sort_by_id_str());
329 for (const auto &c : cell->connections()) {
330 for (auto b : c.second.bits()) {
331 auto is_input = cell->input(c.first);
332 auto is_output = cell->output(c.first);
333 log_assert(is_input || is_output);
334 if (is_input) {
335 SigBit I = sigmap(b);
336 if (I != b)
337 alias_map[b] = I;
338 co_bits.emplace_back(b, 0);
339 }
340 if (is_output) {
341 SigBit O = sigmap(b);
342 ci_bits.emplace_back(O, 0);
343 }
344 }
345 }
346
347 box_list.emplace_back(cell);
348 }
349
350 // TODO: Free memory from toposort, bit_drivers, bit_users
351 }
352
353 for (auto bit : input_bits) {
354 RTLIL::Wire *wire = bit.wire;
355 // If encountering an inout port, or a keep-ed wire, then create a new wire
356 // with $inout.out suffix, make it a PO driven by the existing inout, and
357 // inherit existing inout's drivers
358 if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
359 || wire->attributes.count("\\keep")) {
360 log_assert(input_bits.count(bit) && output_bits.count(bit));
361 RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
362 if (!new_wire)
363 new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
364 SigBit new_bit(new_wire, bit.offset);
365 module->connect(new_bit, bit);
366 if (not_map.count(bit))
367 not_map[new_bit] = not_map.at(bit);
368 else if (and_map.count(bit))
369 and_map[new_bit] = and_map.at(bit);
370 else if (alias_map.count(bit))
371 alias_map[new_bit] = alias_map.at(bit);
372 else
373 //log_abort();
374 alias_map[new_bit] = bit;
375 output_bits.erase(bit);
376 output_bits.insert(new_bit);
377 }
378 }
379
380 // Do some CI/CO post-processing:
381 // CIs cannot be undriven
382 for (const auto &c : ci_bits)
383 undriven_bits.erase(c.first);
384 // Erase all POs that are undriven
385 if (!holes_mode)
386 for (auto bit : undriven_bits)
387 output_bits.erase(bit);
388 for (auto bit : unused_bits)
389 undriven_bits.erase(bit);
390
391 if (!undriven_bits.empty() && !holes_mode) {
392 undriven_bits.sort();
393 for (auto bit : undriven_bits) {
394 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
395 input_bits.insert(bit);
396 }
397 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
398 }
399
400 init_map.sort();
401 input_bits.sort();
402 output_bits.sort();
403 not_map.sort();
404 ff_map.sort();
405 and_map.sort();
406
407 aig_map[State::S0] = 0;
408 aig_map[State::S1] = 1;
409
410 for (auto bit : input_bits) {
411 aig_m++, aig_i++;
412 aig_map[bit] = 2*aig_m;
413 }
414
415 for (auto &c : ci_bits) {
416 aig_m++, aig_i++;
417 c.second = 2*aig_m;
418 aig_map[c.first] = c.second;
419 }
420
421 if (imode && input_bits.empty()) {
422 aig_m++, aig_i++;
423 }
424
425 //if (zinit_mode)
426 //{
427 // for (auto it : ff_map) {
428 // if (init_map.count(it.first))
429 // continue;
430 // aig_m++, aig_i++;
431 // init_inputs[it.first] = 2*aig_m;
432 // }
433 //}
434
435 for (auto it : ff_map) {
436 aig_m++, aig_l++;
437 aig_map[it.first] = 2*aig_m;
438 ordered_latches[it.first] = aig_l-1;
439 if (init_map.count(it.first) == 0)
440 aig_latchinit.push_back(2);
441 else
442 aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
443 }
444
445 //if (!initstate_bits.empty() || !init_inputs.empty()) {
446 // aig_m++, aig_l++;
447 // initstate_ff = 2*aig_m+1;
448 // aig_latchinit.push_back(0);
449 //}
450
451 //if (zinit_mode)
452 //{
453 // for (auto it : ff_map)
454 // {
455 // int l = ordered_latches[it.first];
456
457 // if (aig_latchinit.at(l) == 1)
458 // aig_map[it.first] ^= 1;
459
460 // if (aig_latchinit.at(l) == 2)
461 // {
462 // int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
463 // int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
464 // aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
465 // }
466 // }
467 //}
468
469 for (auto it : ff_map) {
470 int a = bit2aig(it.second);
471 int l = ordered_latches[it.first];
472 if (zinit_mode && aig_latchinit.at(l) == 1)
473 aig_latchin.push_back(a ^ 1);
474 else
475 aig_latchin.push_back(a);
476 }
477
478 //if (!initstate_bits.empty() || !init_inputs.empty())
479 // aig_latchin.push_back(1);
480
481 for (auto &c : co_bits) {
482 RTLIL::SigBit bit = c.first;
483 c.second = aig_o++;
484 ordered_outputs[bit] = c.second;
485 aig_outputs.push_back(bit2aig(bit));
486 }
487
488 for (auto bit : output_bits) {
489 ordered_outputs[bit] = aig_o++;
490 aig_outputs.push_back(bit2aig(bit));
491 }
492
493 if (omode && output_bits.empty()) {
494 aig_o++;
495 aig_outputs.push_back(0);
496 }
497
498 if (bmode) {
499 //aig_b++;
500 aig_outputs.push_back(0);
501 }
502 }
503
504 void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
505 {
506 int aig_obc = aig_o;
507 int aig_obcj = aig_obc;
508 int aig_obcjf = aig_obcj;
509
510 log_assert(aig_m == aig_i + aig_l + aig_a);
511 log_assert(aig_l == GetSize(aig_latchin));
512 log_assert(aig_l == GetSize(aig_latchinit));
513 log_assert(aig_obcjf == GetSize(aig_outputs));
514
515 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
516 f << stringf("\n");
517
518 if (ascii_mode)
519 {
520 for (int i = 0; i < aig_i; i++)
521 f << stringf("%d\n", 2*i+2);
522
523 for (int i = 0; i < aig_l; i++) {
524 if (zinit_mode || aig_latchinit.at(i) == 0)
525 f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
526 else if (aig_latchinit.at(i) == 1)
527 f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
528 else if (aig_latchinit.at(i) == 2)
529 f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
530 }
531
532 for (int i = 0; i < aig_obc; i++)
533 f << stringf("%d\n", aig_outputs.at(i));
534
535 for (int i = aig_obc; i < aig_obcj; i++)
536 f << stringf("1\n");
537
538 for (int i = aig_obc; i < aig_obcj; i++)
539 f << stringf("%d\n", aig_outputs.at(i));
540
541 for (int i = aig_obcj; i < aig_obcjf; i++)
542 f << stringf("%d\n", aig_outputs.at(i));
543
544 for (int i = 0; i < aig_a; i++)
545 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
546 }
547 else
548 {
549 for (int i = 0; i < aig_l; i++) {
550 if (zinit_mode || aig_latchinit.at(i) == 0)
551 f << stringf("%d\n", aig_latchin.at(i));
552 else if (aig_latchinit.at(i) == 1)
553 f << stringf("%d 1\n", aig_latchin.at(i));
554 else if (aig_latchinit.at(i) == 2)
555 f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
556 }
557
558 for (int i = 0; i < aig_obc; i++)
559 f << stringf("%d\n", aig_outputs.at(i));
560
561 for (int i = aig_obc; i < aig_obcj; i++)
562 f << stringf("1\n");
563
564 for (int i = aig_obc; i < aig_obcj; i++)
565 f << stringf("%d\n", aig_outputs.at(i));
566
567 for (int i = aig_obcj; i < aig_obcjf; i++)
568 f << stringf("%d\n", aig_outputs.at(i));
569
570 for (int i = 0; i < aig_a; i++) {
571 int lhs = 2*(aig_i+aig_l+i)+2;
572 int rhs0 = aig_gates.at(i).first;
573 int rhs1 = aig_gates.at(i).second;
574 int delta0 = lhs - rhs0;
575 int delta1 = rhs0 - rhs1;
576 aiger_encode(f, delta0);
577 aiger_encode(f, delta1);
578 }
579 }
580
581 if (symbols_mode)
582 {
583 dict<string, vector<string>> symbols;
584
585 bool output_seen = false;
586 for (auto wire : module->wires())
587 {
588 //if (wire->name[0] == '$')
589 // continue;
590
591 SigSpec sig = sigmap(wire);
592
593 for (int i = 0; i < GetSize(wire); i++)
594 {
595 RTLIL::SigBit b(wire, i);
596 if (input_bits.count(b)) {
597 int a = aig_map.at(sig[i]);
598 log_assert((a & 1) == 0);
599 if (GetSize(wire) != 1)
600 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
601 else
602 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
603 }
604
605 if (output_bits.count(b)) {
606 int o = ordered_outputs.at(b);
607 output_seen = !miter_mode;
608 if (GetSize(wire) != 1)
609 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
610 else
611 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
612 }
613
614 //if (init_inputs.count(sig[i])) {
615 // int a = init_inputs.at(sig[i]);
616 // log_assert((a & 1) == 0);
617 // if (GetSize(wire) != 1)
618 // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
619 // else
620 // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
621 //}
622
623 if (ordered_latches.count(sig[i])) {
624 int l = ordered_latches.at(sig[i]);
625 const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
626 if (GetSize(wire) != 1)
627 symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
628 else
629 symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
630 }
631 }
632 }
633
634 if (omode && !output_seen)
635 symbols["o0"].push_back("__dummy_o__");
636
637 symbols.sort();
638
639 for (auto &sym : symbols) {
640 f << sym.first;
641 std::sort(sym.second.begin(), sym.second.end());
642 for (auto &s : sym.second)
643 f << " " << s;
644 f << std::endl;
645 }
646 }
647
648 f << "c";
649
650 if (!box_list.empty()) {
651 std::stringstream h_buffer;
652 auto write_h_buffer = [&h_buffer](int i32) {
653 // TODO: Don't assume we're on little endian
654 #ifdef _WIN32
655 int i32_be = _byteswap_ulong(i32);
656 #else
657 int i32_be = __builtin_bswap32(i32);
658 #endif
659 h_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
660 };
661 int num_outputs = output_bits.size();
662 if (omode && num_outputs == 0)
663 num_outputs = 1;
664 write_h_buffer(1);
665 write_h_buffer(input_bits.size() + ci_bits.size());
666 write_h_buffer(num_outputs + co_bits.size());
667 write_h_buffer(input_bits.size());
668 write_h_buffer(num_outputs);
669 write_h_buffer(box_list.size());
670
671 RTLIL::Module *holes_module = nullptr;
672 holes_module = module->design->addModule("\\__holes__");
673 log_assert(holes_module);
674
675 for (auto cell : box_list) {
676 RTLIL::Module* box_module = module->design->module(cell->type);
677 int box_inputs = 0, box_outputs = 0;
678 Cell *holes_cell = nullptr;
679 if (box_module->get_bool_attribute("\\whitebox"))
680 holes_cell = holes_module->addCell(cell->name, cell->type);
681
682 RTLIL::Wire *holes_wire;
683 // TODO: Only sort once
684 box_module->wires_.sort(RTLIL::sort_by_id_str());
685 for (const auto w : box_module->wires()) {
686 RTLIL::SigSpec port_wire;
687 if (w->port_input) {
688 for (int i = 0; i < GetSize(w); i++) {
689 box_inputs++;
690 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
691 if (!holes_wire) {
692 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
693 holes_wire->port_input = true;
694 }
695 if (holes_cell)
696 port_wire.append(holes_wire);
697 }
698 if (!port_wire.empty())
699 holes_cell->setPort(w->name, port_wire);
700 }
701 if (w->port_output) {
702 box_outputs += GetSize(w);
703 for (int i = 0; i < GetSize(w); i++) {
704 if (GetSize(w) == 1)
705 holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
706 else
707 holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
708 holes_wire->port_output = true;
709 if (holes_cell)
710 port_wire.append(holes_wire);
711 else
712 holes_module->connect(holes_wire, RTLIL::S0);
713 }
714 if (!port_wire.empty())
715 holes_cell->setPort(w->name, port_wire);
716 }
717 }
718
719 write_h_buffer(box_inputs);
720 write_h_buffer(box_outputs);
721 write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
722 write_h_buffer(0 /* OldBoxNum */);
723 }
724
725 f << "h";
726 std::string buffer_str = h_buffer.str();
727 // TODO: Don't assume we're on little endian
728 #ifdef _WIN32
729 int buffer_size_be = _byteswap_ulong(buffer_str.size());
730 #else
731 int buffer_size_be = __builtin_bswap32(buffer_str.size());
732 #endif
733 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
734 f.write(buffer_str.data(), buffer_str.size());
735
736 if (holes_module) {
737 holes_module->fixup_ports();
738
739 holes_module->design->selection_stack.emplace_back(false);
740 RTLIL::Selection& sel = holes_module->design->selection_stack.back();
741 sel.select(holes_module);
742
743 // TODO: Should not need to opt_merge if we only instantiate
744 // each box type once...
745 Pass::call(holes_module->design, "opt_merge -share_all");
746
747 Pass::call(holes_module->design, "flatten -wb");
748
749 // TODO: Should techmap all lib_whitebox-es once
750 //Pass::call(holes_module->design, "techmap");
751
752 Pass::call(holes_module->design, "aigmap");
753 Pass::call(holes_module->design, "clean -purge");
754
755 holes_module->design->selection_stack.pop_back();
756
757 std::stringstream a_buffer;
758 XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/, true /* holes_mode */);
759 writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/);
760
761 f << "a";
762 std::string buffer_str = a_buffer.str();
763 // TODO: Don't assume we're on little endian
764 #ifdef _WIN32
765 int buffer_size_be = _byteswap_ulong(buffer_str.size());
766 #else
767 int buffer_size_be = __builtin_bswap32(buffer_str.size());
768 #endif
769 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
770 f.write(buffer_str.data(), buffer_str.size());
771 holes_module->design->remove(holes_module);
772 }
773
774 std::stringstream r_buffer;
775 auto write_r_buffer = [&r_buffer](int i32) {
776 // TODO: Don't assume we're on little endian
777 #ifdef _WIN32
778 int i32_be = _byteswap_ulong(i32);
779 #else
780 int i32_be = __builtin_bswap32(i32);
781 #endif
782 r_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
783 };
784 write_r_buffer(0);
785
786 f << "r";
787 buffer_str = r_buffer.str();
788 // TODO: Don't assume we're on little endian
789 #ifdef _WIN32
790 buffer_size_be = _byteswap_ulong(buffer_str.size());
791 #else
792 buffer_size_be = __builtin_bswap32(buffer_str.size());
793 #endif
794 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
795 f.write(buffer_str.data(), buffer_str.size());
796 }
797
798 f << stringf("Generated by %s\n", yosys_version_str);
799 }
800
801 void write_map(std::ostream &f, bool verbose_map, bool omode)
802 {
803 dict<int, string> input_lines;
804 dict<int, string> init_lines;
805 dict<int, string> output_lines;
806 dict<int, string> latch_lines;
807 dict<int, string> wire_lines;
808
809 for (auto wire : module->wires())
810 {
811 //if (!verbose_map && wire->name[0] == '$')
812 // continue;
813
814 SigSpec sig = sigmap(wire);
815
816 for (int i = 0; i < GetSize(wire); i++)
817 {
818 RTLIL::SigBit b(wire, i);
819 if (input_bits.count(b)) {
820 int a = aig_map.at(b);
821 log_assert((a & 1) == 0);
822 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
823 }
824
825 if (output_bits.count(b)) {
826 int o = ordered_outputs.at(b);
827 output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
828 continue;
829 }
830
831 //if (init_inputs.count(sig[i])) {
832 // int a = init_inputs.at(sig[i]);
833 // log_assert((a & 1) == 0);
834 // init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
835 // continue;
836 //}
837
838 if (ordered_latches.count(sig[i])) {
839 int l = ordered_latches.at(sig[i]);
840 if (zinit_mode && (aig_latchinit.at(l) == 1))
841 latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
842 else
843 latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
844 continue;
845 }
846
847 if (verbose_map) {
848 if (aig_map.count(sig[i]) == 0)
849 continue;
850
851 int a = aig_map.at(sig[i]);
852 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
853 }
854 }
855 }
856
857 for (const auto &c : ci_bits) {
858 RTLIL::SigBit b = c.first;
859 RTLIL::Wire *wire = b.wire;
860 int i = b.offset;
861 int a = bit2aig(b);
862 log_assert((a & 1) == 0);
863 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
864 }
865
866 for (const auto &c : co_bits) {
867 RTLIL::SigBit b = c.first;
868 RTLIL::Wire *wire = b.wire;
869 int o = c.second;
870 if (wire)
871 output_lines[o] += stringf("output %d %d %s\n", o, b.offset, log_id(wire));
872 else
873 output_lines[o] += stringf("output %d %d __const%d__\n", o, 0, b.data);
874 }
875
876 input_lines.sort();
877 for (auto &it : input_lines)
878 f << it.second;
879 log_assert(input_lines.size() == input_bits.size() + ci_bits.size());
880
881 init_lines.sort();
882 for (auto &it : init_lines)
883 f << it.second;
884
885 output_lines.sort();
886 for (auto &it : output_lines)
887 f << it.second;
888 log_assert(output_lines.size() == output_bits.size() + co_bits.size());
889 if (omode && output_bits.empty())
890 f << "output " << output_lines.size() << " 0 __dummy_o__\n";
891
892 latch_lines.sort();
893 for (auto &it : latch_lines)
894 f << it.second;
895
896 wire_lines.sort();
897 for (auto &it : wire_lines)
898 f << it.second;
899 }
900 };
901
902 struct XAigerBackend : public Backend {
903 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
904 void help() YS_OVERRIDE
905 {
906 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
907 log("\n");
908 log(" write_xaiger [options] [filename]\n");
909 log("\n");
910 log("Write the current design to an XAIGER file. The design must be flattened and\n");
911 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
912 log("\n");
913 log(" -ascii\n");
914 log(" write ASCII version of AIGER format\n");
915 log("\n");
916 log(" -zinit\n");
917 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
918 log(" uninitialized FFs.\n");
919 log("\n");
920 log(" -symbols\n");
921 log(" include a symbol table in the generated AIGER file\n");
922 log("\n");
923 log(" -map <filename>\n");
924 log(" write an extra file with port and latch symbols\n");
925 log("\n");
926 log(" -vmap <filename>\n");
927 log(" like -map, but more verbose\n");
928 log("\n");
929 log(" -I, -O, -B\n");
930 log(" If the design contains no input/output/assert then create one\n");
931 log(" dummy input/output/bad_state pin to make the tools reading the\n");
932 log(" AIGER file happy.\n");
933 log("\n");
934 }
935 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
936 {
937 bool ascii_mode = false;
938 bool zinit_mode = false;
939 bool miter_mode = false;
940 bool symbols_mode = false;
941 bool verbose_map = false;
942 bool imode = false;
943 bool omode = false;
944 bool bmode = false;
945 std::string map_filename;
946
947 log_header(design, "Executing XAIGER backend.\n");
948
949 size_t argidx;
950 for (argidx = 1; argidx < args.size(); argidx++)
951 {
952 if (args[argidx] == "-ascii") {
953 ascii_mode = true;
954 continue;
955 }
956 if (args[argidx] == "-zinit") {
957 zinit_mode = true;
958 continue;
959 }
960 if (args[argidx] == "-symbols") {
961 symbols_mode = true;
962 continue;
963 }
964 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
965 map_filename = args[++argidx];
966 continue;
967 }
968 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
969 map_filename = args[++argidx];
970 verbose_map = true;
971 continue;
972 }
973 if (args[argidx] == "-I") {
974 imode = true;
975 continue;
976 }
977 if (args[argidx] == "-O") {
978 omode = true;
979 continue;
980 }
981 if (args[argidx] == "-B") {
982 bmode = true;
983 continue;
984 }
985 break;
986 }
987 extra_args(f, filename, args, argidx);
988
989 Module *top_module = design->top_module();
990
991 if (top_module == nullptr)
992 log_error("Can't find top module in current design!\n");
993
994 XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
995 writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
996
997 if (!map_filename.empty()) {
998 std::ofstream mapf;
999 mapf.open(map_filename.c_str(), std::ofstream::trunc);
1000 if (mapf.fail())
1001 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
1002 writer.write_map(mapf, verbose_map, omode);
1003 }
1004 }
1005 } XAigerBackend;
1006
1007 PRIVATE_NAMESPACE_END