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Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/yosys.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/utils.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 void aiger_encode(std::ostream &f, int x)
30 {
31 log_assert(x >= 0);
32
33 while (x & ~0x7f) {
34 f.put((x & 0x7f) | 0x80);
35 x = x >> 7;
36 }
37
38 f.put(x);
39 }
40
41 struct XAigerWriter
42 {
43 Module *module;
44 bool zinit_mode;
45 SigMap sigmap;
46
47 dict<SigBit, bool> init_map;
48 pool<SigBit> input_bits, output_bits;
49 dict<SigBit, SigBit> not_map, ff_map, alias_map;
50 dict<SigBit, pair<SigBit, SigBit>> and_map;
51 //pool<SigBit> initstate_bits;
52 vector<std::pair<SigBit,int>> ci_bits, co_bits;
53
54 vector<pair<int, int>> aig_gates;
55 vector<int> aig_latchin, aig_latchinit, aig_outputs;
56 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
57
58 dict<SigBit, int> aig_map;
59 dict<SigBit, int> ordered_outputs;
60 dict<SigBit, int> ordered_latches;
61
62 vector<Cell*> box_list;
63
64 //dict<SigBit, int> init_inputs;
65 //int initstate_ff = 0;
66
67 int mkgate(int a0, int a1)
68 {
69 aig_m++, aig_a++;
70 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
71 return 2*aig_m;
72 }
73
74 int bit2aig(SigBit bit)
75 {
76 if (aig_map.count(bit) == 0)
77 {
78 aig_map[bit] = -1;
79
80 //if (initstate_bits.count(bit)) {
81 // log_assert(initstate_ff > 0);
82 // aig_map[bit] = initstate_ff;
83 //} else
84 if (not_map.count(bit)) {
85 int a = bit2aig(not_map.at(bit)) ^ 1;
86 aig_map[bit] = a;
87 } else
88 if (and_map.count(bit)) {
89 auto args = and_map.at(bit);
90 int a0 = bit2aig(args.first);
91 int a1 = bit2aig(args.second);
92 aig_map[bit] = mkgate(a0, a1);
93 } else
94 if (alias_map.count(bit)) {
95 aig_map[bit] = bit2aig(alias_map.at(bit));
96 }
97
98 if (bit == State::Sx || bit == State::Sz)
99 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
100 }
101
102 log_assert(aig_map.at(bit) >= 0);
103 return aig_map.at(bit);
104 }
105
106 XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
107 {
108 pool<SigBit> undriven_bits;
109 pool<SigBit> unused_bits;
110
111 // promote public wires
112 for (auto wire : module->wires())
113 if (wire->name[0] == '\\')
114 sigmap.add(wire);
115
116 // promote input wires
117 for (auto wire : module->wires())
118 if (wire->port_input)
119 sigmap.add(wire);
120
121 // promote output wires
122 for (auto wire : module->wires())
123 if (wire->port_output)
124 sigmap.add(wire);
125
126 for (auto wire : module->wires())
127 {
128 if (wire->attributes.count("\\init")) {
129 SigSpec initsig = sigmap(wire);
130 Const initval = wire->attributes.at("\\init");
131 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
132 if (initval[i] == State::S0 || initval[i] == State::S1)
133 init_map[initsig[i]] = initval[i] == State::S1;
134 }
135
136 bool keep = wire->attributes.count("\\keep");
137
138 for (int i = 0; i < GetSize(wire); i++)
139 {
140 SigBit wirebit(wire, i);
141 SigBit bit = sigmap(wirebit);
142
143 if (bit.wire == nullptr) {
144 if (wire->port_output) {
145 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
146 output_bits.insert(wirebit);
147 }
148 continue;
149 }
150
151 undriven_bits.insert(bit);
152 unused_bits.insert(bit);
153
154 if (wire->port_input)
155 input_bits.insert(bit);
156 else if (keep)
157 input_bits.insert(wirebit);
158
159 if (wire->port_output || keep) {
160 if (bit != wirebit)
161 alias_map[wirebit] = bit;
162 output_bits.insert(wirebit);
163 }
164 }
165 }
166
167 for (auto bit : input_bits)
168 undriven_bits.erase(bit);
169
170 for (auto bit : output_bits)
171 if (!bit.wire->port_input)
172 unused_bits.erase(bit);
173
174 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
175 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
176 bool abc_box_seen = false;
177
178 for (auto cell : module->cells())
179 {
180 RTLIL::Module* inst_module = module->design->module(cell->type);
181 bool known_type = yosys_celltypes.cell_known(cell->type);
182
183 if (!holes_mode) {
184 toposort.node(cell->name);
185 for (const auto &conn : cell->connections())
186 {
187 if (!cell->type.in("$_NOT_", "$_AND_")) {
188 if (known_type) {
189 if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
190 continue;
191 if (cell->type == "$memrd" && conn.first == "\\DATA")
192 continue;
193 }
194
195 if (inst_module) {
196 RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
197 log_assert(inst_module_port);
198
199 if (inst_module_port->attributes.count("\\abc_flop_q"))
200 continue;
201 }
202 }
203
204 if (cell->input(conn.first)) {
205 // Ignore inout for the sake of topographical ordering
206 if (cell->output(conn.first)) continue;
207 for (auto bit : sigmap(conn.second))
208 bit_users[bit].insert(cell->name);
209 }
210
211 if (cell->output(conn.first))
212 for (auto bit : sigmap(conn.second))
213 bit_drivers[bit].insert(cell->name);
214 }
215 }
216
217 if (cell->type == "$_NOT_")
218 {
219 SigBit A = sigmap(cell->getPort("\\A").as_bit());
220 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
221 unused_bits.erase(A);
222 undriven_bits.erase(Y);
223 not_map[Y] = A;
224 continue;
225 }
226
227 //if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
228 //{
229 // SigBit D = sigmap(cell->getPort("\\D").as_bit());
230 // SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
231 // unused_bits.erase(D);
232 // undriven_bits.erase(Q);
233 // ff_map[Q] = D;
234 // continue;
235 //}
236
237 if (cell->type == "$_AND_")
238 {
239 SigBit A = sigmap(cell->getPort("\\A").as_bit());
240 SigBit B = sigmap(cell->getPort("\\B").as_bit());
241 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
242 unused_bits.erase(A);
243 unused_bits.erase(B);
244 undriven_bits.erase(Y);
245 and_map[Y] = make_pair(A, B);
246 continue;
247 }
248
249 //if (cell->type == "$initstate")
250 //{
251 // SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
252 // undriven_bits.erase(Y);
253 // initstate_bits.insert(Y);
254 // continue;
255 //}
256
257 if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
258 abc_box_seen = true;
259 }
260 else {
261 for (const auto &c : cell->connections()) {
262 if (c.second.is_fully_const()) continue;
263 for (auto b : c.second.bits()) {
264 Wire *w = b.wire;
265 if (!w) continue;
266 auto is_input = cell->input(c.first);
267 auto is_output = cell->output(c.first);
268 log_assert(is_input || is_output);
269 if (is_input) {
270 if (!w->port_input) {
271 SigBit I = sigmap(b);
272 if (I != b)
273 alias_map[b] = I;
274 output_bits.insert(b);
275 unused_bits.erase(b);
276 }
277 }
278 if (is_output) {
279 SigBit O = sigmap(b);
280 input_bits.insert(O);
281 undriven_bits.erase(O);
282 }
283 }
284 }
285 }
286
287 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
288 }
289
290 if (abc_box_seen) {
291 for (auto &it : bit_users)
292 if (bit_drivers.count(it.first))
293 for (auto driver_cell : bit_drivers.at(it.first))
294 for (auto user_cell : it.second)
295 toposort.edge(driver_cell, user_cell);
296
297 toposort.sort();
298 for (auto cell_name : toposort.sorted) {
299 RTLIL::Cell *cell = module->cell(cell_name);
300 RTLIL::Module* box_module = module->design->module(cell->type);
301 if (!box_module || !box_module->attributes.count("\\abc_box_id"))
302 continue;
303
304 // Fully pad all unused input connections of this box cell with S0
305 // Fully pad all undriven output connections of thix box cell with anonymous wires
306 for (const auto w : box_module->wires()) {
307 if (w->port_input) {
308 auto it = cell->connections_.find(w->name);
309 if (it != cell->connections_.end()) {
310 if (GetSize(it->second) < GetSize(w)) {
311 RTLIL::SigSpec padded_connection(RTLIL::S0, GetSize(w)-GetSize(it->second));
312 padded_connection.append(it->second);
313 it->second = std::move(padded_connection);
314 }
315 }
316 else
317 cell->connections_[w->name] = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
318 }
319 if (w->port_output) {
320 auto it = cell->connections_.find(w->name);
321 if (it != cell->connections_.end()) {
322 if (GetSize(it->second) < GetSize(w)) {
323 RTLIL::SigSpec padded_connection = module->addWire(NEW_ID, GetSize(w)-GetSize(it->second));
324 padded_connection.append(it->second);
325 it->second = std::move(padded_connection);
326 }
327 }
328 else
329 cell->connections_[w->name] = module->addWire(NEW_ID, GetSize(w));
330 }
331 }
332
333 // Box ordering is alphabetical
334 cell->connections_.sort(RTLIL::sort_by_id_str());
335 for (const auto &c : cell->connections()) {
336 for (auto b : c.second.bits()) {
337 auto is_input = cell->input(c.first);
338 auto is_output = cell->output(c.first);
339 log_assert(is_input || is_output);
340 if (is_input) {
341 SigBit I = sigmap(b);
342 if (I != b)
343 alias_map[b] = I;
344 co_bits.emplace_back(b, 0);
345 }
346 if (is_output) {
347 SigBit O = sigmap(b);
348 ci_bits.emplace_back(O, 0);
349 }
350 }
351 }
352
353 box_list.emplace_back(cell);
354 }
355
356 // TODO: Free memory from toposort, bit_drivers, bit_users
357 }
358
359 for (auto bit : input_bits) {
360 RTLIL::Wire *wire = bit.wire;
361 // If encountering an inout port, or a keep-ed wire, then create a new wire
362 // with $inout.out suffix, make it a PO driven by the existing inout, and
363 // inherit existing inout's drivers
364 if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
365 || wire->attributes.count("\\keep")) {
366 log_assert(input_bits.count(bit) && output_bits.count(bit));
367 RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
368 if (!new_wire)
369 new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
370 SigBit new_bit(new_wire, bit.offset);
371 module->connect(new_bit, bit);
372 if (not_map.count(bit))
373 not_map[new_bit] = not_map.at(bit);
374 else if (and_map.count(bit))
375 and_map[new_bit] = and_map.at(bit);
376 else if (alias_map.count(bit))
377 alias_map[new_bit] = alias_map.at(bit);
378 else
379 //log_abort();
380 alias_map[new_bit] = bit;
381 output_bits.erase(bit);
382 output_bits.insert(new_bit);
383 }
384 }
385
386 // Do some CI/CO post-processing:
387 // Erase all POs that are undriven
388 for (auto bit : undriven_bits)
389 output_bits.erase(bit);
390 // CIs cannot be undriven
391 for (const auto &c : ci_bits)
392 undriven_bits.erase(c.first);
393 for (auto bit : unused_bits)
394 undriven_bits.erase(bit);
395
396 if (!undriven_bits.empty() && !holes_mode) {
397 undriven_bits.sort();
398 for (auto bit : undriven_bits) {
399 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
400 input_bits.insert(bit);
401 }
402 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
403 }
404
405 init_map.sort();
406 input_bits.sort();
407 output_bits.sort();
408 not_map.sort();
409 ff_map.sort();
410 and_map.sort();
411
412 aig_map[State::S0] = 0;
413 aig_map[State::S1] = 1;
414
415 for (auto bit : input_bits) {
416 aig_m++, aig_i++;
417 aig_map[bit] = 2*aig_m;
418 }
419
420 for (auto &c : ci_bits) {
421 aig_m++, aig_i++;
422 c.second = 2*aig_m;
423 aig_map[c.first] = c.second;
424 }
425
426 if (imode && input_bits.empty()) {
427 aig_m++, aig_i++;
428 }
429
430 //if (zinit_mode)
431 //{
432 // for (auto it : ff_map) {
433 // if (init_map.count(it.first))
434 // continue;
435 // aig_m++, aig_i++;
436 // init_inputs[it.first] = 2*aig_m;
437 // }
438 //}
439
440 for (auto it : ff_map) {
441 aig_m++, aig_l++;
442 aig_map[it.first] = 2*aig_m;
443 ordered_latches[it.first] = aig_l-1;
444 if (init_map.count(it.first) == 0)
445 aig_latchinit.push_back(2);
446 else
447 aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
448 }
449
450 //if (!initstate_bits.empty() || !init_inputs.empty()) {
451 // aig_m++, aig_l++;
452 // initstate_ff = 2*aig_m+1;
453 // aig_latchinit.push_back(0);
454 //}
455
456 //if (zinit_mode)
457 //{
458 // for (auto it : ff_map)
459 // {
460 // int l = ordered_latches[it.first];
461
462 // if (aig_latchinit.at(l) == 1)
463 // aig_map[it.first] ^= 1;
464
465 // if (aig_latchinit.at(l) == 2)
466 // {
467 // int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
468 // int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
469 // aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
470 // }
471 // }
472 //}
473
474 for (auto it : ff_map) {
475 int a = bit2aig(it.second);
476 int l = ordered_latches[it.first];
477 if (zinit_mode && aig_latchinit.at(l) == 1)
478 aig_latchin.push_back(a ^ 1);
479 else
480 aig_latchin.push_back(a);
481 }
482
483 //if (!initstate_bits.empty() || !init_inputs.empty())
484 // aig_latchin.push_back(1);
485
486 for (auto &c : co_bits) {
487 RTLIL::SigBit bit = c.first;
488 c.second = aig_o++;
489 ordered_outputs[bit] = c.second;
490 aig_outputs.push_back(bit2aig(bit));
491 }
492
493 for (auto bit : output_bits) {
494 ordered_outputs[bit] = aig_o++;
495 aig_outputs.push_back(bit2aig(bit));
496 }
497
498 if (omode && output_bits.empty()) {
499 aig_o++;
500 aig_outputs.push_back(0);
501 }
502
503 if (bmode) {
504 //aig_b++;
505 aig_outputs.push_back(0);
506 }
507 }
508
509 void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
510 {
511 int aig_obc = aig_o;
512 int aig_obcj = aig_obc;
513 int aig_obcjf = aig_obcj;
514
515 log_assert(aig_m == aig_i + aig_l + aig_a);
516 log_assert(aig_l == GetSize(aig_latchin));
517 log_assert(aig_l == GetSize(aig_latchinit));
518 log_assert(aig_obcjf == GetSize(aig_outputs));
519
520 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
521 f << stringf("\n");
522
523 if (ascii_mode)
524 {
525 for (int i = 0; i < aig_i; i++)
526 f << stringf("%d\n", 2*i+2);
527
528 for (int i = 0; i < aig_l; i++) {
529 if (zinit_mode || aig_latchinit.at(i) == 0)
530 f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
531 else if (aig_latchinit.at(i) == 1)
532 f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
533 else if (aig_latchinit.at(i) == 2)
534 f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
535 }
536
537 for (int i = 0; i < aig_obc; i++)
538 f << stringf("%d\n", aig_outputs.at(i));
539
540 for (int i = aig_obc; i < aig_obcj; i++)
541 f << stringf("1\n");
542
543 for (int i = aig_obc; i < aig_obcj; i++)
544 f << stringf("%d\n", aig_outputs.at(i));
545
546 for (int i = aig_obcj; i < aig_obcjf; i++)
547 f << stringf("%d\n", aig_outputs.at(i));
548
549 for (int i = 0; i < aig_a; i++)
550 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
551 }
552 else
553 {
554 for (int i = 0; i < aig_l; i++) {
555 if (zinit_mode || aig_latchinit.at(i) == 0)
556 f << stringf("%d\n", aig_latchin.at(i));
557 else if (aig_latchinit.at(i) == 1)
558 f << stringf("%d 1\n", aig_latchin.at(i));
559 else if (aig_latchinit.at(i) == 2)
560 f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
561 }
562
563 for (int i = 0; i < aig_obc; i++)
564 f << stringf("%d\n", aig_outputs.at(i));
565
566 for (int i = aig_obc; i < aig_obcj; i++)
567 f << stringf("1\n");
568
569 for (int i = aig_obc; i < aig_obcj; i++)
570 f << stringf("%d\n", aig_outputs.at(i));
571
572 for (int i = aig_obcj; i < aig_obcjf; i++)
573 f << stringf("%d\n", aig_outputs.at(i));
574
575 for (int i = 0; i < aig_a; i++) {
576 int lhs = 2*(aig_i+aig_l+i)+2;
577 int rhs0 = aig_gates.at(i).first;
578 int rhs1 = aig_gates.at(i).second;
579 int delta0 = lhs - rhs0;
580 int delta1 = rhs0 - rhs1;
581 aiger_encode(f, delta0);
582 aiger_encode(f, delta1);
583 }
584 }
585
586 if (symbols_mode)
587 {
588 dict<string, vector<string>> symbols;
589
590 bool output_seen = false;
591 for (auto wire : module->wires())
592 {
593 //if (wire->name[0] == '$')
594 // continue;
595
596 SigSpec sig = sigmap(wire);
597
598 for (int i = 0; i < GetSize(wire); i++)
599 {
600 RTLIL::SigBit b(wire, i);
601 if (input_bits.count(b)) {
602 int a = aig_map.at(sig[i]);
603 log_assert((a & 1) == 0);
604 if (GetSize(wire) != 1)
605 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
606 else
607 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
608 }
609
610 if (output_bits.count(b)) {
611 int o = ordered_outputs.at(b);
612 output_seen = !miter_mode;
613 if (GetSize(wire) != 1)
614 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
615 else
616 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
617 }
618
619 //if (init_inputs.count(sig[i])) {
620 // int a = init_inputs.at(sig[i]);
621 // log_assert((a & 1) == 0);
622 // if (GetSize(wire) != 1)
623 // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
624 // else
625 // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
626 //}
627
628 if (ordered_latches.count(sig[i])) {
629 int l = ordered_latches.at(sig[i]);
630 const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
631 if (GetSize(wire) != 1)
632 symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
633 else
634 symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
635 }
636 }
637 }
638
639 if (omode && !output_seen)
640 symbols["o0"].push_back("__dummy_o__");
641
642 symbols.sort();
643
644 for (auto &sym : symbols) {
645 f << sym.first;
646 std::sort(sym.second.begin(), sym.second.end());
647 for (auto &s : sym.second)
648 f << " " << s;
649 f << std::endl;
650 }
651 }
652
653 f << "c";
654
655 if (!box_list.empty()) {
656 std::stringstream h_buffer;
657 auto write_h_buffer = [&h_buffer](int i32) {
658 // TODO: Don't assume we're on little endian
659 #ifdef _WIN32
660 int i32_be = _byteswap_ulong(i32);
661 #else
662 int i32_be = __builtin_bswap32(i32);
663 #endif
664 h_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
665 };
666 int num_outputs = output_bits.size();
667 if (omode && num_outputs == 0)
668 num_outputs = 1;
669 write_h_buffer(1);
670 write_h_buffer(input_bits.size() + ci_bits.size());
671 write_h_buffer(num_outputs + co_bits.size());
672 write_h_buffer(input_bits.size());
673 write_h_buffer(num_outputs);
674 write_h_buffer(box_list.size());
675
676 RTLIL::Module *holes_module = nullptr;
677 holes_module = module->design->addModule("\\__holes__");
678 log_assert(holes_module);
679 dict<IdString, std::pair<int,int>> box_io;
680
681 for (auto cell : box_list) {
682 RTLIL::Module* box_module = module->design->module(cell->type);
683 int box_id = box_module->attributes.at("\\abc_box_id").as_int();
684 Cell *holes_cell = nullptr;
685 int box_inputs = 0, box_outputs = 0;
686
687 auto it = box_io.find(cell->type);
688 if (it == box_io.end()) {
689 holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
690
691 RTLIL::Wire *holes_wire;
692 box_module->wires_.sort(RTLIL::sort_by_id_str());
693 for (const auto w : box_module->wires()) {
694 RTLIL::SigSpec port_wire;
695 if (w->port_input) {
696 for (int i = 0; i < GetSize(w); i++) {
697 box_inputs++;
698 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
699 if (!holes_wire) {
700 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
701 holes_wire->port_input = true;
702 }
703 port_wire.append(holes_wire);
704 }
705 holes_cell->setPort(w->name, holes_wire);
706 }
707 if (w->port_output) {
708 box_outputs += GetSize(w);
709 for (int i = 0; i < GetSize(w); i++) {
710 if (GetSize(w) == 1)
711 holes_wire = holes_module->addWire(stringf("%s.%s", cell->type.c_str(), w->name.c_str()));
712 else
713 holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->type.c_str(), w->name.c_str(), i));
714 holes_wire->port_output = true;
715 port_wire.append(holes_wire);
716 }
717 holes_cell->setPort(w->name, holes_wire);
718 }
719 }
720 box_io[cell->type] = std::make_pair(box_inputs,box_outputs);
721 }
722 else
723 std::tie(box_inputs,box_outputs) = it->second;
724
725 write_h_buffer(box_inputs);
726 write_h_buffer(box_outputs);
727 write_h_buffer(box_id);
728 write_h_buffer(0 /* OldBoxNum */);
729 }
730
731 f << "h";
732 std::string buffer_str = h_buffer.str();
733 // TODO: Don't assume we're on little endian
734 #ifdef _WIN32
735 int buffer_size_be = _byteswap_ulong(buffer_str.size());
736 #else
737 int buffer_size_be = __builtin_bswap32(buffer_str.size());
738 #endif
739 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
740 f.write(buffer_str.data(), buffer_str.size());
741
742 if (holes_module) {
743 holes_module->fixup_ports();
744
745 holes_module->design->selection_stack.emplace_back(false);
746 RTLIL::Selection& sel = holes_module->design->selection_stack.back();
747 sel.select(holes_module);
748
749 Pass::call(holes_module->design, "flatten -wb; aigmap; clean -purge");
750
751 holes_module->design->selection_stack.pop_back();
752
753 std::stringstream a_buffer;
754 XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/, true /* holes_mode */);
755 writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/);
756
757 f << "a";
758 std::string buffer_str = a_buffer.str();
759 // TODO: Don't assume we're on little endian
760 #ifdef _WIN32
761 int buffer_size_be = _byteswap_ulong(buffer_str.size());
762 #else
763 int buffer_size_be = __builtin_bswap32(buffer_str.size());
764 #endif
765 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
766 f.write(buffer_str.data(), buffer_str.size());
767 holes_module->design->remove(holes_module);
768 }
769 }
770
771 f << stringf("Generated by %s\n", yosys_version_str);
772 }
773
774 void write_map(std::ostream &f, bool verbose_map, bool omode)
775 {
776 dict<int, string> input_lines;
777 dict<int, string> init_lines;
778 dict<int, string> output_lines;
779 dict<int, string> latch_lines;
780 dict<int, string> wire_lines;
781
782 for (auto wire : module->wires())
783 {
784 //if (!verbose_map && wire->name[0] == '$')
785 // continue;
786
787 SigSpec sig = sigmap(wire);
788
789 for (int i = 0; i < GetSize(wire); i++)
790 {
791 RTLIL::SigBit b(wire, i);
792 if (input_bits.count(b)) {
793 int a = aig_map.at(b);
794 log_assert((a & 1) == 0);
795 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
796 }
797
798 if (output_bits.count(b)) {
799 int o = ordered_outputs.at(b);
800 output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
801 continue;
802 }
803
804 //if (init_inputs.count(sig[i])) {
805 // int a = init_inputs.at(sig[i]);
806 // log_assert((a & 1) == 0);
807 // init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
808 // continue;
809 //}
810
811 if (ordered_latches.count(sig[i])) {
812 int l = ordered_latches.at(sig[i]);
813 if (zinit_mode && (aig_latchinit.at(l) == 1))
814 latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
815 else
816 latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
817 continue;
818 }
819
820 if (verbose_map) {
821 if (aig_map.count(sig[i]) == 0)
822 continue;
823
824 int a = aig_map.at(sig[i]);
825 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
826 }
827 }
828 }
829
830 for (const auto &c : ci_bits) {
831 RTLIL::SigBit b = c.first;
832 RTLIL::Wire *wire = b.wire;
833 int i = b.offset;
834 int a = bit2aig(b);
835 log_assert((a & 1) == 0);
836 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
837 }
838
839 for (const auto &c : co_bits) {
840 RTLIL::SigBit b = c.first;
841 RTLIL::Wire *wire = b.wire;
842 int o = c.second;
843 if (wire)
844 output_lines[o] += stringf("output %d %d %s\n", o, b.offset, log_id(wire));
845 else
846 output_lines[o] += stringf("output %d %d __const%d__\n", o, 0, b.data);
847 }
848
849 input_lines.sort();
850 for (auto &it : input_lines)
851 f << it.second;
852 log_assert(input_lines.size() == input_bits.size() + ci_bits.size());
853
854 init_lines.sort();
855 for (auto &it : init_lines)
856 f << it.second;
857
858 output_lines.sort();
859 for (auto &it : output_lines)
860 f << it.second;
861 log_assert(output_lines.size() == output_bits.size() + co_bits.size());
862 if (omode && output_bits.empty())
863 f << "output " << output_lines.size() << " 0 __dummy_o__\n";
864
865 latch_lines.sort();
866 for (auto &it : latch_lines)
867 f << it.second;
868
869 wire_lines.sort();
870 for (auto &it : wire_lines)
871 f << it.second;
872 }
873 };
874
875 struct XAigerBackend : public Backend {
876 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
877 void help() YS_OVERRIDE
878 {
879 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
880 log("\n");
881 log(" write_xaiger [options] [filename]\n");
882 log("\n");
883 log("Write the current design to an XAIGER file. The design must be flattened and\n");
884 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
885 log("\n");
886 log(" -ascii\n");
887 log(" write ASCII version of AIGER format\n");
888 log("\n");
889 log(" -zinit\n");
890 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
891 log(" uninitialized FFs.\n");
892 log("\n");
893 log(" -symbols\n");
894 log(" include a symbol table in the generated AIGER file\n");
895 log("\n");
896 log(" -map <filename>\n");
897 log(" write an extra file with port and latch symbols\n");
898 log("\n");
899 log(" -vmap <filename>\n");
900 log(" like -map, but more verbose\n");
901 log("\n");
902 log(" -I, -O, -B\n");
903 log(" If the design contains no input/output/assert then create one\n");
904 log(" dummy input/output/bad_state pin to make the tools reading the\n");
905 log(" AIGER file happy.\n");
906 log("\n");
907 }
908 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
909 {
910 bool ascii_mode = false;
911 bool zinit_mode = false;
912 bool miter_mode = false;
913 bool symbols_mode = false;
914 bool verbose_map = false;
915 bool imode = false;
916 bool omode = false;
917 bool bmode = false;
918 std::string map_filename;
919
920 log_header(design, "Executing XAIGER backend.\n");
921
922 size_t argidx;
923 for (argidx = 1; argidx < args.size(); argidx++)
924 {
925 if (args[argidx] == "-ascii") {
926 ascii_mode = true;
927 continue;
928 }
929 if (args[argidx] == "-zinit") {
930 zinit_mode = true;
931 continue;
932 }
933 if (args[argidx] == "-symbols") {
934 symbols_mode = true;
935 continue;
936 }
937 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
938 map_filename = args[++argidx];
939 continue;
940 }
941 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
942 map_filename = args[++argidx];
943 verbose_map = true;
944 continue;
945 }
946 if (args[argidx] == "-I") {
947 imode = true;
948 continue;
949 }
950 if (args[argidx] == "-O") {
951 omode = true;
952 continue;
953 }
954 if (args[argidx] == "-B") {
955 bmode = true;
956 continue;
957 }
958 break;
959 }
960 extra_args(f, filename, args, argidx);
961
962 Module *top_module = design->top_module();
963
964 if (top_module == nullptr)
965 log_error("Can't find top module in current design!\n");
966
967 XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
968 writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
969
970 if (!map_filename.empty()) {
971 std::ofstream mapf;
972 mapf.open(map_filename.c_str(), std::ofstream::trunc);
973 if (mapf.fail())
974 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
975 writer.write_map(mapf, verbose_map, omode);
976 }
977 }
978 } XAigerBackend;
979
980 PRIVATE_NAMESPACE_END