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Use a cell_cache to instantiate once rather than opt_merge call
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50
51 USING_YOSYS_NAMESPACE
52 PRIVATE_NAMESPACE_BEGIN
53
54 inline int32_t to_big_endian(int32_t i32) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
56 return bswap32(i32);
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
58 return i32;
59 #else
60 #error "Unknown endianness"
61 #endif
62 }
63
64 void aiger_encode(std::ostream &f, int x)
65 {
66 log_assert(x >= 0);
67
68 while (x & ~0x7f) {
69 f.put((x & 0x7f) | 0x80);
70 x = x >> 7;
71 }
72
73 f.put(x);
74 }
75
76 struct XAigerWriter
77 {
78 Module *module;
79 bool zinit_mode;
80 SigMap sigmap;
81
82 dict<SigBit, bool> init_map;
83 pool<SigBit> input_bits, output_bits;
84 dict<SigBit, SigBit> not_map, /*ff_map,*/ alias_map;
85 dict<SigBit, pair<SigBit, SigBit>> and_map;
86 vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
87 vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
88 dict<SigBit, int> ff_bits;
89 dict<SigBit, float> arrival_times;
90
91 vector<pair<int, int>> aig_gates;
92 vector<int> aig_latchin, aig_latchinit, aig_outputs;
93 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
94
95 dict<SigBit, int> aig_map;
96 dict<SigBit, int> ordered_outputs;
97 dict<SigBit, int> ordered_latches;
98
99 vector<Cell*> box_list;
100 bool omode = false;
101
102 //dict<SigBit, int> init_inputs;
103 //int initstate_ff = 0;
104
105 int mkgate(int a0, int a1)
106 {
107 aig_m++, aig_a++;
108 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
109 return 2*aig_m;
110 }
111
112 int bit2aig(SigBit bit)
113 {
114 auto it = aig_map.find(bit);
115 if (it != aig_map.end()) {
116 log_assert(it->second >= 0);
117 return it->second;
118 }
119
120 // NB: Cannot use iterator returned from aig_map.insert()
121 // since this function is called recursively
122
123 int a = -1;
124 if (not_map.count(bit)) {
125 a = bit2aig(not_map.at(bit)) ^ 1;
126 } else
127 if (and_map.count(bit)) {
128 auto args = and_map.at(bit);
129 int a0 = bit2aig(args.first);
130 int a1 = bit2aig(args.second);
131 a = mkgate(a0, a1);
132 } else
133 if (alias_map.count(bit)) {
134 a = bit2aig(alias_map.at(bit));
135 }
136
137 if (bit == State::Sx || bit == State::Sz) {
138 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
139 a = aig_map.at(State::S0);
140 }
141
142 log_assert(a >= 0);
143 aig_map[bit] = a;
144 return a;
145 }
146
147 XAigerWriter(Module *module, bool zinit_mode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
148 {
149 pool<SigBit> undriven_bits;
150 pool<SigBit> unused_bits;
151 pool<SigBit> keep_bits;
152
153 // promote public wires
154 for (auto wire : module->wires())
155 if (wire->name[0] == '\\')
156 sigmap.add(wire);
157
158 // promote input wires
159 for (auto wire : module->wires())
160 if (wire->port_input)
161 sigmap.add(wire);
162
163 // promote output wires
164 for (auto wire : module->wires())
165 if (wire->port_output)
166 sigmap.add(wire);
167
168 for (auto wire : module->wires())
169 {
170 if (wire->attributes.count("\\init")) {
171 SigSpec initsig = sigmap(wire);
172 Const initval = wire->attributes.at("\\init");
173 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
174 if (initval[i] == State::S0 || initval[i] == State::S1)
175 init_map[initsig[i]] = initval[i] == State::S1;
176 }
177
178 bool keep = wire->attributes.count("\\keep");
179
180 for (int i = 0; i < GetSize(wire); i++)
181 {
182 SigBit wirebit(wire, i);
183 SigBit bit = sigmap(wirebit);
184
185 if (bit.wire) {
186 undriven_bits.insert(bit);
187 unused_bits.insert(bit);
188 }
189
190 if (keep)
191 keep_bits.insert(bit);
192
193 if (wire->port_input || keep) {
194 if (bit != wirebit)
195 alias_map[bit] = wirebit;
196 input_bits.insert(wirebit);
197 }
198
199 if (wire->port_output || keep) {
200 if (bit != RTLIL::Sx) {
201 if (bit != wirebit)
202 alias_map[wirebit] = bit;
203 output_bits.insert(wirebit);
204 }
205 else
206 log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
207 }
208 }
209 }
210
211 for (auto bit : input_bits)
212 undriven_bits.erase(sigmap(bit));
213 for (auto bit : output_bits)
214 if (!bit.wire->port_input)
215 unused_bits.erase(bit);
216
217 // TODO: Speed up toposort -- ultimately we care about
218 // box ordering, but not individual AIG cells
219 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
220 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
221 bool abc_box_seen = false;
222 std::vector<Cell*> flop_boxes;
223
224 for (auto cell : module->selected_cells()) {
225 if (cell->type == "$_NOT_")
226 {
227 SigBit A = sigmap(cell->getPort("\\A").as_bit());
228 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
229 unused_bits.erase(A);
230 undriven_bits.erase(Y);
231 not_map[Y] = A;
232 if (!holes_mode) {
233 toposort.node(cell->name);
234 bit_users[A].insert(cell->name);
235 bit_drivers[Y].insert(cell->name);
236 }
237 continue;
238 }
239
240 if (cell->type == "$_AND_")
241 {
242 SigBit A = sigmap(cell->getPort("\\A").as_bit());
243 SigBit B = sigmap(cell->getPort("\\B").as_bit());
244 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
245 unused_bits.erase(A);
246 unused_bits.erase(B);
247 undriven_bits.erase(Y);
248 and_map[Y] = make_pair(A, B);
249 if (!holes_mode) {
250 toposort.node(cell->name);
251 bit_users[A].insert(cell->name);
252 bit_users[B].insert(cell->name);
253 bit_drivers[Y].insert(cell->name);
254 }
255 continue;
256 }
257
258 log_assert(!holes_mode);
259
260 if (cell->type == "$__ABC_FF_")
261 {
262 SigBit D = sigmap(cell->getPort("\\D").as_bit());
263 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
264 unused_bits.erase(D);
265 undriven_bits.erase(Q);
266 alias_map[Q] = D;
267 auto r = ff_bits.insert(std::make_pair(D, 0));
268 log_assert(r.second);
269 continue;
270 }
271
272 RTLIL::Module* inst_module = module->design->module(cell->type);
273 if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
274 abc_box_seen = true;
275
276 toposort.node(cell->name);
277
278 for (const auto &conn : cell->connections()) {
279 auto port_wire = inst_module->wire(conn.first);
280 if (port_wire->port_input) {
281 // Ignore inout for the sake of topographical ordering
282 if (port_wire->port_output) continue;
283 for (auto bit : sigmap(conn.second))
284 bit_users[bit].insert(cell->name);
285 }
286
287 if (port_wire->port_output)
288 for (auto bit : sigmap(conn.second))
289 bit_drivers[bit].insert(cell->name);
290 }
291
292 if (inst_module->attributes.count("\\abc9_flop"))
293 flop_boxes.push_back(cell);
294 continue;
295 }
296
297 bool cell_known = inst_module || cell->known();
298 for (const auto &c : cell->connections()) {
299 if (c.second.is_fully_const()) continue;
300 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
301 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
302 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
303 if (!is_input && !is_output)
304 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
305
306 if (is_input) {
307 for (auto b : c.second) {
308 Wire *w = b.wire;
309 if (!w) continue;
310 if (!w->port_output || !cell_known) {
311 SigBit I = sigmap(b);
312 if (I != b)
313 alias_map[b] = I;
314 output_bits.insert(b);
315 unused_bits.erase(b);
316
317 if (!cell_known)
318 keep_bits.insert(b);
319 }
320 }
321 }
322 if (is_output) {
323 int arrival = 0;
324 if (port_wire) {
325 auto it = port_wire->attributes.find("\\abc_arrival");
326 if (it != port_wire->attributes.end()) {
327 if (it->second.flags != 0)
328 log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
329 arrival = it->second.as_int();
330 }
331 }
332
333 for (auto b : c.second) {
334 Wire *w = b.wire;
335 if (!w) continue;
336 input_bits.insert(b);
337 SigBit O = sigmap(b);
338 if (O != b)
339 alias_map[O] = b;
340 undriven_bits.erase(O);
341
342 if (arrival)
343 arrival_times[b] = arrival;
344 }
345 }
346 }
347
348 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
349 }
350
351 if (abc_box_seen) {
352 dict<IdString, std::pair<IdString,int>> flop_q;
353 for (auto cell : flop_boxes) {
354 auto r = flop_q.insert(std::make_pair(cell->type, std::make_pair(IdString(), 0)));
355 SigBit d;
356 if (r.second) {
357 for (const auto &conn : cell->connections()) {
358 const SigSpec &rhs = conn.second;
359 if (!rhs.is_bit())
360 continue;
361 if (!ff_bits.count(rhs))
362 continue;
363 r.first->second.first = conn.first;
364 Module *inst_module = module->design->module(cell->type);
365 Wire *wire = inst_module->wire(conn.first);
366 log_assert(wire);
367 auto jt = wire->attributes.find("\\abc_arrival");
368 if (jt != wire->attributes.end()) {
369 if (jt->second.flags != 0)
370 log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
371 r.first->second.second = jt->second.as_int();
372 }
373 d = rhs;
374 log_assert(d == sigmap(d));
375 break;
376 }
377 }
378 else
379 d = cell->getPort(r.first->second.first);
380
381 auto it = cell->attributes.find(ID(abc9_mergeability));
382 log_assert(it != cell->attributes.end());
383 ff_bits.at(d) = it->second.as_int();
384 cell->attributes.erase(it);
385
386 auto arrival = r.first->second.second;
387 if (arrival)
388 arrival_times[d] = arrival;
389 }
390
391 for (auto &it : bit_users)
392 if (bit_drivers.count(it.first))
393 for (auto driver_cell : bit_drivers.at(it.first))
394 for (auto user_cell : it.second)
395 toposort.edge(driver_cell, user_cell);
396
397 #if 0
398 toposort.analyze_loops = true;
399 #endif
400 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
401 #if 0
402 unsigned i = 0;
403 for (auto &it : toposort.loops) {
404 log(" loop %d\n", i++);
405 for (auto cell_name : it) {
406 auto cell = module->cell(cell_name);
407 log_assert(cell);
408 log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
409 }
410 }
411 #endif
412 log_assert(no_loops);
413
414 for (auto cell_name : toposort.sorted) {
415 RTLIL::Cell *cell = module->cell(cell_name);
416 log_assert(cell);
417
418 RTLIL::Module* box_module = module->design->module(cell->type);
419 if (!box_module || !box_module->attributes.count("\\abc_box_id"))
420 continue;
421
422 bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
423
424 // Fully pad all unused input connections of this box cell with S0
425 // Fully pad all undriven output connections of this box cell with anonymous wires
426 // NB: Assume box_module->ports are sorted alphabetically
427 // (as RTLIL::Module::fixup_ports() would do)
428 for (const auto &port_name : box_module->ports) {
429 RTLIL::Wire* w = box_module->wire(port_name);
430 log_assert(w);
431 auto it = cell->connections_.find(port_name);
432 if (w->port_input) {
433 RTLIL::SigSpec rhs;
434 if (it != cell->connections_.end()) {
435 if (GetSize(it->second) < GetSize(w))
436 it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
437 rhs = it->second;
438 }
439 else {
440 rhs = RTLIL::SigSpec(State::S0, GetSize(w));
441 cell->setPort(port_name, rhs);
442 }
443
444 int offset = 0;
445 for (auto b : rhs.bits()) {
446 SigBit I = sigmap(b);
447 if (b == RTLIL::Sx)
448 b = State::S0;
449 else if (I != b) {
450 if (I == RTLIL::Sx)
451 alias_map[b] = State::S0;
452 else
453 alias_map[b] = I;
454 }
455 co_bits.emplace_back(b, cell, port_name, offset++, 0);
456 unused_bits.erase(b);
457 }
458 }
459 if (w->port_output) {
460 RTLIL::SigSpec rhs;
461 auto it = cell->connections_.find(w->name);
462 if (it != cell->connections_.end()) {
463 if (GetSize(it->second) < GetSize(w))
464 it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
465 rhs = it->second;
466 }
467 else {
468 Wire *wire = module->addWire(NEW_ID, GetSize(w));
469 if (blackbox)
470 wire->set_bool_attribute(ID(abc_padding));
471 rhs = wire;
472 cell->setPort(port_name, rhs);
473 }
474
475 int offset = 0;
476 for (const auto &b : rhs.bits()) {
477 ci_bits.emplace_back(b, cell, port_name, offset++);
478 SigBit O = sigmap(b);
479 if (O != b)
480 alias_map[O] = b;
481 undriven_bits.erase(O);
482 input_bits.erase(b);
483 }
484 }
485 }
486
487 if (box_module->get_bool_attribute("\\abc9_flop")) {
488 IdString port_name = "\\$currQ";
489 RTLIL::Wire* w = box_module->wire(port_name);
490 SigSpec rhs = cell->getPort(port_name);
491 log_assert(GetSize(w) == GetSize(rhs));
492
493 int offset = 0;
494 for (auto b : rhs.bits()) {
495 SigBit I = sigmap(b);
496 if (b == RTLIL::Sx)
497 b = State::S0;
498 else if (I != b) {
499 if (I == RTLIL::Sx)
500 alias_map[b] = State::S0;
501 else
502 alias_map[b] = I;
503 }
504 co_bits.emplace_back(b, cell, port_name, offset++, 0);
505 unused_bits.erase(b);
506 }
507 }
508
509 box_list.emplace_back(cell);
510 }
511
512 // TODO: Free memory from toposort, bit_drivers, bit_users
513 }
514
515 for (auto bit : input_bits) {
516 if (!output_bits.count(bit))
517 continue;
518 RTLIL::Wire *wire = bit.wire;
519 // If encountering an inout port, or a keep-ed wire, then create a new wire
520 // with $inout.out suffix, make it a PO driven by the existing inout, and
521 // inherit existing inout's drivers
522 if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
523 || keep_bits.count(bit)) {
524 RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
525 RTLIL::Wire *new_wire = module->wire(wire_name);
526 if (!new_wire)
527 new_wire = module->addWire(wire_name, GetSize(wire));
528 SigBit new_bit(new_wire, bit.offset);
529 module->connect(new_bit, bit);
530 if (not_map.count(bit)) {
531 auto a = not_map.at(bit);
532 not_map[new_bit] = a;
533 }
534 else if (and_map.count(bit)) {
535 auto a = and_map.at(bit);
536 and_map[new_bit] = a;
537 }
538 else if (alias_map.count(bit)) {
539 auto a = alias_map.at(bit);
540 alias_map[new_bit] = a;
541 }
542 else
543 alias_map[new_bit] = bit;
544 output_bits.erase(bit);
545 output_bits.insert(new_bit);
546 }
547 }
548
549 for (auto bit : unused_bits)
550 undriven_bits.erase(bit);
551
552 if (!undriven_bits.empty() && !holes_mode) {
553 bool whole_module = module->design->selected_whole_module(module->name);
554 undriven_bits.sort();
555 for (auto bit : undriven_bits) {
556 if (whole_module)
557 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
558 input_bits.insert(bit);
559 }
560 if (whole_module)
561 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
562 }
563
564 init_map.sort();
565 if (holes_mode) {
566 struct sort_by_port_id {
567 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
568 return a.wire->port_id < b.wire->port_id;
569 }
570 };
571 input_bits.sort(sort_by_port_id());
572 output_bits.sort(sort_by_port_id());
573 }
574 else {
575 input_bits.sort();
576 output_bits.sort();
577 }
578
579 not_map.sort();
580 //ff_map.sort();
581 and_map.sort();
582
583 aig_map[State::S0] = 0;
584 aig_map[State::S1] = 1;
585
586 for (auto bit : input_bits) {
587 aig_m++, aig_i++;
588 log_assert(!aig_map.count(bit));
589 aig_map[bit] = 2*aig_m;
590 }
591
592 for (const auto &i : ff_bits) {
593 const SigBit &bit = i.first;
594 aig_m++, aig_i++;
595 log_assert(!aig_map.count(bit));
596 aig_map[bit] = 2*aig_m;
597 }
598
599 dict<SigBit, int> ff_aig_map;
600 for (auto &c : ci_bits) {
601 RTLIL::SigBit bit = std::get<0>(c);
602 aig_m++, aig_i++;
603 auto r = aig_map.insert(std::make_pair(bit, 2*aig_m));
604 if (!r.second)
605 ff_aig_map[bit] = 2*aig_m;
606 }
607
608 //if (zinit_mode)
609 //{
610 // for (auto it : ff_map) {
611 // if (init_map.count(it.first))
612 // continue;
613 // aig_m++, aig_i++;
614 // init_inputs[it.first] = 2*aig_m;
615 // }
616 //}
617
618 //for (auto it : ff_map) {
619 // aig_m++, aig_l++;
620 // aig_map[it.first] = 2*aig_m;
621 // ordered_latches[it.first] = aig_l-1;
622 // if (init_map.count(it.first) == 0)
623 // aig_latchinit.push_back(2);
624 // else
625 // aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
626 //}
627
628 //if (!init_inputs.empty()) {
629 // aig_m++, aig_l++;
630 // initstate_ff = 2*aig_m+1;
631 // aig_latchinit.push_back(0);
632 //}
633
634 //if (zinit_mode)
635 //{
636 // for (auto it : ff_map)
637 // {
638 // int l = ordered_latches[it.first];
639
640 // if (aig_latchinit.at(l) == 1)
641 // aig_map[it.first] ^= 1;
642
643 // if (aig_latchinit.at(l) == 2)
644 // {
645 // int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
646 // int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
647 // aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
648 // }
649 // }
650 //}
651
652 //for (auto it : ff_map) {
653 // int a = bit2aig(it.second);
654 // int l = ordered_latches[it.first];
655 // if (zinit_mode && aig_latchinit.at(l) == 1)
656 // aig_latchin.push_back(a ^ 1);
657 // else
658 // aig_latchin.push_back(a);
659 //}
660
661 //if (!init_inputs.empty())
662 // aig_latchin.push_back(1);
663
664 for (auto &c : co_bits) {
665 RTLIL::SigBit bit = std::get<0>(c);
666 std::get<4>(c) = ordered_outputs[bit] = aig_o++;
667 aig_outputs.push_back(bit2aig(bit));
668 }
669
670 if (output_bits.empty()) {
671 output_bits.insert(State::S0);
672 omode = true;
673 }
674
675 for (auto bit : output_bits) {
676 ordered_outputs[bit] = aig_o++;
677 aig_outputs.push_back(bit2aig(bit));
678 }
679
680 for (auto &i : ff_bits) {
681 const SigBit &bit = i.first;
682 aig_o++;
683 aig_outputs.push_back(ff_aig_map.at(bit));
684 }
685
686 if (output_bits.empty()) {
687 aig_o++;
688 aig_outputs.push_back(0);
689 omode = true;
690 }
691 }
692
693 void write_aiger(std::ostream &f, bool ascii_mode)
694 {
695 int aig_obc = aig_o;
696 int aig_obcj = aig_obc;
697 int aig_obcjf = aig_obcj;
698
699 log_assert(aig_m == aig_i + aig_l + aig_a);
700 log_assert(aig_l == GetSize(aig_latchin));
701 log_assert(aig_l == GetSize(aig_latchinit));
702 log_assert(aig_obcjf == GetSize(aig_outputs));
703
704 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
705 f << stringf("\n");
706
707 if (ascii_mode)
708 {
709 for (int i = 0; i < aig_i; i++)
710 f << stringf("%d\n", 2*i+2);
711
712 //for (int i = 0; i < aig_l; i++) {
713 // if (zinit_mode || aig_latchinit.at(i) == 0)
714 // f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
715 // else if (aig_latchinit.at(i) == 1)
716 // f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
717 // else if (aig_latchinit.at(i) == 2)
718 // f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
719 //}
720
721 for (int i = 0; i < aig_obc; i++)
722 f << stringf("%d\n", aig_outputs.at(i));
723
724 for (int i = aig_obc; i < aig_obcj; i++)
725 f << stringf("1\n");
726
727 for (int i = aig_obc; i < aig_obcj; i++)
728 f << stringf("%d\n", aig_outputs.at(i));
729
730 for (int i = aig_obcj; i < aig_obcjf; i++)
731 f << stringf("%d\n", aig_outputs.at(i));
732
733 for (int i = 0; i < aig_a; i++)
734 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
735 }
736 else
737 {
738 //for (int i = 0; i < aig_l; i++) {
739 // if (zinit_mode || aig_latchinit.at(i) == 0)
740 // f << stringf("%d\n", aig_latchin.at(i));
741 // else if (aig_latchinit.at(i) == 1)
742 // f << stringf("%d 1\n", aig_latchin.at(i));
743 // else if (aig_latchinit.at(i) == 2)
744 // f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
745 //}
746
747 for (int i = 0; i < aig_obc; i++)
748 f << stringf("%d\n", aig_outputs.at(i));
749
750 for (int i = aig_obc; i < aig_obcj; i++)
751 f << stringf("1\n");
752
753 for (int i = aig_obc; i < aig_obcj; i++)
754 f << stringf("%d\n", aig_outputs.at(i));
755
756 for (int i = aig_obcj; i < aig_obcjf; i++)
757 f << stringf("%d\n", aig_outputs.at(i));
758
759 for (int i = 0; i < aig_a; i++) {
760 int lhs = 2*(aig_i+aig_l+i)+2;
761 int rhs0 = aig_gates.at(i).first;
762 int rhs1 = aig_gates.at(i).second;
763 int delta0 = lhs - rhs0;
764 int delta1 = rhs0 - rhs1;
765 aiger_encode(f, delta0);
766 aiger_encode(f, delta1);
767 }
768 }
769
770 f << "c";
771
772 log_assert(!output_bits.empty());
773 auto write_buffer = [](std::stringstream &buffer, int i32) {
774 int32_t i32_be = to_big_endian(i32);
775 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
776 };
777 std::stringstream h_buffer;
778 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
779 write_h_buffer(1);
780 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
781 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
782 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
783 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
784 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
785 write_h_buffer(input_bits.size() + ff_bits.size());
786 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
787 write_h_buffer(output_bits.size() + ff_bits.size());
788 log_debug("boxNum = %d\n", GetSize(box_list));
789 write_h_buffer(box_list.size());
790
791 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
792 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
793 };
794 std::stringstream i_buffer;
795 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
796 for (auto bit : input_bits)
797 write_i_buffer(arrival_times.at(bit, 0));
798 //std::stringstream o_buffer;
799 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
800 //for (auto bit : output_bits)
801 // write_o_buffer(0);
802
803 if (!box_list.empty() || !ff_bits.empty()) {
804 RTLIL::Module *holes_module = module->design->addModule("$__holes__");
805 log_assert(holes_module);
806
807 dict<IdString, Cell*> cell_cache;
808
809 int port_id = 1;
810 int box_count = 0;
811 for (auto cell : box_list) {
812 RTLIL::Module* box_module = module->design->module(cell->type);
813 log_assert(box_module);
814 IdString derived_name = box_module->derive(module->design, cell->parameters);
815 box_module = module->design->module(derived_name);
816
817 int box_inputs = 0, box_outputs = 0;
818 auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
819 Cell *holes_cell = r.first->second;
820 if (r.second && !holes_cell && box_module->get_bool_attribute("\\whitebox")) {
821 holes_cell = holes_module->addCell(cell->name, cell->type);
822 holes_cell->parameters = cell->parameters;
823 r.first->second = holes_cell;
824 }
825
826 // NB: Assume box_module->ports are sorted alphabetically
827 // (as RTLIL::Module::fixup_ports() would do)
828 for (const auto &port_name : box_module->ports) {
829 RTLIL::Wire *w = box_module->wire(port_name);
830 log_assert(w);
831 RTLIL::Wire *holes_wire;
832 RTLIL::SigSpec port_wire;
833 if (w->port_input)
834 for (int i = 0; i < GetSize(w); i++) {
835 box_inputs++;
836 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
837 if (!holes_wire) {
838 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
839 holes_wire->port_input = true;
840 holes_wire->port_id = port_id++;
841 holes_module->ports.push_back(holes_wire->name);
842 }
843 if (holes_cell)
844 port_wire.append(holes_wire);
845 }
846 if (w->port_output) {
847 box_outputs += GetSize(w);
848 for (int i = 0; i < GetSize(w); i++) {
849 if (GetSize(w) == 1)
850 holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
851 else
852 holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
853 holes_wire->port_output = true;
854 holes_wire->port_id = port_id++;
855 holes_module->ports.push_back(holes_wire->name);
856 if (holes_cell)
857 port_wire.append(holes_wire);
858 else
859 holes_module->connect(holes_wire, State::S0);
860 }
861 }
862 if (!port_wire.empty()) {
863 if (r.second)
864 holes_cell->setPort(w->name, port_wire);
865 else
866 holes_module->connect(port_wire, holes_cell->getPort(w->name));
867 }
868 }
869
870 write_h_buffer(box_inputs);
871 write_h_buffer(box_outputs);
872 write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
873 write_h_buffer(box_count++);
874 }
875
876 std::stringstream r_buffer;
877 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
878 log_debug("flopNum = %d\n", GetSize(ff_bits));
879 write_r_buffer(ff_bits.size());
880 for (const auto &i : ff_bits) {
881 log_assert(i.second > 0);
882 write_r_buffer(i.second);
883 const SigBit &bit = i.first;
884 write_i_buffer(arrival_times.at(bit, 0));
885 //write_o_buffer(0);
886 }
887
888 f << "r";
889 std::string buffer_str = r_buffer.str();
890 int32_t buffer_size_be = to_big_endian(buffer_str.size());
891 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
892 f.write(buffer_str.data(), buffer_str.size());
893
894 std::stringstream s_buffer;
895 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
896 write_s_buffer(ff_bits.size());
897 for (const auto &i : ff_bits) {
898 const SigBit &bit = i.first;
899 auto it = bit.wire->attributes.find("\\init");
900 if (it != bit.wire->attributes.end()) {
901 auto init = it->second[bit.offset];
902 if (init == RTLIL::S1) {
903 write_s_buffer(1);
904 continue;
905 }
906 }
907 write_s_buffer(0);
908 }
909 f << "s";
910 buffer_str = s_buffer.str();
911 buffer_size_be = to_big_endian(buffer_str.size());
912 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
913 f.write(buffer_str.data(), buffer_str.size());
914
915 if (holes_module) {
916 log_push();
917
918 // NB: fixup_ports() will sort ports by name
919 //holes_module->fixup_ports();
920 holes_module->check();
921
922 Design *design = holes_module->design;
923 design->selection_stack.emplace_back(false);
924 RTLIL::Selection& sel = design->selection_stack.back();
925 log_assert(design->selected_active_module == module->name.c_str());
926 design->selected_active_module = holes_module->name.str();
927 sel.select(holes_module);
928
929 Pass::call(design, "flatten -wb");
930
931 // TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
932 // instead of per write_xaiger call
933 Pass::call(design, "techmap");
934 Pass::call(design, "aigmap");
935 for (auto cell : holes_module->cells())
936 if (!cell->type.in("$_NOT_", "$_AND_"))
937 log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
938
939 design->selection_stack.pop_back();
940 design->selected_active_module = module->name.str();
941
942 // Move into a new (temporary) design so that "clean" will only
943 // operate (and run checks on) this one module
944 RTLIL::Design *holes_design = new RTLIL::Design;
945 design->modules_.erase(holes_module->name);
946 holes_design->add(holes_module);
947 Pass::call(holes_design, "clean -purge");
948
949 std::stringstream a_buffer;
950 XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
951 writer.write_aiger(a_buffer, false /*ascii_mode*/);
952
953 delete holes_design;
954
955 f << "a";
956 std::string buffer_str = a_buffer.str();
957 int32_t buffer_size_be = to_big_endian(buffer_str.size());
958 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
959 f.write(buffer_str.data(), buffer_str.size());
960
961 log_pop();
962 }
963 }
964
965 f << "h";
966 std::string buffer_str = h_buffer.str();
967 int32_t buffer_size_be = to_big_endian(buffer_str.size());
968 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
969 f.write(buffer_str.data(), buffer_str.size());
970
971 f << "i";
972 buffer_str = i_buffer.str();
973 buffer_size_be = to_big_endian(buffer_str.size());
974 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
975 f.write(buffer_str.data(), buffer_str.size());
976 //f << "o";
977 //buffer_str = o_buffer.str();
978 //buffer_size_be = to_big_endian(buffer_str.size());
979 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
980 //f.write(buffer_str.data(), buffer_str.size());
981
982 f << stringf("Generated by %s\n", yosys_version_str);
983 }
984
985 void write_map(std::ostream &f, bool verbose_map)
986 {
987 dict<int, string> input_lines;
988 dict<int, string> init_lines;
989 dict<int, string> output_lines;
990 dict<int, string> latch_lines;
991 dict<int, string> wire_lines;
992
993 for (auto wire : module->wires())
994 {
995 //if (!verbose_map && wire->name[0] == '$')
996 // continue;
997
998 SigSpec sig = sigmap(wire);
999
1000 for (int i = 0; i < GetSize(wire); i++)
1001 {
1002 RTLIL::SigBit b(wire, i);
1003 if (input_bits.count(b)) {
1004 int a = aig_map.at(b);
1005 log_assert((a & 1) == 0);
1006 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
1007 }
1008
1009 if (output_bits.count(b)) {
1010 int o = ordered_outputs.at(b);
1011 int init = 2;
1012 auto it = init_map.find(b);
1013 if (it != init_map.end())
1014 init = it->second ? 1 : 0;
1015 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
1016 continue;
1017 }
1018
1019 //if (init_inputs.count(sig[i])) {
1020 // int a = init_inputs.at(sig[i]);
1021 // log_assert((a & 1) == 0);
1022 // init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
1023 // continue;
1024 //}
1025
1026 //if (ordered_latches.count(sig[i])) {
1027 // int l = ordered_latches.at(sig[i]);
1028 // if (zinit_mode && (aig_latchinit.at(l) == 1))
1029 // latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
1030 // else
1031 // latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
1032 // continue;
1033 //}
1034
1035 if (verbose_map) {
1036 if (aig_map.count(sig[i]) == 0)
1037 continue;
1038
1039 int a = aig_map.at(sig[i]);
1040 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
1041 }
1042 }
1043 }
1044
1045 input_lines.sort();
1046 for (auto &it : input_lines)
1047 f << it.second;
1048 log_assert(input_lines.size() == input_bits.size());
1049
1050 init_lines.sort();
1051 for (auto &it : init_lines)
1052 f << it.second;
1053
1054 int box_count = 0;
1055 for (auto cell : box_list)
1056 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
1057
1058 output_lines.sort();
1059 if (omode)
1060 output_lines[State::S0] = "output 0 0 $__dummy__\n";
1061 for (auto &it : output_lines)
1062 f << it.second;
1063 log_assert(output_lines.size() == output_bits.size());
1064 if (omode && output_bits.empty())
1065 f << "output " << output_lines.size() << " 0 $__dummy__\n";
1066
1067 latch_lines.sort();
1068 for (auto &it : latch_lines)
1069 f << it.second;
1070
1071 wire_lines.sort();
1072 for (auto &it : wire_lines)
1073 f << it.second;
1074 }
1075 };
1076
1077 struct XAigerBackend : public Backend {
1078 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
1079 void help() YS_OVERRIDE
1080 {
1081 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1082 log("\n");
1083 log(" write_xaiger [options] [filename]\n");
1084 log("\n");
1085 log("Write the current design to an XAIGER file. The design must be flattened and\n");
1086 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
1087 log("\n");
1088 log(" -ascii\n");
1089 log(" write ASCII version of AIGER format\n");
1090 log("\n");
1091 log(" -zinit\n");
1092 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
1093 log(" uninitialized FFs.\n");
1094 log("\n");
1095 log(" -map <filename>\n");
1096 log(" write an extra file with port and latch symbols\n");
1097 log("\n");
1098 log(" -vmap <filename>\n");
1099 log(" like -map, but more verbose\n");
1100 log("\n");
1101 }
1102 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1103 {
1104 bool ascii_mode = false;
1105 bool zinit_mode = false;
1106 bool verbose_map = false;
1107 std::string map_filename;
1108
1109 log_header(design, "Executing XAIGER backend.\n");
1110
1111 size_t argidx;
1112 for (argidx = 1; argidx < args.size(); argidx++)
1113 {
1114 if (args[argidx] == "-ascii") {
1115 ascii_mode = true;
1116 continue;
1117 }
1118 if (args[argidx] == "-zinit") {
1119 zinit_mode = true;
1120 continue;
1121 }
1122 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
1123 map_filename = args[++argidx];
1124 continue;
1125 }
1126 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
1127 map_filename = args[++argidx];
1128 verbose_map = true;
1129 continue;
1130 }
1131 break;
1132 }
1133 extra_args(f, filename, args, argidx, !ascii_mode);
1134
1135 Module *top_module = design->top_module();
1136
1137 if (top_module == nullptr)
1138 log_error("Can't find top module in current design!\n");
1139
1140 XAigerWriter writer(top_module, zinit_mode);
1141 writer.write_aiger(*f, ascii_mode);
1142
1143 if (!map_filename.empty()) {
1144 std::ofstream mapf;
1145 mapf.open(map_filename.c_str(), std::ofstream::trunc);
1146 if (mapf.fail())
1147 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
1148 writer.write_map(mapf, verbose_map);
1149 }
1150 }
1151 } XAigerBackend;
1152
1153 PRIVATE_NAMESPACE_END