2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 // https://stackoverflow.com/a/46137633
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
32 inline static uint32_t bswap32(uint32_t x
)
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value
= number_to_be_reversed
;
36 uint8_t lolo
= (value
>> 0) & 0xFF;
37 uint8_t lohi
= (value
>> 8) & 0xFF;
38 uint8_t hilo
= (value
>> 16) & 0xFF;
39 uint8_t hihi
= (value
>> 24) & 0xFF;
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
53 PRIVATE_NAMESPACE_BEGIN
55 inline int32_t to_big_endian(int32_t i32
) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
61 #error "Unknown endianness"
65 void aiger_encode(std::ostream
&f
, int x
)
70 f
.put((x
& 0x7f) | 0x80);
82 dict
<SigBit
, State
> init_map
;
83 pool
<SigBit
> input_bits
, output_bits
;
84 dict
<SigBit
, SigBit
> not_map
, alias_map
;
85 dict
<SigBit
, pair
<SigBit
, SigBit
>> and_map
;
86 vector
<SigBit
> ci_bits
, co_bits
;
87 dict
<SigBit
, Cell
*> ff_bits
;
88 dict
<SigBit
, float> arrival_times
;
90 vector
<pair
<int, int>> aig_gates
;
91 vector
<int> aig_outputs
;
92 int aig_m
= 0, aig_i
= 0, aig_l
= 0, aig_o
= 0, aig_a
= 0;
94 dict
<SigBit
, int> aig_map
;
95 dict
<SigBit
, int> ordered_outputs
;
97 vector
<Cell
*> box_list
;
99 int mkgate(int a0
, int a1
)
102 aig_gates
.push_back(a0
> a1
? make_pair(a0
, a1
) : make_pair(a1
, a0
));
106 int bit2aig(SigBit bit
)
108 auto it
= aig_map
.find(bit
);
109 if (it
!= aig_map
.end()) {
110 log_assert(it
->second
>= 0);
114 // NB: Cannot use iterator returned from aig_map.insert()
115 // since this function is called recursively
118 if (not_map
.count(bit
)) {
119 a
= bit2aig(not_map
.at(bit
)) ^ 1;
121 if (and_map
.count(bit
)) {
122 auto args
= and_map
.at(bit
);
123 int a0
= bit2aig(args
.first
);
124 int a1
= bit2aig(args
.second
);
127 if (alias_map
.count(bit
)) {
128 a
= bit2aig(alias_map
.at(bit
));
131 if (bit
== State::Sx
|| bit
== State::Sz
) {
132 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
133 a
= aig_map
.at(State::S0
);
141 XAigerWriter(Module
*module
, bool dff_mode
, bool holes_mode
=false) : module(module
), sigmap(module
)
143 pool
<SigBit
> undriven_bits
;
144 pool
<SigBit
> unused_bits
;
146 // promote public wires
147 for (auto wire
: module
->wires())
148 if (wire
->name
[0] == '\\')
151 // promote input wires
152 for (auto wire
: module
->wires())
153 if (wire
->port_input
)
156 // promote keep wires
157 for (auto wire
: module
->wires())
158 if (wire
->get_bool_attribute(ID::keep
))
161 for (auto wire
: module
->wires()) {
162 auto it
= wire
->attributes
.find(ID::init
);
163 for (int i
= 0; i
< GetSize(wire
); i
++)
165 SigBit
wirebit(wire
, i
);
166 SigBit bit
= sigmap(wirebit
);
168 if (bit
.wire
== nullptr) {
169 if (wire
->port_output
) {
170 aig_map
[wirebit
] = (bit
== State::S1
) ? 1 : 0;
171 output_bits
.insert(wirebit
);
176 undriven_bits
.insert(bit
);
177 unused_bits
.insert(bit
);
179 bool scc
= wire
->attributes
.count(ID::abc9_scc
);
180 if (wire
->port_input
|| scc
)
181 input_bits
.insert(bit
);
183 bool keep
= wire
->get_bool_attribute(ID::keep
);
184 if (wire
->port_output
|| keep
|| scc
) {
186 alias_map
[wirebit
] = bit
;
187 output_bits
.insert(wirebit
);
190 if (it
!= wire
->attributes
.end()) {
191 auto s
= it
->second
[i
];
192 if (s
!= State::Sx
) {
193 auto r
= init_map
.insert(std::make_pair(bit
, it
->second
[i
]));
194 if (!r
.second
&& r
.first
->second
!= it
->second
[i
])
195 log_error("Bit '%s' has a conflicting (* init *) value.\n", log_signal(bit
));
203 for (auto cell
: module
->cells()) {
204 if (!cell
->has_keep_attr()) {
205 if (cell
->type
== ID($_NOT_
))
207 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
208 SigBit Y
= sigmap(cell
->getPort(ID::Y
).as_bit());
209 unused_bits
.erase(A
);
210 undriven_bits
.erase(Y
);
215 if (cell
->type
== ID($_AND_
))
217 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
218 SigBit B
= sigmap(cell
->getPort(ID::B
).as_bit());
219 SigBit Y
= sigmap(cell
->getPort(ID::Y
).as_bit());
220 unused_bits
.erase(A
);
221 unused_bits
.erase(B
);
222 undriven_bits
.erase(Y
);
223 and_map
[Y
] = make_pair(A
, B
);
227 if (dff_mode
&& cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)))
229 SigBit D
= sigmap(cell
->getPort(ID::D
).as_bit());
230 SigBit Q
= sigmap(cell
->getPort(ID::Q
).as_bit());
231 unused_bits
.erase(D
);
232 undriven_bits
.erase(Q
);
234 auto r
YS_ATTRIBUTE(unused
) = ff_bits
.insert(std::make_pair(D
, cell
));
235 log_assert(r
.second
);
239 if (cell
->type
.in(ID($specify2
), ID($specify3
), ID($specrule
)))
243 RTLIL::Module
* inst_module
= module
->design
->module(cell
->type
);
245 IdString derived_type
;
246 if (cell
->parameters
.empty())
247 derived_type
= cell
->type
;
249 derived_type
= inst_module
->derive(module
->design
, cell
->parameters
);
250 inst_module
= module
->design
->module(derived_type
);
251 log_assert(inst_module
);
253 bool abc9_flop
= false;
254 if (!cell
->has_keep_attr()) {
255 auto it
= cell
->attributes
.find(ID::abc9_box_seq
);
256 if (it
!= cell
->attributes
.end()) {
257 int abc9_box_seq
= it
->second
.as_int();
258 if (GetSize(box_list
) <= abc9_box_seq
)
259 box_list
.resize(abc9_box_seq
+1);
260 box_list
[abc9_box_seq
] = cell
;
261 // Only flop boxes may have arrival times
262 // (all others are combinatorial)
263 abc9_flop
= inst_module
->get_bool_attribute(ID::abc9_flop
);
269 if (!timing
.count(derived_type
))
270 timing
.setup_module(inst_module
);
271 auto &t
= timing
.at(derived_type
).arrival
;
272 for (const auto &conn
: cell
->connections()) {
273 auto port_wire
= inst_module
->wire(conn
.first
);
274 if (!port_wire
->port_output
)
277 for (int i
= 0; i
< GetSize(conn
.second
); i
++) {
278 auto d
= t
.at(TimingInfo::NameBit(conn
.first
,i
), 0);
284 static std::set
<std::tuple
<IdString
,IdString
,int>> seen
;
285 if (seen
.emplace(derived_type
, conn
.first
, i
).second
) log("%s.%s[%d] abc9_arrival = %d\n",
286 log_id(cell
->type
), log_id(conn
.first
), i
, d
);
289 arrival_times
[conn
.second
[i
]] = d
;
297 if (cell
->type
== ID($__ABC9_DELAY
))
298 log_error("Cell type '%s' not recognised. Check that '+/abc9_model.v' has been read.\n", cell
->type
.c_str());
301 bool cell_known
= inst_module
|| cell
->known();
302 for (const auto &c
: cell
->connections()) {
303 if (c
.second
.is_fully_const()) continue;
304 auto port_wire
= inst_module
? inst_module
->wire(c
.first
) : nullptr;
305 auto is_input
= (port_wire
&& port_wire
->port_input
) || !cell_known
|| cell
->input(c
.first
);
306 auto is_output
= (port_wire
&& port_wire
->port_output
) || !cell_known
|| cell
->output(c
.first
);
307 if (!is_input
&& !is_output
)
308 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c
.first
), log_id(cell
), log_id(cell
->type
));
311 for (auto b
: c
.second
) {
314 // Do not add as PO if bit is already a PI
315 if (input_bits
.count(b
))
317 if (!w
->port_output
|| !cell_known
) {
318 SigBit I
= sigmap(b
);
321 output_bits
.insert(b
);
326 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
329 dict
<IdString
, std::vector
<IdString
>> box_ports
;
330 for (auto cell
: box_list
) {
333 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
334 log_assert(box_module
);
335 log_assert(box_module
->attributes
.count(ID::abc9_box_id
));
337 auto r
= box_ports
.insert(cell
->type
);
339 // Make carry in the last PI, and carry out the last PO
340 // since ABC requires it this way
341 IdString carry_in
, carry_out
;
342 for (const auto &port_name
: box_module
->ports
) {
343 auto w
= box_module
->wire(port_name
);
345 if (w
->get_bool_attribute(ID::abc9_carry
)) {
347 if (carry_in
!= IdString())
348 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module
));
349 carry_in
= port_name
;
351 if (w
->port_output
) {
352 if (carry_out
!= IdString())
353 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module
));
354 carry_out
= port_name
;
358 r
.first
->second
.push_back(port_name
);
361 if (carry_in
!= IdString() && carry_out
== IdString())
362 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module
));
363 if (carry_in
== IdString() && carry_out
!= IdString())
364 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module
));
365 if (carry_in
!= IdString()) {
366 r
.first
->second
.push_back(carry_in
);
367 r
.first
->second
.push_back(carry_out
);
371 for (auto port_name
: r
.first
->second
) {
372 auto w
= box_module
->wire(port_name
);
374 auto rhs
= cell
->connections_
.at(port_name
, SigSpec());
375 rhs
.append(Const(State::Sx
, GetSize(w
)-GetSize(rhs
)));
378 SigBit I
= sigmap(b
);
383 alias_map
[b
] = State::S0
;
387 co_bits
.emplace_back(b
);
388 unused_bits
.erase(I
);
391 for (const auto &b
: rhs
) {
392 SigBit O
= sigmap(b
);
395 ci_bits
.emplace_back(b
);
396 undriven_bits
.erase(O
);
401 for (auto bit
: input_bits
)
402 undriven_bits
.erase(bit
);
403 for (auto bit
: output_bits
)
404 unused_bits
.erase(sigmap(bit
));
405 for (auto bit
: unused_bits
)
406 undriven_bits
.erase(bit
);
408 // Make all undriven bits a primary input
409 for (auto bit
: undriven_bits
) {
410 input_bits
.insert(bit
);
411 undriven_bits
.erase(bit
);
415 struct sort_by_port_id
{
416 bool operator()(const RTLIL::SigBit
& a
, const RTLIL::SigBit
& b
) const {
417 return a
.wire
->port_id
< b
.wire
->port_id
||
418 (a
.wire
->port_id
== b
.wire
->port_id
&& a
.offset
< b
.offset
);
421 input_bits
.sort(sort_by_port_id());
422 output_bits
.sort(sort_by_port_id());
425 aig_map
[State::S0
] = 0;
426 aig_map
[State::S1
] = 1;
428 for (const auto &bit
: input_bits
) {
430 log_assert(!aig_map
.count(bit
));
431 aig_map
[bit
] = 2*aig_m
;
434 for (const auto &i
: ff_bits
) {
435 const Cell
*cell
= i
.second
;
436 const SigBit
&q
= sigmap(cell
->getPort(ID::Q
));
438 log_assert(!aig_map
.count(q
));
439 aig_map
[q
] = 2*aig_m
;
442 for (auto &bit
: ci_bits
) {
444 // 1'bx may exist here due to a box output
445 // that has been padded to its full width
446 if (bit
== State::Sx
)
448 log_assert(!aig_map
.count(bit
));
449 aig_map
[bit
] = 2*aig_m
;
452 for (auto bit
: co_bits
) {
453 ordered_outputs
[bit
] = aig_o
++;
454 aig_outputs
.push_back(bit2aig(bit
));
457 for (const auto &bit
: output_bits
) {
458 ordered_outputs
[bit
] = aig_o
++;
460 // Unlike bit2aig() which checks aig_map first for
461 // inout/scc bits, since aig_map will point to
462 // the PI, first attempt to find the NOT/AND driver
463 // before resorting to an aig_map lookup (which
464 // could be another PO)
465 if (input_bits
.count(bit
)) {
466 if (not_map
.count(bit
)) {
467 aig
= bit2aig(not_map
.at(bit
)) ^ 1;
468 } else if (and_map
.count(bit
)) {
469 auto args
= and_map
.at(bit
);
470 int a0
= bit2aig(args
.first
);
471 int a1
= bit2aig(args
.second
);
472 aig
= mkgate(a0
, a1
);
475 aig
= aig_map
.at(bit
);
479 aig_outputs
.push_back(aig
);
482 for (auto &i
: ff_bits
) {
483 const SigBit
&d
= i
.first
;
485 aig_outputs
.push_back(aig_map
.at(d
));
489 void write_aiger(std::ostream
&f
, bool ascii_mode
)
492 int aig_obcj
= aig_obc
;
493 int aig_obcjf
= aig_obcj
;
495 log_assert(aig_m
== aig_i
+ aig_l
+ aig_a
);
496 log_assert(aig_obcjf
== GetSize(aig_outputs
));
498 f
<< stringf("%s %d %d %d %d %d", ascii_mode
? "aag" : "aig", aig_m
, aig_i
, aig_l
, aig_o
, aig_a
);
503 for (int i
= 0; i
< aig_i
; i
++)
504 f
<< stringf("%d\n", 2*i
+2);
506 for (int i
= 0; i
< aig_obc
; i
++)
507 f
<< stringf("%d\n", aig_outputs
.at(i
));
509 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
512 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
513 f
<< stringf("%d\n", aig_outputs
.at(i
));
515 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
516 f
<< stringf("%d\n", aig_outputs
.at(i
));
518 for (int i
= 0; i
< aig_a
; i
++)
519 f
<< stringf("%d %d %d\n", 2*(aig_i
+aig_l
+i
)+2, aig_gates
.at(i
).first
, aig_gates
.at(i
).second
);
523 for (int i
= 0; i
< aig_obc
; i
++)
524 f
<< stringf("%d\n", aig_outputs
.at(i
));
526 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
529 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
530 f
<< stringf("%d\n", aig_outputs
.at(i
));
532 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
533 f
<< stringf("%d\n", aig_outputs
.at(i
));
535 for (int i
= 0; i
< aig_a
; i
++) {
536 int lhs
= 2*(aig_i
+aig_l
+i
)+2;
537 int rhs0
= aig_gates
.at(i
).first
;
538 int rhs1
= aig_gates
.at(i
).second
;
539 int delta0
= lhs
- rhs0
;
540 int delta1
= rhs0
- rhs1
;
541 aiger_encode(f
, delta0
);
542 aiger_encode(f
, delta1
);
548 auto write_buffer
= [](std::stringstream
&buffer
, int i32
) {
549 int32_t i32_be
= to_big_endian(i32
);
550 buffer
.write(reinterpret_cast<const char*>(&i32_be
), sizeof(i32_be
));
552 std::stringstream h_buffer
;
553 auto write_h_buffer
= std::bind(write_buffer
, std::ref(h_buffer
), std::placeholders::_1
);
555 log_debug("ciNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
) + GetSize(ci_bits
));
556 write_h_buffer(input_bits
.size() + ff_bits
.size() + ci_bits
.size());
557 log_debug("coNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
) + GetSize(co_bits
));
558 write_h_buffer(output_bits
.size() + GetSize(ff_bits
) + GetSize(co_bits
));
559 log_debug("piNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
));
560 write_h_buffer(input_bits
.size() + ff_bits
.size());
561 log_debug("poNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
));
562 write_h_buffer(output_bits
.size() + ff_bits
.size());
563 log_debug("boxNum = %d\n", GetSize(box_list
));
564 write_h_buffer(box_list
.size());
566 auto write_buffer_float
= [](std::stringstream
&buffer
, float f32
) {
567 buffer
.write(reinterpret_cast<const char*>(&f32
), sizeof(f32
));
569 std::stringstream i_buffer
;
570 auto write_i_buffer
= std::bind(write_buffer_float
, std::ref(i_buffer
), std::placeholders::_1
);
571 for (auto bit
: input_bits
)
572 write_i_buffer(arrival_times
.at(bit
, 0));
573 //std::stringstream o_buffer;
574 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
575 //for (auto bit : output_bits)
576 // write_o_buffer(0);
578 if (!box_list
.empty() || !ff_bits
.empty()) {
579 dict
<IdString
, std::tuple
<int,int,int>> cell_cache
;
582 for (auto cell
: box_list
) {
585 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
586 log_assert(box_module
);
588 IdString derived_type
;
589 if (cell
->parameters
.empty())
590 derived_type
= cell
->type
;
592 derived_type
= box_module
->derive(module
->design
, cell
->parameters
);
593 box_module
= box_module
->design
->module(derived_type
);
594 log_assert(box_module
);
596 auto r
= cell_cache
.insert(derived_type
);
597 auto &v
= r
.first
->second
;
599 int box_inputs
= 0, box_outputs
= 0;
600 for (auto port_name
: box_module
->ports
) {
601 RTLIL::Wire
*w
= box_module
->wire(port_name
);
604 box_inputs
+= GetSize(w
);
606 box_outputs
+= GetSize(w
);
609 std::get
<0>(v
) = box_inputs
;
610 std::get
<1>(v
) = box_outputs
;
611 std::get
<2>(v
) = box_module
->attributes
.at(ID::abc9_box_id
).as_int();
614 write_h_buffer(std::get
<0>(v
));
615 write_h_buffer(std::get
<1>(v
));
616 write_h_buffer(std::get
<2>(v
));
617 write_h_buffer(box_count
++);
620 std::stringstream r_buffer
;
621 auto write_r_buffer
= std::bind(write_buffer
, std::ref(r_buffer
), std::placeholders::_1
);
622 log_debug("flopNum = %d\n", GetSize(ff_bits
));
623 write_r_buffer(ff_bits
.size());
625 std::stringstream s_buffer
;
626 auto write_s_buffer
= std::bind(write_buffer
, std::ref(s_buffer
), std::placeholders::_1
);
627 write_s_buffer(ff_bits
.size());
629 dict
<SigBit
, int> clk_to_mergeability
;
631 for (const auto &i
: ff_bits
) {
632 const SigBit
&d
= i
.first
;
633 const Cell
*cell
= i
.second
;
635 log_assert(cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)));
637 SigBit clock
= sigmap(cell
->getPort(ID::C
));
638 auto r
= clk_to_mergeability
.insert(std::make_pair(clock
, clk_to_mergeability
.size() + 1));
639 int mergeability
= r
.first
->second
;
640 log_assert(mergeability
> 0);
641 if (cell
->type
== ID($_DFF_N_
))
642 write_r_buffer(-mergeability
);
643 else if (cell
->type
== ID($_DFF_P_
))
644 write_r_buffer(mergeability
);
647 SigBit Q
= sigmap(cell
->getPort(ID::Q
));
648 State init
= init_map
.at(Q
, State::Sx
);
649 if (init
== State::S1
)
651 else if (init
== State::S0
)
654 log_assert(init
== State::Sx
);
658 // Use arrival time from output of flop box
659 write_i_buffer(arrival_times
.at(d
, 0));
664 std::string buffer_str
= r_buffer
.str();
665 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
666 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
667 f
.write(buffer_str
.data(), buffer_str
.size());
670 buffer_str
= s_buffer
.str();
671 buffer_size_be
= to_big_endian(buffer_str
.size());
672 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
673 f
.write(buffer_str
.data(), buffer_str
.size());
675 RTLIL::Module
*holes_module
= module
->design
->module(stringf("%s$holes", module
->name
.c_str()));
677 std::stringstream a_buffer
;
678 XAigerWriter
writer(holes_module
, false /* dff_mode */, true /* holes_mode */);
679 writer
.write_aiger(a_buffer
, false /*ascii_mode*/);
682 std::string buffer_str
= a_buffer
.str();
683 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
684 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
685 f
.write(buffer_str
.data(), buffer_str
.size());
690 std::string buffer_str
= h_buffer
.str();
691 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
692 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
693 f
.write(buffer_str
.data(), buffer_str
.size());
696 buffer_str
= i_buffer
.str();
697 buffer_size_be
= to_big_endian(buffer_str
.size());
698 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
699 f
.write(buffer_str
.data(), buffer_str
.size());
701 //buffer_str = o_buffer.str();
702 //buffer_size_be = to_big_endian(buffer_str.size());
703 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
704 //f.write(buffer_str.data(), buffer_str.size());
706 f
<< stringf("Generated by %s\n", yosys_version_str
);
708 module
->design
->scratchpad_set_int("write_xaiger.num_ands", and_map
.size());
709 module
->design
->scratchpad_set_int("write_xaiger.num_wires", aig_map
.size());
710 module
->design
->scratchpad_set_int("write_xaiger.num_inputs", input_bits
.size());
711 module
->design
->scratchpad_set_int("write_xaiger.num_outputs", output_bits
.size());
714 void write_map(std::ostream
&f
)
716 dict
<int, string
> input_lines
;
717 dict
<int, string
> output_lines
;
719 for (auto wire
: module
->wires())
721 SigSpec sig
= sigmap(wire
);
723 for (int i
= 0; i
< GetSize(wire
); i
++)
725 RTLIL::SigBit
b(wire
, i
);
726 if (input_bits
.count(b
)) {
727 int a
= aig_map
.at(b
);
728 log_assert((a
& 1) == 0);
729 input_lines
[a
] += stringf("input %d %d %s\n", (a
>> 1)-1, wire
->start_offset
+i
, log_id(wire
));
732 if (output_bits
.count(b
)) {
733 int o
= ordered_outputs
.at(b
);
734 output_lines
[o
] += stringf("output %d %d %s\n", o
- GetSize(co_bits
), wire
->start_offset
+i
, log_id(wire
));
741 for (auto &it
: input_lines
)
743 log_assert(input_lines
.size() == input_bits
.size());
746 for (auto cell
: box_list
)
747 f
<< stringf("box %d %d %s\n", box_count
++, 0, log_id(cell
->name
));
750 for (auto &it
: output_lines
)
752 log_assert(output_lines
.size() == output_bits
.size());
756 struct XAigerBackend
: public Backend
{
757 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
758 void help() YS_OVERRIDE
760 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
762 log(" write_xaiger [options] [filename]\n");
764 log("Write the top module (according to the (* top *) attribute or if only one module\n");
765 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_DFF_N_,\n");
766 log(" $_DFF_P_, or non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
767 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
768 log("module, if it exists.\n");
771 log(" write ASCII version of AIGER format\n");
773 log(" -map <filename>\n");
774 log(" write an extra file with port and box symbols\n");
777 log(" write $_DFF_[NP]_ cells\n");
780 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
782 bool ascii_mode
= false, dff_mode
= false;
783 std::string map_filename
;
785 log_header(design
, "Executing XAIGER backend.\n");
788 for (argidx
= 1; argidx
< args
.size(); argidx
++)
790 if (args
[argidx
] == "-ascii") {
794 if (map_filename
.empty() && args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
795 map_filename
= args
[++argidx
];
798 if (args
[argidx
] == "-dff") {
804 extra_args(f
, filename
, args
, argidx
, !ascii_mode
);
806 Module
*top_module
= design
->top_module();
808 if (top_module
== nullptr)
809 log_error("Can't find top module in current design!\n");
811 if (!design
->selected_whole_module(top_module
))
812 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module
));
814 if (!top_module
->processes
.empty())
815 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module
));
816 if (!top_module
->memories
.empty())
817 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module
));
819 XAigerWriter
writer(top_module
, dff_mode
);
820 writer
.write_aiger(*f
, ascii_mode
);
822 if (!map_filename
.empty()) {
824 mapf
.open(map_filename
.c_str(), std::ofstream::trunc
);
826 log_error("Can't open file `%s' for writing: %s\n", map_filename
.c_str(), strerror(errno
));
827 writer
.write_map(mapf
);
832 PRIVATE_NAMESPACE_END