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abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
51
52 USING_YOSYS_NAMESPACE
53 PRIVATE_NAMESPACE_BEGIN
54
55 inline int32_t to_big_endian(int32_t i32) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 return bswap32(i32);
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
59 return i32;
60 #else
61 #error "Unknown endianness"
62 #endif
63 }
64
65 void aiger_encode(std::ostream &f, int x)
66 {
67 log_assert(x >= 0);
68
69 while (x & ~0x7f) {
70 f.put((x & 0x7f) | 0x80);
71 x = x >> 7;
72 }
73
74 f.put(x);
75 }
76
77 struct XAigerWriter
78 {
79 Module *module;
80 SigMap sigmap;
81
82 pool<SigBit> input_bits, output_bits;
83 dict<SigBit, SigBit> not_map, alias_map;
84 dict<SigBit, pair<SigBit, SigBit>> and_map;
85 vector<SigBit> ci_bits, co_bits;
86 dict<SigBit, Cell*> ff_bits;
87 dict<SigBit, float> arrival_times;
88
89 vector<pair<int, int>> aig_gates;
90 vector<int> aig_outputs;
91 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
92
93 dict<SigBit, int> aig_map;
94 dict<SigBit, int> ordered_outputs;
95
96 vector<Cell*> box_list;
97
98 int mkgate(int a0, int a1)
99 {
100 aig_m++, aig_a++;
101 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
102 return 2*aig_m;
103 }
104
105 int bit2aig(SigBit bit)
106 {
107 auto it = aig_map.find(bit);
108 if (it != aig_map.end()) {
109 log_assert(it->second >= 0);
110 return it->second;
111 }
112
113 // NB: Cannot use iterator returned from aig_map.insert()
114 // since this function is called recursively
115
116 int a = -1;
117 if (not_map.count(bit)) {
118 a = bit2aig(not_map.at(bit)) ^ 1;
119 } else
120 if (and_map.count(bit)) {
121 auto args = and_map.at(bit);
122 int a0 = bit2aig(args.first);
123 int a1 = bit2aig(args.second);
124 a = mkgate(a0, a1);
125 } else
126 if (alias_map.count(bit)) {
127 a = bit2aig(alias_map.at(bit));
128 }
129
130 if (bit == State::Sx || bit == State::Sz) {
131 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
132 a = aig_map.at(State::S0);
133 }
134
135 log_assert(a >= 0);
136 aig_map[bit] = a;
137 return a;
138 }
139
140 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
141 {
142 pool<SigBit> undriven_bits;
143 pool<SigBit> unused_bits;
144
145 // promote public wires
146 for (auto wire : module->wires())
147 if (wire->name[0] == '\\')
148 sigmap.add(wire);
149
150 // promote input wires
151 for (auto wire : module->wires())
152 if (wire->port_input)
153 sigmap.add(wire);
154
155 // promote keep wires
156 for (auto wire : module->wires())
157 if (wire->get_bool_attribute(ID::keep))
158 sigmap.add(wire);
159
160 for (auto wire : module->wires())
161 for (int i = 0; i < GetSize(wire); i++)
162 {
163 SigBit wirebit(wire, i);
164 SigBit bit = sigmap(wirebit);
165
166 if (bit.wire == nullptr) {
167 if (wire->port_output) {
168 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
169 output_bits.insert(wirebit);
170 }
171 continue;
172 }
173
174 undriven_bits.insert(bit);
175 unused_bits.insert(bit);
176
177 bool scc = wire->attributes.count(ID(abc9_scc));
178 if (wire->port_input || scc)
179 input_bits.insert(bit);
180
181 bool keep = wire->get_bool_attribute(ID::keep);
182 if (wire->port_output || keep || scc) {
183 if (bit != wirebit)
184 alias_map[wirebit] = bit;
185 output_bits.insert(wirebit);
186 }
187 }
188
189 TimingInfo timing;
190
191 for (auto cell : module->cells()) {
192 if (!cell->has_keep_attr()) {
193 if (cell->type == "$_NOT_")
194 {
195 SigBit A = sigmap(cell->getPort("\\A").as_bit());
196 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
197 unused_bits.erase(A);
198 undriven_bits.erase(Y);
199 not_map[Y] = A;
200 continue;
201 }
202
203 if (cell->type == "$_AND_")
204 {
205 SigBit A = sigmap(cell->getPort("\\A").as_bit());
206 SigBit B = sigmap(cell->getPort("\\B").as_bit());
207 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
208 unused_bits.erase(A);
209 unused_bits.erase(B);
210 undriven_bits.erase(Y);
211 and_map[Y] = make_pair(A, B);
212 continue;
213 }
214
215 if (cell->type == "$__ABC9_FF_" &&
216 // The presence of an abc9_mergeability attribute indicates
217 // that we do want to pass this flop to ABC
218 cell->attributes.count("\\abc9_mergeability"))
219 {
220 SigBit D = sigmap(cell->getPort("\\D").as_bit());
221 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
222 unused_bits.erase(D);
223 undriven_bits.erase(Q);
224 alias_map[Q] = D;
225 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
226 log_assert(r.second);
227 if (input_bits.erase(Q))
228 log_assert(Q.wire->attributes.count(ID::keep));
229 continue;
230 }
231
232 if (cell->type.in("$specify2", "$specify3", "$specrule"))
233 continue;
234 }
235
236 RTLIL::Module* inst_module = module->design->module(cell->type);
237 if (inst_module) {
238 IdString derived_type = inst_module->derive(module->design, cell->parameters);
239 inst_module = module->design->module(derived_type);
240 log_assert(inst_module);
241
242 bool abc9_flop = false;
243 if (!cell->has_keep_attr()) {
244 auto it = cell->attributes.find("\\abc9_box_seq");
245 if (it != cell->attributes.end()) {
246 int abc9_box_seq = it->second.as_int();
247 if (GetSize(box_list) <= abc9_box_seq)
248 box_list.resize(abc9_box_seq+1);
249 box_list[abc9_box_seq] = cell;
250 // Only flop boxes may have arrival times
251 // (all others are combinatorial)
252 abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
253 if (!abc9_flop)
254 continue;
255 }
256 }
257
258 if (!timing.count(derived_type))
259 timing.setup_module(inst_module);
260 auto &t = timing.at(derived_type).arrival;
261 for (const auto &conn : cell->connections()) {
262 auto port_wire = inst_module->wire(conn.first);
263 if (!port_wire->port_output)
264 continue;
265
266 for (int i = 0; i < GetSize(conn.second); i++) {
267 auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
268 if (d == 0)
269 continue;
270
271 #ifndef NDEBUG
272 if (ys_debug(1)) {
273 static std::set<std::tuple<IdString,IdString,int>> seen;
274 if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
275 log_id(cell->type), log_id(conn.first), i, d);
276 }
277 #endif
278 arrival_times[conn.second[i]] = d;
279 }
280 }
281
282 if (abc9_flop)
283 continue;
284 }
285
286 bool cell_known = inst_module || cell->known();
287 for (const auto &c : cell->connections()) {
288 if (c.second.is_fully_const()) continue;
289 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
290 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
291 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
292 if (!is_input && !is_output)
293 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
294
295 if (is_input)
296 for (auto b : c.second) {
297 Wire *w = b.wire;
298 if (!w) continue;
299 // Do not add as PO if bit is already a PI
300 if (input_bits.count(b))
301 continue;
302 if (!w->port_output || !cell_known) {
303 SigBit I = sigmap(b);
304 if (I != b)
305 alias_map[b] = I;
306 output_bits.insert(b);
307 }
308 }
309 }
310
311 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
312 }
313
314 dict<IdString, std::vector<IdString>> box_ports;
315 for (auto cell : box_list) {
316 log_assert(cell);
317
318 RTLIL::Module* box_module = module->design->module(cell->type);
319 log_assert(box_module);
320 log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
321
322 auto r = box_ports.insert(cell->type);
323 if (r.second) {
324 // Make carry in the last PI, and carry out the last PO
325 // since ABC requires it this way
326 IdString carry_in, carry_out;
327 for (const auto &port_name : box_module->ports) {
328 auto w = box_module->wire(port_name);
329 log_assert(w);
330 if (w->get_bool_attribute("\\abc9_carry")) {
331 if (w->port_input) {
332 if (carry_in != IdString())
333 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
334 carry_in = port_name;
335 }
336 if (w->port_output) {
337 if (carry_out != IdString())
338 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
339 carry_out = port_name;
340 }
341 }
342 else
343 r.first->second.push_back(port_name);
344 }
345
346 if (carry_in != IdString() && carry_out == IdString())
347 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
348 if (carry_in == IdString() && carry_out != IdString())
349 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
350 if (carry_in != IdString()) {
351 r.first->second.push_back(carry_in);
352 r.first->second.push_back(carry_out);
353 }
354 }
355
356 for (auto port_name : r.first->second) {
357 auto w = box_module->wire(port_name);
358 log_assert(w);
359 auto rhs = cell->connections_.at(port_name, SigSpec());
360 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
361 if (w->port_input)
362 for (auto b : rhs) {
363 SigBit I = sigmap(b);
364 if (b == RTLIL::Sx)
365 b = State::S0;
366 else if (I != b) {
367 if (I == RTLIL::Sx)
368 alias_map[b] = State::S0;
369 else
370 alias_map[b] = I;
371 }
372 co_bits.emplace_back(b);
373 unused_bits.erase(I);
374 }
375 if (w->port_output)
376 for (const auto &b : rhs) {
377 SigBit O = sigmap(b);
378 if (O != b)
379 alias_map[O] = b;
380 ci_bits.emplace_back(b);
381 undriven_bits.erase(O);
382 // If PI and CI, then must be a (* keep *) wire
383 if (input_bits.erase(O)) {
384 log_assert(output_bits.count(O));
385 log_assert(O.wire->get_bool_attribute(ID::keep));
386 }
387 }
388 }
389
390 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
391 if (box_module->get_bool_attribute("\\abc9_flop")) {
392 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
393 if (rhs.empty())
394 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
395
396 for (auto b : rhs) {
397 SigBit I = sigmap(b);
398 if (b == RTLIL::Sx)
399 b = State::S0;
400 else if (I != b) {
401 if (I == RTLIL::Sx)
402 alias_map[b] = State::S0;
403 else
404 alias_map[b] = I;
405 }
406 co_bits.emplace_back(b);
407 unused_bits.erase(I);
408 }
409 }
410 }
411
412 for (auto bit : input_bits)
413 undriven_bits.erase(bit);
414 for (auto bit : output_bits)
415 unused_bits.erase(sigmap(bit));
416 for (auto bit : unused_bits)
417 undriven_bits.erase(bit);
418
419 // Make all undriven bits a primary input
420 for (auto bit : undriven_bits) {
421 input_bits.insert(bit);
422 undriven_bits.erase(bit);
423 }
424
425 if (holes_mode) {
426 struct sort_by_port_id {
427 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
428 return a.wire->port_id < b.wire->port_id ||
429 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
430 }
431 };
432 input_bits.sort(sort_by_port_id());
433 output_bits.sort(sort_by_port_id());
434 }
435
436 aig_map[State::S0] = 0;
437 aig_map[State::S1] = 1;
438
439 for (const auto &bit : input_bits) {
440 aig_m++, aig_i++;
441 log_assert(!aig_map.count(bit));
442 aig_map[bit] = 2*aig_m;
443 }
444
445 for (const auto &i : ff_bits) {
446 const Cell *cell = i.second;
447 const SigBit &q = sigmap(cell->getPort("\\Q"));
448 aig_m++, aig_i++;
449 log_assert(!aig_map.count(q));
450 aig_map[q] = 2*aig_m;
451 }
452
453 for (auto &bit : ci_bits) {
454 aig_m++, aig_i++;
455 // 1'bx may exist here due to a box output
456 // that has been padded to its full width
457 if (bit == State::Sx)
458 continue;
459 log_assert(!aig_map.count(bit));
460 aig_map[bit] = 2*aig_m;
461 }
462
463 for (auto bit : co_bits) {
464 ordered_outputs[bit] = aig_o++;
465 aig_outputs.push_back(bit2aig(bit));
466 }
467
468 for (const auto &bit : output_bits) {
469 ordered_outputs[bit] = aig_o++;
470 int aig;
471 // Unlike bit2aig() which checks aig_map first, for
472 // inout/keep bits, since aig_map will point to
473 // the PI, first attempt to find the NOT/AND driver
474 // before resorting to an aig_map lookup (which
475 // could be another PO)
476 if (input_bits.count(bit)) {
477 if (not_map.count(bit)) {
478 aig = bit2aig(not_map.at(bit)) ^ 1;
479 } else if (and_map.count(bit)) {
480 auto args = and_map.at(bit);
481 int a0 = bit2aig(args.first);
482 int a1 = bit2aig(args.second);
483 aig = mkgate(a0, a1);
484 }
485 else
486 aig = aig_map.at(bit);
487 }
488 else
489 aig = bit2aig(bit);
490 aig_outputs.push_back(aig);
491 }
492
493 for (auto &i : ff_bits) {
494 const SigBit &d = i.first;
495 aig_o++;
496 aig_outputs.push_back(aig_map.at(d));
497 }
498 }
499
500 void write_aiger(std::ostream &f, bool ascii_mode)
501 {
502 int aig_obc = aig_o;
503 int aig_obcj = aig_obc;
504 int aig_obcjf = aig_obcj;
505
506 log_assert(aig_m == aig_i + aig_l + aig_a);
507 log_assert(aig_obcjf == GetSize(aig_outputs));
508
509 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
510 f << stringf("\n");
511
512 if (ascii_mode)
513 {
514 for (int i = 0; i < aig_i; i++)
515 f << stringf("%d\n", 2*i+2);
516
517 for (int i = 0; i < aig_obc; i++)
518 f << stringf("%d\n", aig_outputs.at(i));
519
520 for (int i = aig_obc; i < aig_obcj; i++)
521 f << stringf("1\n");
522
523 for (int i = aig_obc; i < aig_obcj; i++)
524 f << stringf("%d\n", aig_outputs.at(i));
525
526 for (int i = aig_obcj; i < aig_obcjf; i++)
527 f << stringf("%d\n", aig_outputs.at(i));
528
529 for (int i = 0; i < aig_a; i++)
530 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
531 }
532 else
533 {
534 for (int i = 0; i < aig_obc; i++)
535 f << stringf("%d\n", aig_outputs.at(i));
536
537 for (int i = aig_obc; i < aig_obcj; i++)
538 f << stringf("1\n");
539
540 for (int i = aig_obc; i < aig_obcj; i++)
541 f << stringf("%d\n", aig_outputs.at(i));
542
543 for (int i = aig_obcj; i < aig_obcjf; i++)
544 f << stringf("%d\n", aig_outputs.at(i));
545
546 for (int i = 0; i < aig_a; i++) {
547 int lhs = 2*(aig_i+aig_l+i)+2;
548 int rhs0 = aig_gates.at(i).first;
549 int rhs1 = aig_gates.at(i).second;
550 int delta0 = lhs - rhs0;
551 int delta1 = rhs0 - rhs1;
552 aiger_encode(f, delta0);
553 aiger_encode(f, delta1);
554 }
555 }
556
557 f << "c";
558
559 auto write_buffer = [](std::stringstream &buffer, int i32) {
560 int32_t i32_be = to_big_endian(i32);
561 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
562 };
563 std::stringstream h_buffer;
564 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
565 write_h_buffer(1);
566 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
567 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
568 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
569 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
570 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
571 write_h_buffer(input_bits.size() + ff_bits.size());
572 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
573 write_h_buffer(output_bits.size() + ff_bits.size());
574 log_debug("boxNum = %d\n", GetSize(box_list));
575 write_h_buffer(box_list.size());
576
577 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
578 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
579 };
580 std::stringstream i_buffer;
581 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
582 for (auto bit : input_bits)
583 write_i_buffer(arrival_times.at(bit, 0));
584 //std::stringstream o_buffer;
585 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
586 //for (auto bit : output_bits)
587 // write_o_buffer(0);
588
589 if (!box_list.empty() || !ff_bits.empty()) {
590 dict<IdString, std::tuple<int,int,int>> cell_cache;
591
592 int box_count = 0;
593 for (auto cell : box_list) {
594 log_assert(cell);
595
596 RTLIL::Module* box_module = module->design->module(cell->type);
597 log_assert(box_module);
598
599 IdString derived_type = box_module->derive(box_module->design, cell->parameters);
600 box_module = box_module->design->module(derived_type);
601 log_assert(box_module);
602
603 auto r = cell_cache.insert(derived_type);
604 auto &v = r.first->second;
605 if (r.second) {
606 int box_inputs = 0, box_outputs = 0;
607 for (auto port_name : box_module->ports) {
608 RTLIL::Wire *w = box_module->wire(port_name);
609 log_assert(w);
610 if (w->port_input)
611 box_inputs += GetSize(w);
612 if (w->port_output)
613 box_outputs += GetSize(w);
614 }
615
616 // For flops only, create an extra 1-bit input that drives a new wire
617 // called "<cell>.abc9_ff.Q" that is used below
618 if (box_module->get_bool_attribute("\\abc9_flop"))
619 box_inputs++;
620
621 std::get<0>(v) = box_inputs;
622 std::get<1>(v) = box_outputs;
623 std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
624 }
625
626 write_h_buffer(std::get<0>(v));
627 write_h_buffer(std::get<1>(v));
628 write_h_buffer(std::get<2>(v));
629 write_h_buffer(box_count++);
630 }
631
632 std::stringstream r_buffer;
633 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
634 log_debug("flopNum = %d\n", GetSize(ff_bits));
635 write_r_buffer(ff_bits.size());
636
637 std::stringstream s_buffer;
638 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
639 write_s_buffer(ff_bits.size());
640
641 for (const auto &i : ff_bits) {
642 const SigBit &d = i.first;
643 const Cell *cell = i.second;
644
645 int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
646 log_assert(mergeability > 0);
647 write_r_buffer(mergeability);
648
649 Const init = cell->attributes.at(ID(abc9_init), State::Sx);
650 log_assert(GetSize(init) == 1);
651 if (init == State::S1)
652 write_s_buffer(1);
653 else if (init == State::S0)
654 write_s_buffer(0);
655 else {
656 log_assert(init == State::Sx);
657 write_s_buffer(0);
658 }
659
660 // Use arrival time from output of flop box
661 write_i_buffer(arrival_times.at(d, 0));
662 //write_o_buffer(0);
663 }
664
665 f << "r";
666 std::string buffer_str = r_buffer.str();
667 int32_t buffer_size_be = to_big_endian(buffer_str.size());
668 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
669 f.write(buffer_str.data(), buffer_str.size());
670
671 f << "s";
672 buffer_str = s_buffer.str();
673 buffer_size_be = to_big_endian(buffer_str.size());
674 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
675 f.write(buffer_str.data(), buffer_str.size());
676
677 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
678 if (holes_module) {
679 std::stringstream a_buffer;
680 XAigerWriter writer(holes_module, true /* holes_mode */);
681 writer.write_aiger(a_buffer, false /*ascii_mode*/);
682
683 f << "a";
684 std::string buffer_str = a_buffer.str();
685 int32_t buffer_size_be = to_big_endian(buffer_str.size());
686 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
687 f.write(buffer_str.data(), buffer_str.size());
688 }
689 }
690
691 f << "h";
692 std::string buffer_str = h_buffer.str();
693 int32_t buffer_size_be = to_big_endian(buffer_str.size());
694 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
695 f.write(buffer_str.data(), buffer_str.size());
696
697 f << "i";
698 buffer_str = i_buffer.str();
699 buffer_size_be = to_big_endian(buffer_str.size());
700 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
701 f.write(buffer_str.data(), buffer_str.size());
702 //f << "o";
703 //buffer_str = o_buffer.str();
704 //buffer_size_be = to_big_endian(buffer_str.size());
705 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
706 //f.write(buffer_str.data(), buffer_str.size());
707
708 f << stringf("Generated by %s\n", yosys_version_str);
709
710 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
711 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
712 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
713 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
714 }
715
716 void write_map(std::ostream &f)
717 {
718 dict<int, string> input_lines;
719 dict<int, string> output_lines;
720
721 for (auto wire : module->wires())
722 {
723 SigSpec sig = sigmap(wire);
724
725 for (int i = 0; i < GetSize(wire); i++)
726 {
727 RTLIL::SigBit b(wire, i);
728 if (input_bits.count(b)) {
729 int a = aig_map.at(b);
730 log_assert((a & 1) == 0);
731 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
732 }
733
734 if (output_bits.count(b)) {
735 int o = ordered_outputs.at(b);
736 int init = 2;
737 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
738 continue;
739 }
740 }
741 }
742
743 input_lines.sort();
744 for (auto &it : input_lines)
745 f << it.second;
746 log_assert(input_lines.size() == input_bits.size());
747
748 int box_count = 0;
749 for (auto cell : box_list)
750 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
751
752 output_lines.sort();
753 for (auto &it : output_lines)
754 f << it.second;
755 log_assert(output_lines.size() == output_bits.size());
756 }
757 };
758
759 struct XAigerBackend : public Backend {
760 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
761 void help() YS_OVERRIDE
762 {
763 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
764 log("\n");
765 log(" write_xaiger [options] [filename]\n");
766 log("\n");
767 log("Write the top module (according to the (* top *) attribute or if only one module\n");
768 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
769 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
770 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
771 log("module, if it exists.\n");
772 log("\n");
773 log(" -ascii\n");
774 log(" write ASCII version of AIGER format\n");
775 log("\n");
776 log(" -map <filename>\n");
777 log(" write an extra file with port and box symbols\n");
778 log("\n");
779 }
780 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
781 {
782 bool ascii_mode = false;
783 std::string map_filename;
784
785 log_header(design, "Executing XAIGER backend.\n");
786
787 size_t argidx;
788 for (argidx = 1; argidx < args.size(); argidx++)
789 {
790 if (args[argidx] == "-ascii") {
791 ascii_mode = true;
792 continue;
793 }
794 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
795 map_filename = args[++argidx];
796 continue;
797 }
798 break;
799 }
800 extra_args(f, filename, args, argidx, !ascii_mode);
801
802 Module *top_module = design->top_module();
803
804 if (top_module == nullptr)
805 log_error("Can't find top module in current design!\n");
806
807 if (!design->selected_whole_module(top_module))
808 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
809
810 if (!top_module->processes.empty())
811 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
812 if (!top_module->memories.empty())
813 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
814
815 XAigerWriter writer(top_module);
816 writer.write_aiger(*f, ascii_mode);
817
818 if (!map_filename.empty()) {
819 std::ofstream mapf;
820 mapf.open(map_filename.c_str(), std::ofstream::trunc);
821 if (mapf.fail())
822 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
823 writer.write_map(mapf);
824 }
825 }
826 } XAigerBackend;
827
828 PRIVATE_NAMESPACE_END