2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 // https://stackoverflow.com/a/46137633
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
32 inline static uint32_t bswap32(uint32_t x
)
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value
= number_to_be_reversed
;
36 uint8_t lolo
= (value
>> 0) & 0xFF;
37 uint8_t lohi
= (value
>> 8) & 0xFF;
38 uint8_t hilo
= (value
>> 16) & 0xFF;
39 uint8_t hihi
= (value
>> 24) & 0xFF;
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
53 PRIVATE_NAMESPACE_BEGIN
55 inline int32_t to_big_endian(int32_t i32
) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
61 #error "Unknown endianness"
65 void aiger_encode(std::ostream
&f
, int x
)
70 f
.put((x
& 0x7f) | 0x80);
82 pool
<SigBit
> input_bits
, output_bits
;
83 dict
<SigBit
, SigBit
> not_map
, alias_map
;
84 dict
<SigBit
, pair
<SigBit
, SigBit
>> and_map
;
85 vector
<SigBit
> ci_bits
, co_bits
;
86 dict
<SigBit
, Cell
*> ff_bits
;
87 dict
<SigBit
, float> arrival_times
;
89 vector
<pair
<int, int>> aig_gates
;
90 vector
<int> aig_outputs
;
91 int aig_m
= 0, aig_i
= 0, aig_l
= 0, aig_o
= 0, aig_a
= 0;
93 dict
<SigBit
, int> aig_map
;
94 dict
<SigBit
, int> ordered_outputs
;
96 vector
<Cell
*> box_list
;
98 int mkgate(int a0
, int a1
)
101 aig_gates
.push_back(a0
> a1
? make_pair(a0
, a1
) : make_pair(a1
, a0
));
105 int bit2aig(SigBit bit
)
107 auto it
= aig_map
.find(bit
);
108 if (it
!= aig_map
.end()) {
109 log_assert(it
->second
>= 0);
113 // NB: Cannot use iterator returned from aig_map.insert()
114 // since this function is called recursively
117 if (not_map
.count(bit
)) {
118 a
= bit2aig(not_map
.at(bit
)) ^ 1;
120 if (and_map
.count(bit
)) {
121 auto args
= and_map
.at(bit
);
122 int a0
= bit2aig(args
.first
);
123 int a1
= bit2aig(args
.second
);
126 if (alias_map
.count(bit
)) {
127 a
= bit2aig(alias_map
.at(bit
));
130 if (bit
== State::Sx
|| bit
== State::Sz
) {
131 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
132 a
= aig_map
.at(State::S0
);
140 XAigerWriter(Module
*module
, bool dff_mode
, bool holes_mode
=false) : module(module
), sigmap(module
)
142 pool
<SigBit
> undriven_bits
;
143 pool
<SigBit
> unused_bits
;
145 // promote public wires
146 for (auto wire
: module
->wires())
147 if (wire
->name
[0] == '\\')
150 // promote input wires
151 for (auto wire
: module
->wires())
152 if (wire
->port_input
)
155 // promote keep wires
156 for (auto wire
: module
->wires())
157 if (wire
->get_bool_attribute(ID::keep
))
160 for (auto wire
: module
->wires())
161 for (int i
= 0; i
< GetSize(wire
); i
++)
163 SigBit
wirebit(wire
, i
);
164 SigBit bit
= sigmap(wirebit
);
166 if (bit
.wire
== nullptr) {
167 if (wire
->port_output
) {
168 aig_map
[wirebit
] = (bit
== State::S1
) ? 1 : 0;
169 output_bits
.insert(wirebit
);
174 undriven_bits
.insert(bit
);
175 unused_bits
.insert(bit
);
177 bool scc
= wire
->attributes
.count(ID::abc9_scc
);
178 if (wire
->port_input
|| scc
)
179 input_bits
.insert(bit
);
181 bool keep
= wire
->get_bool_attribute(ID::keep
);
182 if (wire
->port_output
|| keep
|| scc
) {
184 alias_map
[wirebit
] = bit
;
185 output_bits
.insert(wirebit
);
191 for (auto cell
: module
->cells()) {
192 if (!cell
->has_keep_attr()) {
193 if (cell
->type
== ID($_NOT_
))
195 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
196 SigBit Y
= sigmap(cell
->getPort(ID::Y
).as_bit());
197 unused_bits
.erase(A
);
198 undriven_bits
.erase(Y
);
203 if (cell
->type
== ID($_AND_
))
205 SigBit A
= sigmap(cell
->getPort(ID::A
).as_bit());
206 SigBit B
= sigmap(cell
->getPort(ID::B
).as_bit());
207 SigBit Y
= sigmap(cell
->getPort(ID::Y
).as_bit());
208 unused_bits
.erase(A
);
209 unused_bits
.erase(B
);
210 undriven_bits
.erase(Y
);
211 and_map
[Y
] = make_pair(A
, B
);
215 if (dff_mode
&& cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)))
217 SigBit D
= sigmap(cell
->getPort(ID::D
).as_bit());
218 SigBit Q
= sigmap(cell
->getPort(ID::Q
).as_bit());
219 unused_bits
.erase(D
);
220 undriven_bits
.erase(Q
);
222 auto r
YS_ATTRIBUTE(unused
) = ff_bits
.insert(std::make_pair(D
, cell
));
223 log_assert(r
.second
);
227 if (cell
->type
.in(ID($specify2
), ID($specify3
), ID($specrule
)))
231 RTLIL::Module
* inst_module
= module
->design
->module(cell
->type
);
233 IdString derived_type
;
234 if (cell
->parameters
.empty())
235 derived_type
= cell
->type
;
237 derived_type
= inst_module
->derive(module
->design
, cell
->parameters
);
238 inst_module
= module
->design
->module(derived_type
);
239 log_assert(inst_module
);
241 bool abc9_flop
= false;
242 if (!cell
->has_keep_attr()) {
243 auto it
= cell
->attributes
.find(ID::abc9_box_seq
);
244 if (it
!= cell
->attributes
.end()) {
245 int abc9_box_seq
= it
->second
.as_int();
246 if (GetSize(box_list
) <= abc9_box_seq
)
247 box_list
.resize(abc9_box_seq
+1);
248 box_list
[abc9_box_seq
] = cell
;
249 // Only flop boxes may have arrival times
250 // (all others are combinatorial)
251 abc9_flop
= inst_module
->get_bool_attribute(ID::abc9_flop
);
257 if (!timing
.count(derived_type
))
258 timing
.setup_module(inst_module
);
259 auto &t
= timing
.at(derived_type
).arrival
;
260 for (const auto &conn
: cell
->connections()) {
261 auto port_wire
= inst_module
->wire(conn
.first
);
262 if (!port_wire
->port_output
)
265 for (int i
= 0; i
< GetSize(conn
.second
); i
++) {
266 auto d
= t
.at(TimingInfo::NameBit(conn
.first
,i
), 0);
272 static std::set
<std::tuple
<IdString
,IdString
,int>> seen
;
273 if (seen
.emplace(derived_type
, conn
.first
, i
).second
) log("%s.%s[%d] abc9_arrival = %d\n",
274 log_id(cell
->type
), log_id(conn
.first
), i
, d
);
277 arrival_times
[conn
.second
[i
]] = d
;
285 if (cell
->type
== ID($__ABC9_DELAY
))
286 log_error("Cell type '%s' not recognised. Check that '+/abc9_model.v' has been read.\n", cell
->type
.c_str());
289 bool cell_known
= inst_module
|| cell
->known();
290 for (const auto &c
: cell
->connections()) {
291 if (c
.second
.is_fully_const()) continue;
292 auto port_wire
= inst_module
? inst_module
->wire(c
.first
) : nullptr;
293 auto is_input
= (port_wire
&& port_wire
->port_input
) || !cell_known
|| cell
->input(c
.first
);
294 auto is_output
= (port_wire
&& port_wire
->port_output
) || !cell_known
|| cell
->output(c
.first
);
295 if (!is_input
&& !is_output
)
296 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c
.first
), log_id(cell
), log_id(cell
->type
));
299 for (auto b
: c
.second
) {
302 // Do not add as PO if bit is already a PI
303 if (input_bits
.count(b
))
305 if (!w
->port_output
|| !cell_known
) {
306 SigBit I
= sigmap(b
);
309 output_bits
.insert(b
);
314 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
317 dict
<IdString
, std::vector
<IdString
>> box_ports
;
318 for (auto cell
: box_list
) {
321 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
322 log_assert(box_module
);
323 log_assert(box_module
->attributes
.count(ID::abc9_box_id
));
325 auto r
= box_ports
.insert(cell
->type
);
327 // Make carry in the last PI, and carry out the last PO
328 // since ABC requires it this way
329 IdString carry_in
, carry_out
;
330 for (const auto &port_name
: box_module
->ports
) {
331 auto w
= box_module
->wire(port_name
);
333 if (w
->get_bool_attribute(ID::abc9_carry
)) {
335 if (carry_in
!= IdString())
336 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module
));
337 carry_in
= port_name
;
339 if (w
->port_output
) {
340 if (carry_out
!= IdString())
341 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module
));
342 carry_out
= port_name
;
346 r
.first
->second
.push_back(port_name
);
349 if (carry_in
!= IdString() && carry_out
== IdString())
350 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module
));
351 if (carry_in
== IdString() && carry_out
!= IdString())
352 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module
));
353 if (carry_in
!= IdString()) {
354 r
.first
->second
.push_back(carry_in
);
355 r
.first
->second
.push_back(carry_out
);
359 for (auto port_name
: r
.first
->second
) {
360 auto w
= box_module
->wire(port_name
);
362 auto rhs
= cell
->connections_
.at(port_name
, SigSpec());
363 rhs
.append(Const(State::Sx
, GetSize(w
)-GetSize(rhs
)));
366 SigBit I
= sigmap(b
);
371 alias_map
[b
] = State::S0
;
375 co_bits
.emplace_back(b
);
376 unused_bits
.erase(I
);
379 for (const auto &b
: rhs
) {
380 SigBit O
= sigmap(b
);
383 ci_bits
.emplace_back(b
);
384 undriven_bits
.erase(O
);
389 for (auto bit
: input_bits
)
390 undriven_bits
.erase(bit
);
391 for (auto bit
: output_bits
)
392 unused_bits
.erase(sigmap(bit
));
393 for (auto bit
: unused_bits
)
394 undriven_bits
.erase(bit
);
396 // Make all undriven bits a primary input
397 for (auto bit
: undriven_bits
) {
398 input_bits
.insert(bit
);
399 undriven_bits
.erase(bit
);
403 struct sort_by_port_id
{
404 bool operator()(const RTLIL::SigBit
& a
, const RTLIL::SigBit
& b
) const {
405 return a
.wire
->port_id
< b
.wire
->port_id
||
406 (a
.wire
->port_id
== b
.wire
->port_id
&& a
.offset
< b
.offset
);
409 input_bits
.sort(sort_by_port_id());
410 output_bits
.sort(sort_by_port_id());
413 aig_map
[State::S0
] = 0;
414 aig_map
[State::S1
] = 1;
416 for (const auto &bit
: input_bits
) {
418 log_assert(!aig_map
.count(bit
));
419 aig_map
[bit
] = 2*aig_m
;
422 for (const auto &i
: ff_bits
) {
423 const Cell
*cell
= i
.second
;
424 const SigBit
&q
= sigmap(cell
->getPort(ID::Q
));
426 log_assert(!aig_map
.count(q
));
427 aig_map
[q
] = 2*aig_m
;
430 for (auto &bit
: ci_bits
) {
432 // 1'bx may exist here due to a box output
433 // that has been padded to its full width
434 if (bit
== State::Sx
)
436 log_assert(!aig_map
.count(bit
));
437 aig_map
[bit
] = 2*aig_m
;
440 for (auto bit
: co_bits
) {
441 ordered_outputs
[bit
] = aig_o
++;
442 aig_outputs
.push_back(bit2aig(bit
));
445 for (const auto &bit
: output_bits
) {
446 ordered_outputs
[bit
] = aig_o
++;
448 // Unlike bit2aig() which checks aig_map first for
449 // inout/scc bits, since aig_map will point to
450 // the PI, first attempt to find the NOT/AND driver
451 // before resorting to an aig_map lookup (which
452 // could be another PO)
453 if (input_bits
.count(bit
)) {
454 if (not_map
.count(bit
)) {
455 aig
= bit2aig(not_map
.at(bit
)) ^ 1;
456 } else if (and_map
.count(bit
)) {
457 auto args
= and_map
.at(bit
);
458 int a0
= bit2aig(args
.first
);
459 int a1
= bit2aig(args
.second
);
460 aig
= mkgate(a0
, a1
);
463 aig
= aig_map
.at(bit
);
467 aig_outputs
.push_back(aig
);
470 for (auto &i
: ff_bits
) {
471 const SigBit
&d
= i
.first
;
473 aig_outputs
.push_back(aig_map
.at(d
));
477 void write_aiger(std::ostream
&f
, bool ascii_mode
)
480 int aig_obcj
= aig_obc
;
481 int aig_obcjf
= aig_obcj
;
483 log_assert(aig_m
== aig_i
+ aig_l
+ aig_a
);
484 log_assert(aig_obcjf
== GetSize(aig_outputs
));
486 f
<< stringf("%s %d %d %d %d %d", ascii_mode
? "aag" : "aig", aig_m
, aig_i
, aig_l
, aig_o
, aig_a
);
491 for (int i
= 0; i
< aig_i
; i
++)
492 f
<< stringf("%d\n", 2*i
+2);
494 for (int i
= 0; i
< aig_obc
; i
++)
495 f
<< stringf("%d\n", aig_outputs
.at(i
));
497 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
500 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
501 f
<< stringf("%d\n", aig_outputs
.at(i
));
503 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
504 f
<< stringf("%d\n", aig_outputs
.at(i
));
506 for (int i
= 0; i
< aig_a
; i
++)
507 f
<< stringf("%d %d %d\n", 2*(aig_i
+aig_l
+i
)+2, aig_gates
.at(i
).first
, aig_gates
.at(i
).second
);
511 for (int i
= 0; i
< aig_obc
; i
++)
512 f
<< stringf("%d\n", aig_outputs
.at(i
));
514 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
517 for (int i
= aig_obc
; i
< aig_obcj
; i
++)
518 f
<< stringf("%d\n", aig_outputs
.at(i
));
520 for (int i
= aig_obcj
; i
< aig_obcjf
; i
++)
521 f
<< stringf("%d\n", aig_outputs
.at(i
));
523 for (int i
= 0; i
< aig_a
; i
++) {
524 int lhs
= 2*(aig_i
+aig_l
+i
)+2;
525 int rhs0
= aig_gates
.at(i
).first
;
526 int rhs1
= aig_gates
.at(i
).second
;
527 int delta0
= lhs
- rhs0
;
528 int delta1
= rhs0
- rhs1
;
529 aiger_encode(f
, delta0
);
530 aiger_encode(f
, delta1
);
536 auto write_buffer
= [](std::stringstream
&buffer
, int i32
) {
537 int32_t i32_be
= to_big_endian(i32
);
538 buffer
.write(reinterpret_cast<const char*>(&i32_be
), sizeof(i32_be
));
540 std::stringstream h_buffer
;
541 auto write_h_buffer
= std::bind(write_buffer
, std::ref(h_buffer
), std::placeholders::_1
);
543 log_debug("ciNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
) + GetSize(ci_bits
));
544 write_h_buffer(input_bits
.size() + ff_bits
.size() + ci_bits
.size());
545 log_debug("coNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
) + GetSize(co_bits
));
546 write_h_buffer(output_bits
.size() + GetSize(ff_bits
) + GetSize(co_bits
));
547 log_debug("piNum = %d\n", GetSize(input_bits
) + GetSize(ff_bits
));
548 write_h_buffer(input_bits
.size() + ff_bits
.size());
549 log_debug("poNum = %d\n", GetSize(output_bits
) + GetSize(ff_bits
));
550 write_h_buffer(output_bits
.size() + ff_bits
.size());
551 log_debug("boxNum = %d\n", GetSize(box_list
));
552 write_h_buffer(box_list
.size());
554 auto write_buffer_float
= [](std::stringstream
&buffer
, float f32
) {
555 buffer
.write(reinterpret_cast<const char*>(&f32
), sizeof(f32
));
557 std::stringstream i_buffer
;
558 auto write_i_buffer
= std::bind(write_buffer_float
, std::ref(i_buffer
), std::placeholders::_1
);
559 for (auto bit
: input_bits
)
560 write_i_buffer(arrival_times
.at(bit
, 0));
561 //std::stringstream o_buffer;
562 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
563 //for (auto bit : output_bits)
564 // write_o_buffer(0);
566 if (!box_list
.empty() || !ff_bits
.empty()) {
567 dict
<IdString
, std::tuple
<int,int,int>> cell_cache
;
570 for (auto cell
: box_list
) {
573 RTLIL::Module
* box_module
= module
->design
->module(cell
->type
);
574 log_assert(box_module
);
576 IdString derived_type
;
577 if (cell
->parameters
.empty())
578 derived_type
= cell
->type
;
580 derived_type
= box_module
->derive(module
->design
, cell
->parameters
);
581 box_module
= box_module
->design
->module(derived_type
);
582 log_assert(box_module
);
584 auto r
= cell_cache
.insert(derived_type
);
585 auto &v
= r
.first
->second
;
587 int box_inputs
= 0, box_outputs
= 0;
588 for (auto port_name
: box_module
->ports
) {
589 RTLIL::Wire
*w
= box_module
->wire(port_name
);
592 box_inputs
+= GetSize(w
);
594 box_outputs
+= GetSize(w
);
597 std::get
<0>(v
) = box_inputs
;
598 std::get
<1>(v
) = box_outputs
;
599 std::get
<2>(v
) = box_module
->attributes
.at(ID::abc9_box_id
).as_int();
602 write_h_buffer(std::get
<0>(v
));
603 write_h_buffer(std::get
<1>(v
));
604 write_h_buffer(std::get
<2>(v
));
605 write_h_buffer(box_count
++);
608 std::stringstream r_buffer
;
609 auto write_r_buffer
= std::bind(write_buffer
, std::ref(r_buffer
), std::placeholders::_1
);
610 log_debug("flopNum = %d\n", GetSize(ff_bits
));
611 write_r_buffer(ff_bits
.size());
613 std::stringstream s_buffer
;
614 auto write_s_buffer
= std::bind(write_buffer
, std::ref(s_buffer
), std::placeholders::_1
);
615 write_s_buffer(ff_bits
.size());
617 dict
<SigBit
, int> clk_to_mergeability
;
619 for (const auto &i
: ff_bits
) {
620 const SigBit
&d
= i
.first
;
621 const Cell
*cell
= i
.second
;
623 log_assert(cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)));
625 SigBit clock
= sigmap(cell
->getPort(ID::C
));
626 auto r
= clk_to_mergeability
.insert(std::make_pair(clock
, clk_to_mergeability
.size() + 1));
627 int mergeability
= r
.first
->second
;
628 log_assert(mergeability
> 0);
629 if (cell
->type
== ID($_DFF_N_
))
630 write_r_buffer(-mergeability
);
631 else if (cell
->type
== ID($_DFF_P_
))
632 write_r_buffer(mergeability
);
635 Const init
= cell
->attributes
.at(ID::abc9_init
);
636 log_assert(GetSize(init
) == 1);
637 if (init
== State::S1
)
639 else if (init
== State::S0
)
642 log_assert(init
== State::Sx
);
646 // Use arrival time from output of flop box
647 write_i_buffer(arrival_times
.at(d
, 0));
652 std::string buffer_str
= r_buffer
.str();
653 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
654 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
655 f
.write(buffer_str
.data(), buffer_str
.size());
658 buffer_str
= s_buffer
.str();
659 buffer_size_be
= to_big_endian(buffer_str
.size());
660 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
661 f
.write(buffer_str
.data(), buffer_str
.size());
663 RTLIL::Module
*holes_module
= module
->design
->module(stringf("%s$holes", module
->name
.c_str()));
665 std::stringstream a_buffer
;
666 XAigerWriter
writer(holes_module
, false /* dff_mode */, true /* holes_mode */);
667 writer
.write_aiger(a_buffer
, false /*ascii_mode*/);
670 std::string buffer_str
= a_buffer
.str();
671 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
672 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
673 f
.write(buffer_str
.data(), buffer_str
.size());
678 std::string buffer_str
= h_buffer
.str();
679 int32_t buffer_size_be
= to_big_endian(buffer_str
.size());
680 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
681 f
.write(buffer_str
.data(), buffer_str
.size());
684 buffer_str
= i_buffer
.str();
685 buffer_size_be
= to_big_endian(buffer_str
.size());
686 f
.write(reinterpret_cast<const char*>(&buffer_size_be
), sizeof(buffer_size_be
));
687 f
.write(buffer_str
.data(), buffer_str
.size());
689 //buffer_str = o_buffer.str();
690 //buffer_size_be = to_big_endian(buffer_str.size());
691 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
692 //f.write(buffer_str.data(), buffer_str.size());
694 f
<< stringf("Generated by %s\n", yosys_version_str
);
696 module
->design
->scratchpad_set_int("write_xaiger.num_ands", and_map
.size());
697 module
->design
->scratchpad_set_int("write_xaiger.num_wires", aig_map
.size());
698 module
->design
->scratchpad_set_int("write_xaiger.num_inputs", input_bits
.size());
699 module
->design
->scratchpad_set_int("write_xaiger.num_outputs", output_bits
.size());
702 void write_map(std::ostream
&f
)
704 dict
<int, string
> input_lines
;
705 dict
<int, string
> output_lines
;
707 for (auto wire
: module
->wires())
709 SigSpec sig
= sigmap(wire
);
711 for (int i
= 0; i
< GetSize(wire
); i
++)
713 RTLIL::SigBit
b(wire
, i
);
714 if (input_bits
.count(b
)) {
715 int a
= aig_map
.at(b
);
716 log_assert((a
& 1) == 0);
717 input_lines
[a
] += stringf("input %d %d %s\n", (a
>> 1)-1, wire
->start_offset
+i
, log_id(wire
));
720 if (output_bits
.count(b
)) {
721 int o
= ordered_outputs
.at(b
);
722 output_lines
[o
] += stringf("output %d %d %s\n", o
- GetSize(co_bits
), wire
->start_offset
+i
, log_id(wire
));
729 for (auto &it
: input_lines
)
731 log_assert(input_lines
.size() == input_bits
.size());
734 for (auto cell
: box_list
)
735 f
<< stringf("box %d %d %s\n", box_count
++, 0, log_id(cell
->name
));
738 for (auto &it
: output_lines
)
740 log_assert(output_lines
.size() == output_bits
.size());
744 struct XAigerBackend
: public Backend
{
745 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
746 void help() YS_OVERRIDE
748 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
750 log(" write_xaiger [options] [filename]\n");
752 log("Write the top module (according to the (* top *) attribute or if only one module\n");
753 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_DFF_N_,\n");
754 log(" $_DFF_P_, or non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
755 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
756 log("module, if it exists.\n");
759 log(" write ASCII version of AIGER format\n");
761 log(" -map <filename>\n");
762 log(" write an extra file with port and box symbols\n");
765 log(" write $_DFF_[NP]_ cells\n");
768 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
770 bool ascii_mode
= false, dff_mode
= false;
771 std::string map_filename
;
773 log_header(design
, "Executing XAIGER backend.\n");
776 for (argidx
= 1; argidx
< args
.size(); argidx
++)
778 if (args
[argidx
] == "-ascii") {
782 if (map_filename
.empty() && args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
783 map_filename
= args
[++argidx
];
786 if (args
[argidx
] == "-dff") {
792 extra_args(f
, filename
, args
, argidx
, !ascii_mode
);
794 Module
*top_module
= design
->top_module();
796 if (top_module
== nullptr)
797 log_error("Can't find top module in current design!\n");
799 if (!design
->selected_whole_module(top_module
))
800 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module
));
802 if (!top_module
->processes
.empty())
803 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module
));
804 if (!top_module
->memories
.empty())
805 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module
));
807 XAigerWriter
writer(top_module
, dff_mode
);
808 writer
.write_aiger(*f
, ascii_mode
);
810 if (!map_filename
.empty()) {
812 mapf
.open(map_filename
.c_str(), std::ofstream::trunc
);
814 log_error("Can't open file `%s' for writing: %s\n", map_filename
.c_str(), strerror(errno
));
815 writer
.write_map(mapf
);
820 PRIVATE_NAMESPACE_END