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Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50 #include "kernel/timinginfo.h"
51
52 USING_YOSYS_NAMESPACE
53 PRIVATE_NAMESPACE_BEGIN
54
55 inline int32_t to_big_endian(int32_t i32) {
56 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
57 return bswap32(i32);
58 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
59 return i32;
60 #else
61 #error "Unknown endianness"
62 #endif
63 }
64
65 void aiger_encode(std::ostream &f, int x)
66 {
67 log_assert(x >= 0);
68
69 while (x & ~0x7f) {
70 f.put((x & 0x7f) | 0x80);
71 x = x >> 7;
72 }
73
74 f.put(x);
75 }
76
77 struct XAigerWriter
78 {
79 Module *module;
80 SigMap sigmap;
81
82 pool<SigBit> input_bits, output_bits;
83 dict<SigBit, SigBit> not_map, alias_map;
84 dict<SigBit, pair<SigBit, SigBit>> and_map;
85 vector<SigBit> ci_bits, co_bits;
86 dict<SigBit, Cell*> ff_bits;
87 dict<SigBit, float> arrival_times;
88
89 vector<pair<int, int>> aig_gates;
90 vector<int> aig_outputs;
91 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
92
93 dict<SigBit, int> aig_map;
94 dict<SigBit, int> ordered_outputs;
95
96 vector<Cell*> box_list;
97
98 int mkgate(int a0, int a1)
99 {
100 aig_m++, aig_a++;
101 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
102 return 2*aig_m;
103 }
104
105 int bit2aig(SigBit bit)
106 {
107 auto it = aig_map.find(bit);
108 if (it != aig_map.end()) {
109 log_assert(it->second >= 0);
110 return it->second;
111 }
112
113 // NB: Cannot use iterator returned from aig_map.insert()
114 // since this function is called recursively
115
116 int a = -1;
117 if (not_map.count(bit)) {
118 a = bit2aig(not_map.at(bit)) ^ 1;
119 } else
120 if (and_map.count(bit)) {
121 auto args = and_map.at(bit);
122 int a0 = bit2aig(args.first);
123 int a1 = bit2aig(args.second);
124 a = mkgate(a0, a1);
125 } else
126 if (alias_map.count(bit)) {
127 a = bit2aig(alias_map.at(bit));
128 }
129
130 if (bit == State::Sx || bit == State::Sz) {
131 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
132 a = aig_map.at(State::S0);
133 }
134
135 log_assert(a >= 0);
136 aig_map[bit] = a;
137 return a;
138 }
139
140 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
141 {
142 pool<SigBit> undriven_bits;
143 pool<SigBit> unused_bits;
144
145 // promote public wires
146 for (auto wire : module->wires())
147 if (wire->name[0] == '\\')
148 sigmap.add(wire);
149
150 // promote input wires
151 for (auto wire : module->wires())
152 if (wire->port_input)
153 sigmap.add(wire);
154
155 // promote keep wires
156 for (auto wire : module->wires())
157 if (wire->get_bool_attribute(ID::keep))
158 sigmap.add(wire);
159
160 for (auto wire : module->wires())
161 for (int i = 0; i < GetSize(wire); i++)
162 {
163 SigBit wirebit(wire, i);
164 SigBit bit = sigmap(wirebit);
165
166 if (bit.wire == nullptr) {
167 if (wire->port_output) {
168 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
169 output_bits.insert(wirebit);
170 }
171 continue;
172 }
173
174 undriven_bits.insert(bit);
175 unused_bits.insert(bit);
176
177 bool scc = wire->attributes.count(ID::abc9_scc);
178 if (wire->port_input || scc)
179 input_bits.insert(bit);
180
181 bool keep = wire->get_bool_attribute(ID::keep);
182 if (wire->port_output || keep || scc) {
183 if (bit != wirebit)
184 alias_map[wirebit] = bit;
185 output_bits.insert(wirebit);
186 }
187 }
188
189 TimingInfo timing;
190
191 for (auto cell : module->cells()) {
192 if (!cell->has_keep_attr()) {
193 if (cell->type == ID($_NOT_))
194 {
195 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
196 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
197 unused_bits.erase(A);
198 undriven_bits.erase(Y);
199 not_map[Y] = A;
200 continue;
201 }
202
203 if (cell->type == ID($_AND_))
204 {
205 SigBit A = sigmap(cell->getPort(ID::A).as_bit());
206 SigBit B = sigmap(cell->getPort(ID::B).as_bit());
207 SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
208 unused_bits.erase(A);
209 unused_bits.erase(B);
210 undriven_bits.erase(Y);
211 and_map[Y] = make_pair(A, B);
212 continue;
213 }
214
215 if (cell->type == ID($__ABC9_FF_) &&
216 // The presence of an abc9_mergeability attribute indicates
217 // that we do want to pass this flop to ABC
218 cell->attributes.count(ID::abc9_mergeability))
219 {
220 SigBit D = sigmap(cell->getPort(ID::D).as_bit());
221 SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
222 unused_bits.erase(D);
223 undriven_bits.erase(Q);
224 alias_map[Q] = D;
225 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
226 log_assert(r.second);
227 continue;
228 }
229
230 if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
231 continue;
232 }
233
234 RTLIL::Module* inst_module = module->design->module(cell->type);
235 if (inst_module) {
236 IdString derived_type = inst_module->derive(module->design, cell->parameters);
237 inst_module = module->design->module(derived_type);
238 log_assert(inst_module);
239
240 bool abc9_flop = false;
241 if (!cell->has_keep_attr()) {
242 auto it = cell->attributes.find(ID::abc9_box_seq);
243 if (it != cell->attributes.end()) {
244 int abc9_box_seq = it->second.as_int();
245 if (GetSize(box_list) <= abc9_box_seq)
246 box_list.resize(abc9_box_seq+1);
247 box_list[abc9_box_seq] = cell;
248 // Only flop boxes may have arrival times
249 // (all others are combinatorial)
250 abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
251 if (!abc9_flop)
252 continue;
253 }
254 }
255
256 if (!timing.count(derived_type))
257 timing.setup_module(inst_module);
258 auto &t = timing.at(derived_type).arrival;
259 for (const auto &conn : cell->connections()) {
260 auto port_wire = inst_module->wire(conn.first);
261 if (!port_wire->port_output)
262 continue;
263
264 for (int i = 0; i < GetSize(conn.second); i++) {
265 auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
266 if (d == 0)
267 continue;
268
269 #ifndef NDEBUG
270 if (ys_debug(1)) {
271 static std::set<std::tuple<IdString,IdString,int>> seen;
272 if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
273 log_id(cell->type), log_id(conn.first), i, d);
274 }
275 #endif
276 arrival_times[conn.second[i]] = d;
277 }
278 }
279
280 if (abc9_flop)
281 continue;
282 }
283
284 bool cell_known = inst_module || cell->known();
285 for (const auto &c : cell->connections()) {
286 if (c.second.is_fully_const()) continue;
287 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
288 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
289 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
290 if (!is_input && !is_output)
291 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
292
293 if (is_input)
294 for (auto b : c.second) {
295 Wire *w = b.wire;
296 if (!w) continue;
297 // Do not add as PO if bit is already a PI
298 if (input_bits.count(b))
299 continue;
300 if (!w->port_output || !cell_known) {
301 SigBit I = sigmap(b);
302 if (I != b)
303 alias_map[b] = I;
304 output_bits.insert(b);
305 }
306 }
307 }
308
309 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
310 }
311
312 dict<IdString, std::vector<IdString>> box_ports;
313 for (auto cell : box_list) {
314 log_assert(cell);
315
316 RTLIL::Module* box_module = module->design->module(cell->type);
317 log_assert(box_module);
318 log_assert(box_module->attributes.count(ID::abc9_box_id) || box_module->get_bool_attribute(ID::abc9_flop));
319
320 auto r = box_ports.insert(cell->type);
321 if (r.second) {
322 // Make carry in the last PI, and carry out the last PO
323 // since ABC requires it this way
324 IdString carry_in, carry_out;
325 for (const auto &port_name : box_module->ports) {
326 auto w = box_module->wire(port_name);
327 log_assert(w);
328 if (w->get_bool_attribute(ID::abc9_carry)) {
329 if (w->port_input) {
330 if (carry_in != IdString())
331 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
332 carry_in = port_name;
333 }
334 if (w->port_output) {
335 if (carry_out != IdString())
336 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
337 carry_out = port_name;
338 }
339 }
340 else
341 r.first->second.push_back(port_name);
342 }
343
344 if (carry_in != IdString() && carry_out == IdString())
345 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
346 if (carry_in == IdString() && carry_out != IdString())
347 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
348 if (carry_in != IdString()) {
349 r.first->second.push_back(carry_in);
350 r.first->second.push_back(carry_out);
351 }
352 }
353
354 for (auto port_name : r.first->second) {
355 auto w = box_module->wire(port_name);
356 log_assert(w);
357 auto rhs = cell->connections_.at(port_name, SigSpec());
358 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
359 if (w->port_input)
360 for (auto b : rhs) {
361 SigBit I = sigmap(b);
362 if (b == RTLIL::Sx)
363 b = State::S0;
364 else if (I != b) {
365 if (I == RTLIL::Sx)
366 alias_map[b] = State::S0;
367 else
368 alias_map[b] = I;
369 }
370 co_bits.emplace_back(b);
371 unused_bits.erase(I);
372 }
373 if (w->port_output)
374 for (const auto &b : rhs) {
375 SigBit O = sigmap(b);
376 if (O != b)
377 alias_map[O] = b;
378 ci_bits.emplace_back(b);
379 undriven_bits.erase(O);
380 }
381 }
382
383 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
384 if (box_module->get_bool_attribute(ID::abc9_flop)) {
385 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
386 if (rhs.empty())
387 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
388
389 for (auto b : rhs) {
390 SigBit I = sigmap(b);
391 if (b == RTLIL::Sx)
392 b = State::S0;
393 else if (I != b) {
394 if (I == RTLIL::Sx)
395 alias_map[b] = State::S0;
396 else
397 alias_map[b] = I;
398 }
399 co_bits.emplace_back(b);
400 unused_bits.erase(I);
401 }
402 }
403 }
404
405 for (auto bit : input_bits)
406 undriven_bits.erase(bit);
407 for (auto bit : output_bits)
408 unused_bits.erase(sigmap(bit));
409 for (auto bit : unused_bits)
410 undriven_bits.erase(bit);
411
412 // Make all undriven bits a primary input
413 for (auto bit : undriven_bits) {
414 input_bits.insert(bit);
415 undriven_bits.erase(bit);
416 }
417
418 if (holes_mode) {
419 struct sort_by_port_id {
420 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
421 return a.wire->port_id < b.wire->port_id ||
422 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
423 }
424 };
425 input_bits.sort(sort_by_port_id());
426 output_bits.sort(sort_by_port_id());
427 }
428
429 aig_map[State::S0] = 0;
430 aig_map[State::S1] = 1;
431
432 for (const auto &bit : input_bits) {
433 aig_m++, aig_i++;
434 log_assert(!aig_map.count(bit));
435 aig_map[bit] = 2*aig_m;
436 }
437
438 for (const auto &i : ff_bits) {
439 const Cell *cell = i.second;
440 const SigBit &q = sigmap(cell->getPort(ID::Q));
441 aig_m++, aig_i++;
442 log_assert(!aig_map.count(q));
443 aig_map[q] = 2*aig_m;
444 }
445
446 for (auto &bit : ci_bits) {
447 aig_m++, aig_i++;
448 // 1'bx may exist here due to a box output
449 // that has been padded to its full width
450 if (bit == State::Sx)
451 continue;
452 log_assert(!aig_map.count(bit));
453 aig_map[bit] = 2*aig_m;
454 }
455
456 for (auto bit : co_bits) {
457 ordered_outputs[bit] = aig_o++;
458 aig_outputs.push_back(bit2aig(bit));
459 }
460
461 for (const auto &bit : output_bits) {
462 ordered_outputs[bit] = aig_o++;
463 int aig;
464 // Unlike bit2aig() which checks aig_map first for
465 // inout/scc bits, since aig_map will point to
466 // the PI, first attempt to find the NOT/AND driver
467 // before resorting to an aig_map lookup (which
468 // could be another PO)
469 if (input_bits.count(bit)) {
470 if (not_map.count(bit)) {
471 aig = bit2aig(not_map.at(bit)) ^ 1;
472 } else if (and_map.count(bit)) {
473 auto args = and_map.at(bit);
474 int a0 = bit2aig(args.first);
475 int a1 = bit2aig(args.second);
476 aig = mkgate(a0, a1);
477 }
478 else
479 aig = aig_map.at(bit);
480 }
481 else
482 aig = bit2aig(bit);
483 aig_outputs.push_back(aig);
484 }
485
486 for (auto &i : ff_bits) {
487 const SigBit &d = i.first;
488 aig_o++;
489 aig_outputs.push_back(aig_map.at(d));
490 }
491 }
492
493 void write_aiger(std::ostream &f, bool ascii_mode)
494 {
495 int aig_obc = aig_o;
496 int aig_obcj = aig_obc;
497 int aig_obcjf = aig_obcj;
498
499 log_assert(aig_m == aig_i + aig_l + aig_a);
500 log_assert(aig_obcjf == GetSize(aig_outputs));
501
502 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
503 f << stringf("\n");
504
505 if (ascii_mode)
506 {
507 for (int i = 0; i < aig_i; i++)
508 f << stringf("%d\n", 2*i+2);
509
510 for (int i = 0; i < aig_obc; i++)
511 f << stringf("%d\n", aig_outputs.at(i));
512
513 for (int i = aig_obc; i < aig_obcj; i++)
514 f << stringf("1\n");
515
516 for (int i = aig_obc; i < aig_obcj; i++)
517 f << stringf("%d\n", aig_outputs.at(i));
518
519 for (int i = aig_obcj; i < aig_obcjf; i++)
520 f << stringf("%d\n", aig_outputs.at(i));
521
522 for (int i = 0; i < aig_a; i++)
523 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
524 }
525 else
526 {
527 for (int i = 0; i < aig_obc; i++)
528 f << stringf("%d\n", aig_outputs.at(i));
529
530 for (int i = aig_obc; i < aig_obcj; i++)
531 f << stringf("1\n");
532
533 for (int i = aig_obc; i < aig_obcj; i++)
534 f << stringf("%d\n", aig_outputs.at(i));
535
536 for (int i = aig_obcj; i < aig_obcjf; i++)
537 f << stringf("%d\n", aig_outputs.at(i));
538
539 for (int i = 0; i < aig_a; i++) {
540 int lhs = 2*(aig_i+aig_l+i)+2;
541 int rhs0 = aig_gates.at(i).first;
542 int rhs1 = aig_gates.at(i).second;
543 int delta0 = lhs - rhs0;
544 int delta1 = rhs0 - rhs1;
545 aiger_encode(f, delta0);
546 aiger_encode(f, delta1);
547 }
548 }
549
550 f << "c";
551
552 auto write_buffer = [](std::stringstream &buffer, int i32) {
553 int32_t i32_be = to_big_endian(i32);
554 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
555 };
556 std::stringstream h_buffer;
557 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
558 write_h_buffer(1);
559 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
560 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
561 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
562 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
563 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
564 write_h_buffer(input_bits.size() + ff_bits.size());
565 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
566 write_h_buffer(output_bits.size() + ff_bits.size());
567 log_debug("boxNum = %d\n", GetSize(box_list));
568 write_h_buffer(box_list.size());
569
570 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
571 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
572 };
573 std::stringstream i_buffer;
574 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
575 for (auto bit : input_bits)
576 write_i_buffer(arrival_times.at(bit, 0));
577 //std::stringstream o_buffer;
578 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
579 //for (auto bit : output_bits)
580 // write_o_buffer(0);
581
582 if (!box_list.empty() || !ff_bits.empty()) {
583 dict<IdString, std::tuple<int,int,int>> cell_cache;
584
585 int box_count = 0;
586 for (auto cell : box_list) {
587 log_assert(cell);
588
589 RTLIL::Module* box_module = module->design->module(cell->type);
590 log_assert(box_module);
591
592 IdString derived_type = box_module->derive(box_module->design, cell->parameters);
593 box_module = box_module->design->module(derived_type);
594 log_assert(box_module);
595
596 auto r = cell_cache.insert(derived_type);
597 auto &v = r.first->second;
598 if (r.second) {
599 int box_inputs = 0, box_outputs = 0;
600 for (auto port_name : box_module->ports) {
601 RTLIL::Wire *w = box_module->wire(port_name);
602 log_assert(w);
603 if (w->port_input)
604 box_inputs += GetSize(w);
605 if (w->port_output)
606 box_outputs += GetSize(w);
607 }
608
609 // For flops only, create an extra 1-bit input that drives a new wire
610 // called "<cell>.abc9_ff.Q" that is used below
611 if (box_module->get_bool_attribute(ID::abc9_flop))
612 box_inputs++;
613
614 std::get<0>(v) = box_inputs;
615 std::get<1>(v) = box_outputs;
616 std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
617 }
618
619 write_h_buffer(std::get<0>(v));
620 write_h_buffer(std::get<1>(v));
621 write_h_buffer(std::get<2>(v));
622 write_h_buffer(box_count++);
623 }
624
625 std::stringstream r_buffer;
626 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
627 log_debug("flopNum = %d\n", GetSize(ff_bits));
628 write_r_buffer(ff_bits.size());
629
630 std::stringstream s_buffer;
631 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
632 write_s_buffer(ff_bits.size());
633
634 for (const auto &i : ff_bits) {
635 const SigBit &d = i.first;
636 const Cell *cell = i.second;
637
638 int mergeability = cell->attributes.at(ID::abc9_mergeability).as_int();
639 log_assert(mergeability > 0);
640 write_r_buffer(mergeability);
641
642 Const init = cell->attributes.at(ID::abc9_init, State::Sx);
643 log_assert(GetSize(init) == 1);
644 if (init == State::S1)
645 write_s_buffer(1);
646 else if (init == State::S0)
647 write_s_buffer(0);
648 else {
649 log_assert(init == State::Sx);
650 write_s_buffer(0);
651 }
652
653 // Use arrival time from output of flop box
654 write_i_buffer(arrival_times.at(d, 0));
655 //write_o_buffer(0);
656 }
657
658 f << "r";
659 std::string buffer_str = r_buffer.str();
660 int32_t buffer_size_be = to_big_endian(buffer_str.size());
661 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
662 f.write(buffer_str.data(), buffer_str.size());
663
664 f << "s";
665 buffer_str = s_buffer.str();
666 buffer_size_be = to_big_endian(buffer_str.size());
667 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
668 f.write(buffer_str.data(), buffer_str.size());
669
670 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
671 if (holes_module) {
672 std::stringstream a_buffer;
673 XAigerWriter writer(holes_module, true /* holes_mode */);
674 writer.write_aiger(a_buffer, false /*ascii_mode*/);
675
676 f << "a";
677 std::string buffer_str = a_buffer.str();
678 int32_t buffer_size_be = to_big_endian(buffer_str.size());
679 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
680 f.write(buffer_str.data(), buffer_str.size());
681 }
682 }
683
684 f << "h";
685 std::string buffer_str = h_buffer.str();
686 int32_t buffer_size_be = to_big_endian(buffer_str.size());
687 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
688 f.write(buffer_str.data(), buffer_str.size());
689
690 f << "i";
691 buffer_str = i_buffer.str();
692 buffer_size_be = to_big_endian(buffer_str.size());
693 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
694 f.write(buffer_str.data(), buffer_str.size());
695 //f << "o";
696 //buffer_str = o_buffer.str();
697 //buffer_size_be = to_big_endian(buffer_str.size());
698 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
699 //f.write(buffer_str.data(), buffer_str.size());
700
701 f << stringf("Generated by %s\n", yosys_version_str);
702
703 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
704 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
705 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
706 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
707 }
708
709 void write_map(std::ostream &f)
710 {
711 dict<int, string> input_lines;
712 dict<int, string> output_lines;
713
714 for (auto wire : module->wires())
715 {
716 SigSpec sig = sigmap(wire);
717
718 for (int i = 0; i < GetSize(wire); i++)
719 {
720 RTLIL::SigBit b(wire, i);
721 if (input_bits.count(b)) {
722 int a = aig_map.at(b);
723 log_assert((a & 1) == 0);
724 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
725 }
726
727 if (output_bits.count(b)) {
728 int o = ordered_outputs.at(b);
729 int init = 2;
730 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
731 continue;
732 }
733 }
734 }
735
736 input_lines.sort();
737 for (auto &it : input_lines)
738 f << it.second;
739 log_assert(input_lines.size() == input_bits.size());
740
741 int box_count = 0;
742 for (auto cell : box_list)
743 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
744
745 output_lines.sort();
746 for (auto &it : output_lines)
747 f << it.second;
748 log_assert(output_lines.size() == output_bits.size());
749 }
750 };
751
752 struct XAigerBackend : public Backend {
753 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
754 void help() YS_OVERRIDE
755 {
756 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
757 log("\n");
758 log(" write_xaiger [options] [filename]\n");
759 log("\n");
760 log("Write the top module (according to the (* top *) attribute or if only one module\n");
761 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
762 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
763 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
764 log("module, if it exists.\n");
765 log("\n");
766 log(" -ascii\n");
767 log(" write ASCII version of AIGER format\n");
768 log("\n");
769 log(" -map <filename>\n");
770 log(" write an extra file with port and box symbols\n");
771 log("\n");
772 }
773 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
774 {
775 bool ascii_mode = false;
776 std::string map_filename;
777
778 log_header(design, "Executing XAIGER backend.\n");
779
780 size_t argidx;
781 for (argidx = 1; argidx < args.size(); argidx++)
782 {
783 if (args[argidx] == "-ascii") {
784 ascii_mode = true;
785 continue;
786 }
787 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
788 map_filename = args[++argidx];
789 continue;
790 }
791 break;
792 }
793 extra_args(f, filename, args, argidx, !ascii_mode);
794
795 Module *top_module = design->top_module();
796
797 if (top_module == nullptr)
798 log_error("Can't find top module in current design!\n");
799
800 if (!design->selected_whole_module(top_module))
801 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
802
803 if (!top_module->processes.empty())
804 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
805 if (!top_module->memories.empty())
806 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
807
808 XAigerWriter writer(top_module);
809 writer.write_aiger(*f, ascii_mode);
810
811 if (!map_filename.empty()) {
812 std::ofstream mapf;
813 mapf.open(map_filename.c_str(), std::ofstream::trunc);
814 if (mapf.fail())
815 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
816 writer.write_map(mapf);
817 }
818 }
819 } XAigerBackend;
820
821 PRIVATE_NAMESPACE_END