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abc9_ops: ignore (* abc9_flop *) if not '-dff'
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // https://stackoverflow.com/a/46137633
22 #ifdef _MSC_VER
23 #include <stdlib.h>
24 #define bswap32 _byteswap_ulong
25 #elif defined(__APPLE__)
26 #include <libkern/OSByteOrder.h>
27 #define bswap32 OSSwapInt32
28 #elif defined(__GNUC__)
29 #define bswap32 __builtin_bswap32
30 #else
31 #include <cstdint>
32 inline static uint32_t bswap32(uint32_t x)
33 {
34 // https://stackoverflow.com/a/27796212
35 register uint32_t value = number_to_be_reversed;
36 uint8_t lolo = (value >> 0) & 0xFF;
37 uint8_t lohi = (value >> 8) & 0xFF;
38 uint8_t hilo = (value >> 16) & 0xFF;
39 uint8_t hihi = (value >> 24) & 0xFF;
40 return (hihi << 24)
41 | (hilo << 16)
42 | (lohi << 8)
43 | (lolo << 0);
44 }
45 #endif
46
47 #include "kernel/yosys.h"
48 #include "kernel/sigtools.h"
49 #include "kernel/utils.h"
50
51 USING_YOSYS_NAMESPACE
52 PRIVATE_NAMESPACE_BEGIN
53
54 inline int32_t to_big_endian(int32_t i32) {
55 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
56 return bswap32(i32);
57 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
58 return i32;
59 #else
60 #error "Unknown endianness"
61 #endif
62 }
63
64 void aiger_encode(std::ostream &f, int x)
65 {
66 log_assert(x >= 0);
67
68 while (x & ~0x7f) {
69 f.put((x & 0x7f) | 0x80);
70 x = x >> 7;
71 }
72
73 f.put(x);
74 }
75
76 struct XAigerWriter
77 {
78 Module *module;
79 SigMap sigmap;
80
81 pool<SigBit> input_bits, output_bits;
82 dict<SigBit, SigBit> not_map, alias_map;
83 dict<SigBit, pair<SigBit, SigBit>> and_map;
84 vector<SigBit> ci_bits, co_bits;
85 dict<SigBit, Cell*> ff_bits;
86 dict<SigBit, float> arrival_times;
87
88 vector<pair<int, int>> aig_gates;
89 vector<int> aig_outputs;
90 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
91
92 dict<SigBit, int> aig_map;
93 dict<SigBit, int> ordered_outputs;
94
95 vector<Cell*> box_list;
96
97 int mkgate(int a0, int a1)
98 {
99 aig_m++, aig_a++;
100 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
101 return 2*aig_m;
102 }
103
104 int bit2aig(SigBit bit)
105 {
106 auto it = aig_map.find(bit);
107 if (it != aig_map.end()) {
108 log_assert(it->second >= 0);
109 return it->second;
110 }
111
112 // NB: Cannot use iterator returned from aig_map.insert()
113 // since this function is called recursively
114
115 int a = -1;
116 if (not_map.count(bit)) {
117 a = bit2aig(not_map.at(bit)) ^ 1;
118 } else
119 if (and_map.count(bit)) {
120 auto args = and_map.at(bit);
121 int a0 = bit2aig(args.first);
122 int a1 = bit2aig(args.second);
123 a = mkgate(a0, a1);
124 } else
125 if (alias_map.count(bit)) {
126 a = bit2aig(alias_map.at(bit));
127 }
128
129 if (bit == State::Sx || bit == State::Sz) {
130 log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
131 a = aig_map.at(State::S0);
132 }
133
134 log_assert(a >= 0);
135 aig_map[bit] = a;
136 return a;
137 }
138
139 XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
140 {
141 pool<SigBit> undriven_bits;
142 pool<SigBit> unused_bits;
143
144 // promote public wires
145 for (auto wire : module->wires())
146 if (wire->name[0] == '\\')
147 sigmap.add(wire);
148
149 // promote input wires
150 for (auto wire : module->wires())
151 if (wire->port_input)
152 sigmap.add(wire);
153
154 // promote keep wires
155 for (auto wire : module->wires())
156 if (wire->get_bool_attribute(ID::keep))
157 sigmap.add(wire);
158
159 for (auto wire : module->wires())
160 for (int i = 0; i < GetSize(wire); i++)
161 {
162 SigBit wirebit(wire, i);
163 SigBit bit = sigmap(wirebit);
164
165 if (bit.wire == nullptr) {
166 if (wire->port_output) {
167 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
168 output_bits.insert(wirebit);
169 }
170 continue;
171 }
172
173 undriven_bits.insert(bit);
174 unused_bits.insert(bit);
175
176 bool keep = wire->get_bool_attribute(ID::keep);
177 if (wire->port_input || keep)
178 input_bits.insert(bit);
179
180 if (wire->port_output || keep) {
181 if (bit != wirebit)
182 alias_map[wirebit] = bit;
183 output_bits.insert(wirebit);
184 }
185 }
186
187 dict<IdString,dict<IdString,std::vector<int>>> arrivals_cache;
188 for (auto cell : module->cells()) {
189 if (!cell->has_keep_attr()) {
190 if (cell->type == "$_NOT_")
191 {
192 SigBit A = sigmap(cell->getPort("\\A").as_bit());
193 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
194 unused_bits.erase(A);
195 undriven_bits.erase(Y);
196 not_map[Y] = A;
197 continue;
198 }
199
200 if (cell->type == "$_AND_")
201 {
202 SigBit A = sigmap(cell->getPort("\\A").as_bit());
203 SigBit B = sigmap(cell->getPort("\\B").as_bit());
204 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
205 unused_bits.erase(A);
206 unused_bits.erase(B);
207 undriven_bits.erase(Y);
208 and_map[Y] = make_pair(A, B);
209 continue;
210 }
211
212 if (cell->type == "$__ABC9_FF_" &&
213 // The presence of an abc9_mergeability attribute indicates
214 // that we do want to pass this flop to ABC
215 cell->attributes.count("\\abc9_mergeability"))
216 {
217 SigBit D = sigmap(cell->getPort("\\D").as_bit());
218 SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
219 unused_bits.erase(D);
220 undriven_bits.erase(Q);
221 alias_map[Q] = D;
222 auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
223 log_assert(r.second);
224 if (input_bits.erase(Q))
225 log_assert(Q.wire->attributes.count(ID::keep));
226 continue;
227 }
228
229 if (cell->type.in("$specify2", "$specify3", "$specrule"))
230 continue;
231 }
232
233 RTLIL::Module* inst_module = module->design->module(cell->type);
234 if (inst_module) {
235 IdString derived_type = inst_module->derive(module->design, cell->parameters);
236 inst_module = module->design->module(derived_type);
237 log_assert(inst_module);
238
239 bool abc9_flop = false;
240 if (!cell->has_keep_attr()) {
241 auto it = cell->attributes.find("\\abc9_box_seq");
242 if (it != cell->attributes.end()) {
243 int abc9_box_seq = it->second.as_int();
244 if (GetSize(box_list) <= abc9_box_seq)
245 box_list.resize(abc9_box_seq+1);
246 box_list[abc9_box_seq] = cell;
247 // Only flop boxes may have arrival times
248 // (all others are combinatorial)
249 abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
250 if (!abc9_flop)
251 continue;
252 }
253 }
254
255 auto &cell_arrivals = arrivals_cache[derived_type];
256 for (const auto &conn : cell->connections()) {
257 auto port_wire = inst_module->wire(conn.first);
258 if (!port_wire->port_output)
259 continue;
260
261 auto r = cell_arrivals.insert(conn.first);
262 auto &arrivals = r.first->second;
263 if (r.second) {
264 auto it = port_wire->attributes.find("\\abc9_arrival");
265 if (it == port_wire->attributes.end())
266 continue;
267 if (it->second.flags == 0)
268 arrivals.emplace_back(it->second.as_int());
269 else {
270 for (const auto &tok : split_tokens(it->second.decode_string()))
271 arrivals.push_back(atoi(tok.c_str()));
272 if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
273 log_error("%s.%s is %d bits wide but abc9_arrival = '%s' has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
274 GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
275 }
276 }
277
278 if (arrivals.empty())
279 continue;
280
281 auto jt = arrivals.begin();
282 #ifndef NDEBUG
283 if (ys_debug(1)) {
284 static std::set<std::pair<IdString,IdString>> seen;
285 if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt);
286 }
287 #endif
288 for (auto bit : sigmap(conn.second)) {
289 arrival_times[bit] = *jt;
290 if (arrivals.size() > 1)
291 jt++;
292 }
293 }
294
295 if (abc9_flop)
296 continue;
297 }
298
299 bool cell_known = inst_module || cell->known();
300 for (const auto &c : cell->connections()) {
301 if (c.second.is_fully_const()) continue;
302 auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
303 auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
304 auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
305 if (!is_input && !is_output)
306 log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
307
308 if (is_input)
309 for (auto b : c.second) {
310 Wire *w = b.wire;
311 if (!w) continue;
312 // Do not add as PO if bit is already a PI
313 if (input_bits.count(b))
314 continue;
315 if (!w->port_output || !cell_known) {
316 SigBit I = sigmap(b);
317 if (I != b)
318 alias_map[b] = I;
319 output_bits.insert(b);
320 }
321 }
322 }
323
324 //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
325 }
326
327 dict<IdString, std::vector<IdString>> box_ports;
328 for (auto cell : box_list) {
329 log_assert(cell);
330
331 RTLIL::Module* box_module = module->design->module(cell->type);
332 log_assert(box_module);
333 log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
334
335 auto r = box_ports.insert(cell->type);
336 if (r.second) {
337 // Make carry in the last PI, and carry out the last PO
338 // since ABC requires it this way
339 IdString carry_in, carry_out;
340 for (const auto &port_name : box_module->ports) {
341 auto w = box_module->wire(port_name);
342 log_assert(w);
343 if (w->get_bool_attribute("\\abc9_carry")) {
344 if (w->port_input) {
345 if (carry_in != IdString())
346 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
347 carry_in = port_name;
348 }
349 if (w->port_output) {
350 if (carry_out != IdString())
351 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
352 carry_out = port_name;
353 }
354 }
355 else
356 r.first->second.push_back(port_name);
357 }
358
359 if (carry_in != IdString() && carry_out == IdString())
360 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
361 if (carry_in == IdString() && carry_out != IdString())
362 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
363 if (carry_in != IdString()) {
364 r.first->second.push_back(carry_in);
365 r.first->second.push_back(carry_out);
366 }
367 }
368
369 for (auto port_name : r.first->second) {
370 auto w = box_module->wire(port_name);
371 log_assert(w);
372 auto rhs = cell->connections_.at(port_name, SigSpec());
373 rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
374 if (w->port_input)
375 for (auto b : rhs) {
376 SigBit I = sigmap(b);
377 if (b == RTLIL::Sx)
378 b = State::S0;
379 else if (I != b) {
380 if (I == RTLIL::Sx)
381 alias_map[b] = State::S0;
382 else
383 alias_map[b] = I;
384 }
385 co_bits.emplace_back(b);
386 unused_bits.erase(I);
387 }
388 if (w->port_output)
389 for (const auto &b : rhs) {
390 SigBit O = sigmap(b);
391 if (O != b)
392 alias_map[O] = b;
393 ci_bits.emplace_back(b);
394 undriven_bits.erase(O);
395 // If PI and CI, then must be a (* keep *) wire
396 if (input_bits.erase(O)) {
397 log_assert(output_bits.count(O));
398 log_assert(O.wire->get_bool_attribute(ID::keep));
399 }
400 }
401 }
402
403 // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
404 if (box_module->get_bool_attribute("\\abc9_flop")) {
405 SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
406 if (rhs.empty())
407 log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
408
409 for (auto b : rhs) {
410 SigBit I = sigmap(b);
411 if (b == RTLIL::Sx)
412 b = State::S0;
413 else if (I != b) {
414 if (I == RTLIL::Sx)
415 alias_map[b] = State::S0;
416 else
417 alias_map[b] = I;
418 }
419 co_bits.emplace_back(b);
420 unused_bits.erase(I);
421 }
422 }
423 }
424
425 for (auto bit : input_bits)
426 undriven_bits.erase(bit);
427 for (auto bit : output_bits)
428 unused_bits.erase(sigmap(bit));
429 for (auto bit : unused_bits)
430 undriven_bits.erase(bit);
431
432 // Make all undriven bits a primary input
433 for (auto bit : undriven_bits) {
434 input_bits.insert(bit);
435 undriven_bits.erase(bit);
436 }
437
438 if (holes_mode) {
439 struct sort_by_port_id {
440 bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
441 return a.wire->port_id < b.wire->port_id ||
442 (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
443 }
444 };
445 input_bits.sort(sort_by_port_id());
446 output_bits.sort(sort_by_port_id());
447 }
448
449 aig_map[State::S0] = 0;
450 aig_map[State::S1] = 1;
451
452 for (const auto &bit : input_bits) {
453 aig_m++, aig_i++;
454 log_assert(!aig_map.count(bit));
455 aig_map[bit] = 2*aig_m;
456 }
457
458 for (const auto &i : ff_bits) {
459 const Cell *cell = i.second;
460 const SigBit &q = sigmap(cell->getPort("\\Q"));
461 aig_m++, aig_i++;
462 log_assert(!aig_map.count(q));
463 aig_map[q] = 2*aig_m;
464 }
465
466 for (auto &bit : ci_bits) {
467 aig_m++, aig_i++;
468 // 1'bx may exist here due to a box output
469 // that has been padded to its full width
470 if (bit == State::Sx)
471 continue;
472 log_assert(!aig_map.count(bit));
473 aig_map[bit] = 2*aig_m;
474 }
475
476 for (auto bit : co_bits) {
477 ordered_outputs[bit] = aig_o++;
478 aig_outputs.push_back(bit2aig(bit));
479 }
480
481 for (const auto &bit : output_bits) {
482 ordered_outputs[bit] = aig_o++;
483 int aig;
484 // Unlike bit2aig() which checks aig_map first, for
485 // inout/keep bits, since aig_map will point to
486 // the PI, first attempt to find the NOT/AND driver
487 // before resorting to an aig_map lookup (which
488 // could be another PO)
489 if (input_bits.count(bit)) {
490 if (not_map.count(bit)) {
491 aig = bit2aig(not_map.at(bit)) ^ 1;
492 } else if (and_map.count(bit)) {
493 auto args = and_map.at(bit);
494 int a0 = bit2aig(args.first);
495 int a1 = bit2aig(args.second);
496 aig = mkgate(a0, a1);
497 }
498 else
499 aig = aig_map.at(bit);
500 }
501 else
502 aig = bit2aig(bit);
503 aig_outputs.push_back(aig);
504 }
505
506 for (auto &i : ff_bits) {
507 const SigBit &d = i.first;
508 aig_o++;
509 aig_outputs.push_back(aig_map.at(d));
510 }
511 }
512
513 void write_aiger(std::ostream &f, bool ascii_mode)
514 {
515 int aig_obc = aig_o;
516 int aig_obcj = aig_obc;
517 int aig_obcjf = aig_obcj;
518
519 log_assert(aig_m == aig_i + aig_l + aig_a);
520 log_assert(aig_obcjf == GetSize(aig_outputs));
521
522 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
523 f << stringf("\n");
524
525 if (ascii_mode)
526 {
527 for (int i = 0; i < aig_i; i++)
528 f << stringf("%d\n", 2*i+2);
529
530 for (int i = 0; i < aig_obc; i++)
531 f << stringf("%d\n", aig_outputs.at(i));
532
533 for (int i = aig_obc; i < aig_obcj; i++)
534 f << stringf("1\n");
535
536 for (int i = aig_obc; i < aig_obcj; i++)
537 f << stringf("%d\n", aig_outputs.at(i));
538
539 for (int i = aig_obcj; i < aig_obcjf; i++)
540 f << stringf("%d\n", aig_outputs.at(i));
541
542 for (int i = 0; i < aig_a; i++)
543 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
544 }
545 else
546 {
547 for (int i = 0; i < aig_obc; i++)
548 f << stringf("%d\n", aig_outputs.at(i));
549
550 for (int i = aig_obc; i < aig_obcj; i++)
551 f << stringf("1\n");
552
553 for (int i = aig_obc; i < aig_obcj; i++)
554 f << stringf("%d\n", aig_outputs.at(i));
555
556 for (int i = aig_obcj; i < aig_obcjf; i++)
557 f << stringf("%d\n", aig_outputs.at(i));
558
559 for (int i = 0; i < aig_a; i++) {
560 int lhs = 2*(aig_i+aig_l+i)+2;
561 int rhs0 = aig_gates.at(i).first;
562 int rhs1 = aig_gates.at(i).second;
563 int delta0 = lhs - rhs0;
564 int delta1 = rhs0 - rhs1;
565 aiger_encode(f, delta0);
566 aiger_encode(f, delta1);
567 }
568 }
569
570 f << "c";
571
572 auto write_buffer = [](std::stringstream &buffer, int i32) {
573 int32_t i32_be = to_big_endian(i32);
574 buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
575 };
576 std::stringstream h_buffer;
577 auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
578 write_h_buffer(1);
579 log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
580 write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
581 log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
582 write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
583 log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
584 write_h_buffer(input_bits.size() + ff_bits.size());
585 log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
586 write_h_buffer(output_bits.size() + ff_bits.size());
587 log_debug("boxNum = %d\n", GetSize(box_list));
588 write_h_buffer(box_list.size());
589
590 auto write_buffer_float = [](std::stringstream &buffer, float f32) {
591 buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
592 };
593 std::stringstream i_buffer;
594 auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
595 for (auto bit : input_bits)
596 write_i_buffer(arrival_times.at(bit, 0));
597 //std::stringstream o_buffer;
598 //auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
599 //for (auto bit : output_bits)
600 // write_o_buffer(0);
601
602 if (!box_list.empty() || !ff_bits.empty()) {
603 dict<IdString, std::tuple<int,int,int>> cell_cache;
604
605 int box_count = 0;
606 for (auto cell : box_list) {
607 log_assert(cell);
608
609 RTLIL::Module* box_module = module->design->module(cell->type);
610 log_assert(box_module);
611
612 IdString derived_type = box_module->derive(box_module->design, cell->parameters);
613 box_module = box_module->design->module(derived_type);
614 log_assert(box_module);
615
616 auto r = cell_cache.insert(derived_type);
617 auto &v = r.first->second;
618 if (r.second) {
619 int box_inputs = 0, box_outputs = 0;
620 for (auto port_name : box_module->ports) {
621 RTLIL::Wire *w = box_module->wire(port_name);
622 log_assert(w);
623 if (w->port_input)
624 box_inputs += GetSize(w);
625 if (w->port_output)
626 box_outputs += GetSize(w);
627 }
628
629 // For flops only, create an extra 1-bit input that drives a new wire
630 // called "<cell>.abc9_ff.Q" that is used below
631 if (box_module->get_bool_attribute("\\abc9_flop"))
632 box_inputs++;
633
634 std::get<0>(v) = box_inputs;
635 std::get<1>(v) = box_outputs;
636 std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
637 }
638
639 write_h_buffer(std::get<0>(v));
640 write_h_buffer(std::get<1>(v));
641 write_h_buffer(std::get<2>(v));
642 write_h_buffer(box_count++);
643 }
644
645 std::stringstream r_buffer;
646 auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
647 log_debug("flopNum = %d\n", GetSize(ff_bits));
648 write_r_buffer(ff_bits.size());
649
650 std::stringstream s_buffer;
651 auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
652 write_s_buffer(ff_bits.size());
653
654 for (const auto &i : ff_bits) {
655 const SigBit &d = i.first;
656 const Cell *cell = i.second;
657
658 int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
659 log_assert(mergeability > 0);
660 write_r_buffer(mergeability);
661
662 Const init = cell->attributes.at(ID(abc9_init), State::Sx);
663 log_assert(GetSize(init) == 1);
664 if (init == State::S1)
665 write_s_buffer(1);
666 else if (init == State::S0)
667 write_s_buffer(0);
668 else {
669 log_assert(init == State::Sx);
670 write_s_buffer(0);
671 }
672
673 write_i_buffer(arrival_times.at(d, 0));
674 //write_o_buffer(0);
675 }
676
677 f << "r";
678 std::string buffer_str = r_buffer.str();
679 int32_t buffer_size_be = to_big_endian(buffer_str.size());
680 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
681 f.write(buffer_str.data(), buffer_str.size());
682
683 f << "s";
684 buffer_str = s_buffer.str();
685 buffer_size_be = to_big_endian(buffer_str.size());
686 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
687 f.write(buffer_str.data(), buffer_str.size());
688
689 RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
690 if (holes_module) {
691 std::stringstream a_buffer;
692 XAigerWriter writer(holes_module, true /* holes_mode */);
693 writer.write_aiger(a_buffer, false /*ascii_mode*/);
694
695 f << "a";
696 std::string buffer_str = a_buffer.str();
697 int32_t buffer_size_be = to_big_endian(buffer_str.size());
698 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
699 f.write(buffer_str.data(), buffer_str.size());
700 }
701 }
702
703 f << "h";
704 std::string buffer_str = h_buffer.str();
705 int32_t buffer_size_be = to_big_endian(buffer_str.size());
706 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
707 f.write(buffer_str.data(), buffer_str.size());
708
709 f << "i";
710 buffer_str = i_buffer.str();
711 buffer_size_be = to_big_endian(buffer_str.size());
712 f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
713 f.write(buffer_str.data(), buffer_str.size());
714 //f << "o";
715 //buffer_str = o_buffer.str();
716 //buffer_size_be = to_big_endian(buffer_str.size());
717 //f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
718 //f.write(buffer_str.data(), buffer_str.size());
719
720 f << stringf("Generated by %s\n", yosys_version_str);
721
722 module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
723 module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
724 module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
725 module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
726 }
727
728 void write_map(std::ostream &f)
729 {
730 dict<int, string> input_lines;
731 dict<int, string> output_lines;
732
733 for (auto wire : module->wires())
734 {
735 SigSpec sig = sigmap(wire);
736
737 for (int i = 0; i < GetSize(wire); i++)
738 {
739 RTLIL::SigBit b(wire, i);
740 if (input_bits.count(b)) {
741 int a = aig_map.at(b);
742 log_assert((a & 1) == 0);
743 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
744 }
745
746 if (output_bits.count(b)) {
747 int o = ordered_outputs.at(b);
748 int init = 2;
749 output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
750 continue;
751 }
752 }
753 }
754
755 input_lines.sort();
756 for (auto &it : input_lines)
757 f << it.second;
758 log_assert(input_lines.size() == input_bits.size());
759
760 int box_count = 0;
761 for (auto cell : box_list)
762 f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
763
764 output_lines.sort();
765 for (auto &it : output_lines)
766 f << it.second;
767 log_assert(output_lines.size() == output_bits.size());
768 }
769 };
770
771 struct XAigerBackend : public Backend {
772 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
773 void help() YS_OVERRIDE
774 {
775 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
776 log("\n");
777 log(" write_xaiger [options] [filename]\n");
778 log("\n");
779 log("Write the top module (according to the (* top *) attribute or if only one module\n");
780 log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
781 log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
782 log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
783 log("module, if it exists.\n");
784 log("\n");
785 log(" -ascii\n");
786 log(" write ASCII version of AIGER format\n");
787 log("\n");
788 log(" -map <filename>\n");
789 log(" write an extra file with port and box symbols\n");
790 log("\n");
791 }
792 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
793 {
794 bool ascii_mode = false;
795 std::string map_filename;
796
797 log_header(design, "Executing XAIGER backend.\n");
798
799 size_t argidx;
800 for (argidx = 1; argidx < args.size(); argidx++)
801 {
802 if (args[argidx] == "-ascii") {
803 ascii_mode = true;
804 continue;
805 }
806 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
807 map_filename = args[++argidx];
808 continue;
809 }
810 break;
811 }
812 extra_args(f, filename, args, argidx, !ascii_mode);
813
814 Module *top_module = design->top_module();
815
816 if (top_module == nullptr)
817 log_error("Can't find top module in current design!\n");
818
819 if (!design->selected_whole_module(top_module))
820 log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));
821
822 if (!top_module->processes.empty())
823 log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module));
824 if (!top_module->memories.empty())
825 log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
826
827 XAigerWriter writer(top_module);
828 writer.write_aiger(*f, ascii_mode);
829
830 if (!map_filename.empty()) {
831 std::ofstream mapf;
832 mapf.open(map_filename.c_str(), std::ofstream::trunc);
833 if (mapf.fail())
834 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
835 writer.write_map(mapf);
836 }
837 }
838 } XAigerBackend;
839
840 PRIVATE_NAMESPACE_END