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write_xaiger to not write latches, CO/PO fixes
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 void aiger_encode(std::ostream &f, int x)
27 {
28 log_assert(x >= 0);
29
30 while (x & ~0x7f) {
31 f.put((x & 0x7f) | 0x80);
32 x = x >> 7;
33 }
34
35 f.put(x);
36 }
37
38 struct XAigerWriter
39 {
40 Module *module;
41 bool zinit_mode;
42 SigMap sigmap;
43
44 dict<SigBit, bool> init_map;
45 pool<SigBit> input_bits, output_bits;
46 dict<SigBit, SigBit> not_map, ff_map, alias_map;
47 dict<SigBit, pair<SigBit, SigBit>> and_map;
48 pool<SigBit> initstate_bits;
49 pool<SigBit> ci_bits, co_bits;
50 dict<IdString, unsigned> type_map;
51
52 vector<pair<int, int>> aig_gates;
53 vector<int> aig_latchin, aig_latchinit, aig_outputs;
54 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
55
56 dict<SigBit, int> aig_map;
57 dict<SigBit, int> ordered_outputs;
58 dict<SigBit, int> ordered_latches;
59
60 dict<SigBit, int> init_inputs;
61 int initstate_ff = 0;
62
63 int mkgate(int a0, int a1)
64 {
65 aig_m++, aig_a++;
66 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
67 return 2*aig_m;
68 }
69
70 int bit2aig(SigBit bit)
71 {
72 if (aig_map.count(bit) == 0)
73 {
74 aig_map[bit] = -1;
75
76 if (initstate_bits.count(bit)) {
77 log_assert(initstate_ff > 0);
78 aig_map[bit] = initstate_ff;
79 } else
80 if (not_map.count(bit)) {
81 int a = bit2aig(not_map.at(bit)) ^ 1;
82 aig_map[bit] = a;
83 } else
84 if (and_map.count(bit)) {
85 auto args = and_map.at(bit);
86 int a0 = bit2aig(args.first);
87 int a1 = bit2aig(args.second);
88 aig_map[bit] = mkgate(a0, a1);
89 } else
90 if (alias_map.count(bit)) {
91 aig_map[bit] = bit2aig(alias_map.at(bit));
92 }
93
94 if (bit == State::Sx || bit == State::Sz)
95 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
96 }
97
98 log_assert(aig_map.at(bit) >= 0);
99 return aig_map.at(bit);
100 }
101
102 XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
103 {
104 pool<SigBit> undriven_bits;
105 pool<SigBit> unused_bits;
106
107 // promote public wires
108 for (auto wire : module->wires())
109 if (wire->name[0] == '\\')
110 sigmap.add(wire);
111
112 // promote input wires
113 for (auto wire : module->wires())
114 if (wire->port_input)
115 sigmap.add(wire);
116
117 // promote output wires
118 for (auto wire : module->wires())
119 if (wire->port_output)
120 sigmap.add(wire);
121
122 for (auto wire : module->wires())
123 {
124 if (wire->attributes.count("\\init")) {
125 SigSpec initsig = sigmap(wire);
126 Const initval = wire->attributes.at("\\init");
127 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
128 if (initval[i] == State::S0 || initval[i] == State::S1)
129 init_map[initsig[i]] = initval[i] == State::S1;
130 }
131
132 for (int i = 0; i < GetSize(wire); i++)
133 {
134 SigBit wirebit(wire, i);
135 SigBit bit = sigmap(wirebit);
136
137 if (bit.wire == nullptr) {
138 if (wire->port_output) {
139 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
140 output_bits.insert(wirebit);
141 }
142 continue;
143 }
144
145 undriven_bits.insert(bit);
146 unused_bits.insert(bit);
147
148 if (wire->port_input)
149 input_bits.insert(bit);
150
151 if (wire->port_output) {
152 if (bit != wirebit)
153 alias_map[wirebit] = bit;
154 output_bits.insert(wirebit);
155 }
156 }
157 }
158
159 for (auto bit : input_bits)
160 undriven_bits.erase(bit);
161
162 for (auto bit : output_bits)
163 unused_bits.erase(bit);
164
165 for (auto cell : module->cells())
166 {
167 if (cell->type == "$_NOT_")
168 {
169 SigBit A = sigmap(cell->getPort("\\A").as_bit());
170 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
171 unused_bits.erase(A);
172 undriven_bits.erase(Y);
173 not_map[Y] = A;
174 continue;
175 }
176
177 //if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
178 //{
179 // SigBit D = sigmap(cell->getPort("\\D").as_bit());
180 // SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
181 // unused_bits.erase(D);
182 // undriven_bits.erase(Q);
183 // ff_map[Q] = D;
184 // continue;
185 //}
186
187 if (cell->type == "$_AND_")
188 {
189 SigBit A = sigmap(cell->getPort("\\A").as_bit());
190 SigBit B = sigmap(cell->getPort("\\B").as_bit());
191 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
192 unused_bits.erase(A);
193 unused_bits.erase(B);
194 undriven_bits.erase(Y);
195 and_map[Y] = make_pair(A, B);
196 continue;
197 }
198
199 if (cell->type == "$initstate")
200 {
201 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
202 undriven_bits.erase(Y);
203 initstate_bits.insert(Y);
204 continue;
205 }
206
207 for (const auto &c : cell->connections()) {
208 if (c.second.is_fully_const()) continue;
209 for (auto b : c.second.bits()) {
210 Wire *w = b.wire;
211 if (!w) continue;
212 if (cell->input(c.first)) {
213 SigBit I = sigmap(b);
214 if (!w->port_input)
215 co_bits.insert(I);
216 }
217 else if (cell->output(c.first)) {
218 SigBit O = sigmap(b);
219 ci_bits.insert(O);
220 }
221 else log_abort();
222 }
223 if (!type_map.count(cell->type))
224 type_map[cell->type] = type_map.size()+1;
225 }
226 //log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
227 }
228
229 // Do some CI/CO post-processing:
230 // Erase all POs and COs that are undriven
231 for (auto bit : undriven_bits) {
232 co_bits.erase(bit);
233 output_bits.erase(bit);
234 }
235 // Erase all CIs that are also COs or POs
236 for (auto bit : co_bits)
237 ci_bits.erase(bit);
238 for (auto bit : output_bits)
239 ci_bits.erase(bit);
240 // CIs cannot be undriven
241 for (auto bit : ci_bits)
242 undriven_bits.erase(bit);
243 // POs override COs
244 for (auto bit : output_bits)
245 co_bits.erase(bit);
246
247 for (auto bit : unused_bits)
248 undriven_bits.erase(bit);
249
250 if (!undriven_bits.empty()) {
251 undriven_bits.sort();
252 for (auto bit : undriven_bits) {
253 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
254 input_bits.insert(bit);
255 }
256 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
257 }
258
259 init_map.sort();
260 input_bits.sort();
261 output_bits.sort();
262 not_map.sort();
263 ff_map.sort();
264 and_map.sort();
265
266 aig_map[State::S0] = 0;
267 aig_map[State::S1] = 1;
268
269 for (auto bit : ci_bits) {
270 aig_m++, aig_i++;
271 aig_map[bit] = 2*aig_m;
272 }
273
274 for (auto bit : input_bits) {
275 aig_m++, aig_i++;
276 aig_map[bit] = 2*aig_m;
277 }
278
279 if (imode && input_bits.empty()) {
280 aig_m++, aig_i++;
281 }
282
283 if (zinit_mode)
284 {
285 for (auto it : ff_map) {
286 if (init_map.count(it.first))
287 continue;
288 aig_m++, aig_i++;
289 init_inputs[it.first] = 2*aig_m;
290 }
291 }
292
293 for (auto it : ff_map) {
294 aig_m++, aig_l++;
295 aig_map[it.first] = 2*aig_m;
296 ordered_latches[it.first] = aig_l-1;
297 if (init_map.count(it.first) == 0)
298 aig_latchinit.push_back(2);
299 else
300 aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
301 }
302
303 if (!initstate_bits.empty() || !init_inputs.empty()) {
304 aig_m++, aig_l++;
305 initstate_ff = 2*aig_m+1;
306 aig_latchinit.push_back(0);
307 }
308
309 if (zinit_mode)
310 {
311 for (auto it : ff_map)
312 {
313 int l = ordered_latches[it.first];
314
315 if (aig_latchinit.at(l) == 1)
316 aig_map[it.first] ^= 1;
317
318 if (aig_latchinit.at(l) == 2)
319 {
320 int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
321 int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
322 aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
323 }
324 }
325 }
326
327 for (auto it : ff_map) {
328 int a = bit2aig(it.second);
329 int l = ordered_latches[it.first];
330 if (zinit_mode && aig_latchinit.at(l) == 1)
331 aig_latchin.push_back(a ^ 1);
332 else
333 aig_latchin.push_back(a);
334 }
335
336 if (!initstate_bits.empty() || !init_inputs.empty())
337 aig_latchin.push_back(1);
338
339 for (auto bit : co_bits) {
340 aig_o++;
341 ordered_outputs[bit] = aig_o-1;
342 aig_outputs.push_back(bit2aig(bit));
343 }
344
345 for (auto bit : output_bits) {
346 aig_o++;
347 ordered_outputs[bit] = aig_o-1;
348 aig_outputs.push_back(bit2aig(bit));
349 }
350
351 if (omode && output_bits.empty() && co_bits.empty()) {
352 aig_o++;
353 aig_outputs.push_back(0);
354 }
355
356 if (bmode) {
357 //aig_b++;
358 aig_outputs.push_back(0);
359 }
360 }
361
362 void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
363 {
364 int aig_obc = aig_o;
365 int aig_obcj = aig_obc;
366 int aig_obcjf = aig_obcj;
367
368 log_assert(aig_m == aig_i + aig_l + aig_a);
369 log_assert(aig_l == GetSize(aig_latchin));
370 log_assert(aig_l == GetSize(aig_latchinit));
371 log_assert(aig_obcjf == GetSize(aig_outputs));
372
373 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
374 f << stringf("\n");
375
376 if (ascii_mode)
377 {
378 for (int i = 0; i < aig_i; i++)
379 f << stringf("%d\n", 2*i+2);
380
381 for (int i = 0; i < aig_l; i++) {
382 if (zinit_mode || aig_latchinit.at(i) == 0)
383 f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
384 else if (aig_latchinit.at(i) == 1)
385 f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
386 else if (aig_latchinit.at(i) == 2)
387 f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
388 }
389
390 for (int i = 0; i < aig_obc; i++)
391 f << stringf("%d\n", aig_outputs.at(i));
392
393 for (int i = aig_obc; i < aig_obcj; i++)
394 f << stringf("1\n");
395
396 for (int i = aig_obc; i < aig_obcj; i++)
397 f << stringf("%d\n", aig_outputs.at(i));
398
399 for (int i = aig_obcj; i < aig_obcjf; i++)
400 f << stringf("%d\n", aig_outputs.at(i));
401
402 for (int i = 0; i < aig_a; i++)
403 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
404 }
405 else
406 {
407 for (int i = 0; i < aig_l; i++) {
408 if (zinit_mode || aig_latchinit.at(i) == 0)
409 f << stringf("%d\n", aig_latchin.at(i));
410 else if (aig_latchinit.at(i) == 1)
411 f << stringf("%d 1\n", aig_latchin.at(i));
412 else if (aig_latchinit.at(i) == 2)
413 f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
414 }
415
416 for (int i = 0; i < aig_obc; i++)
417 f << stringf("%d\n", aig_outputs.at(i));
418
419 for (int i = aig_obc; i < aig_obcj; i++)
420 f << stringf("1\n");
421
422 for (int i = aig_obc; i < aig_obcj; i++)
423 f << stringf("%d\n", aig_outputs.at(i));
424
425 for (int i = aig_obcj; i < aig_obcjf; i++)
426 f << stringf("%d\n", aig_outputs.at(i));
427
428 for (int i = 0; i < aig_a; i++) {
429 int lhs = 2*(aig_i+aig_l+i)+2;
430 int rhs0 = aig_gates.at(i).first;
431 int rhs1 = aig_gates.at(i).second;
432 int delta0 = lhs - rhs0;
433 int delta1 = rhs0 - rhs1;
434 aiger_encode(f, delta0);
435 aiger_encode(f, delta1);
436 }
437 }
438
439 if (symbols_mode)
440 {
441 dict<string, vector<string>> symbols;
442
443 for (auto wire : module->wires())
444 {
445 //if (wire->name[0] == '$')
446 // continue;
447
448 SigSpec sig = sigmap(wire);
449
450 for (int i = 0; i < GetSize(wire); i++)
451 {
452 if (sig[i].wire == nullptr) {
453 if (wire->port_output)
454 sig[i] = SigBit(wire, i);
455 else
456 continue;
457 }
458
459 if (input_bits.count(sig[i]) || ci_bits.count(SigSpec(sig[i]))) {
460 int a = aig_map.at(sig[i]);
461 log_assert((a & 1) == 0);
462 if (GetSize(wire) != 1)
463 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
464 else
465 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
466 }
467
468 if (output_bits.count(SigSpec(wire, i)) || co_bits.count(SigSpec(wire, i))) {
469 int o = ordered_outputs.at(SigSpec(wire, i));
470 if (GetSize(wire) != 1)
471 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
472 else
473 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
474 }
475
476 if (init_inputs.count(sig[i])) {
477 int a = init_inputs.at(sig[i]);
478 log_assert((a & 1) == 0);
479 if (GetSize(wire) != 1)
480 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
481 else
482 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
483 }
484
485 if (ordered_latches.count(sig[i])) {
486 int l = ordered_latches.at(sig[i]);
487 const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
488 if (GetSize(wire) != 1)
489 symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
490 else
491 symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
492 }
493 }
494 }
495
496 symbols.sort();
497
498 for (auto &sym : symbols) {
499 f << sym.first;
500 std::sort(sym.second.begin(), sym.second.end());
501 for (auto &s : sym.second)
502 f << " " << s;
503 f << std::endl;
504 }
505 }
506
507 f << stringf("c\nGenerated by %s\n", yosys_version_str);
508 }
509
510 void write_map(std::ostream &f, bool verbose_map, bool omode)
511 {
512 dict<int, string> input_lines;
513 dict<int, string> init_lines;
514 dict<int, string> output_lines;
515 dict<int, string> latch_lines;
516 dict<int, string> wire_lines;
517
518 for (auto wire : module->wires())
519 {
520 //if (!verbose_map && wire->name[0] == '$')
521 // continue;
522
523 SigSpec sig = sigmap(wire);
524
525 for (int i = 0; i < GetSize(wire); i++)
526 {
527 RTLIL::SigBit b(wire, i);
528 if (wire->port_input || ci_bits.count(b)) {
529 int a = aig_map.at(sig[i]);
530 log_assert((a & 1) == 0);
531 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
532 continue;
533 }
534
535 if (output_bits.count(b) || co_bits.count(b)) {
536 int o = ordered_outputs.at(b);
537 output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
538 continue;
539 }
540
541 if (init_inputs.count(sig[i])) {
542 int a = init_inputs.at(sig[i]);
543 log_assert((a & 1) == 0);
544 init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
545 continue;
546 }
547
548 if (ordered_latches.count(sig[i])) {
549 int l = ordered_latches.at(sig[i]);
550 if (zinit_mode && (aig_latchinit.at(l) == 1))
551 latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
552 else
553 latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
554 continue;
555 }
556
557 if (verbose_map) {
558 if (aig_map.count(sig[i]) == 0)
559 continue;
560
561 int a = aig_map.at(sig[i]);
562 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
563 }
564 }
565 }
566
567 input_lines.sort();
568 for (auto &it : input_lines)
569 f << it.second;
570
571 init_lines.sort();
572 for (auto &it : init_lines)
573 f << it.second;
574
575 output_lines.sort();
576 for (auto &it : output_lines)
577 f << it.second;
578 log_assert(output_lines.size() == output_bits.size() + co_bits.size());
579 if (omode && output_lines.empty())
580 f << "output 0 0 __dummy_o__\n";
581
582 latch_lines.sort();
583 for (auto &it : latch_lines)
584 f << it.second;
585
586 wire_lines.sort();
587 for (auto &it : wire_lines)
588 f << it.second;
589 }
590 };
591
592 struct XAigerBackend : public Backend {
593 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
594 void help() YS_OVERRIDE
595 {
596 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
597 log("\n");
598 log(" write_xaiger [options] [filename]\n");
599 log("\n");
600 log("Write the current design to an XAIGER file. The design must be flattened and\n");
601 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
602 log("\n");
603 log(" -ascii\n");
604 log(" write ASCII version of AGIER format\n");
605 log("\n");
606 log(" -zinit\n");
607 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
608 log(" uninitialized FFs.\n");
609 log("\n");
610 log(" -symbols\n");
611 log(" include a symbol table in the generated AIGER file\n");
612 log("\n");
613 log(" -map <filename>\n");
614 log(" write an extra file with port and latch symbols\n");
615 log("\n");
616 log(" -vmap <filename>\n");
617 log(" like -map, but more verbose\n");
618 log("\n");
619 log(" -I, -O, -B\n");
620 log(" If the design contains no input/output/assert then create one\n");
621 log(" dummy input/output/bad_state pin to make the tools reading the\n");
622 log(" AIGER file happy.\n");
623 log("\n");
624 }
625 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
626 {
627 bool ascii_mode = false;
628 bool zinit_mode = false;
629 bool miter_mode = false;
630 bool symbols_mode = false;
631 bool verbose_map = false;
632 bool imode = false;
633 bool omode = false;
634 bool bmode = false;
635 std::string map_filename;
636
637 log_header(design, "Executing XAIGER backend.\n");
638
639 size_t argidx;
640 for (argidx = 1; argidx < args.size(); argidx++)
641 {
642 if (args[argidx] == "-ascii") {
643 ascii_mode = true;
644 continue;
645 }
646 if (args[argidx] == "-zinit") {
647 zinit_mode = true;
648 continue;
649 }
650 if (args[argidx] == "-symbols") {
651 symbols_mode = true;
652 continue;
653 }
654 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
655 map_filename = args[++argidx];
656 continue;
657 }
658 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
659 map_filename = args[++argidx];
660 verbose_map = true;
661 continue;
662 }
663 if (args[argidx] == "-I") {
664 imode = true;
665 continue;
666 }
667 if (args[argidx] == "-O") {
668 omode = true;
669 continue;
670 }
671 if (args[argidx] == "-B") {
672 bmode = true;
673 continue;
674 }
675 break;
676 }
677 extra_args(f, filename, args, argidx);
678
679 Module *top_module = design->top_module();
680
681 if (top_module == nullptr)
682 log_error("Can't find top module in current design!\n");
683
684 XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
685 writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
686
687 if (!map_filename.empty()) {
688 std::ofstream mapf;
689 mapf.open(map_filename.c_str(), std::ofstream::trunc);
690 if (mapf.fail())
691 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
692 writer.write_map(mapf, verbose_map, omode);
693 }
694 }
695 } XAigerBackend;
696
697 PRIVATE_NAMESPACE_END