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Merge remote-tracking branch 'origin/master' into xaig
[yosys.git] / backends / aiger / xaiger.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/yosys.h"
22 #include "kernel/sigtools.h"
23
24 USING_YOSYS_NAMESPACE
25 PRIVATE_NAMESPACE_BEGIN
26
27 void aiger_encode(std::ostream &f, int x)
28 {
29 log_assert(x >= 0);
30
31 while (x & ~0x7f) {
32 f.put((x & 0x7f) | 0x80);
33 x = x >> 7;
34 }
35
36 f.put(x);
37 }
38
39 struct XAigerWriter
40 {
41 Module *module;
42 bool zinit_mode;
43 SigMap sigmap;
44
45 dict<SigBit, bool> init_map;
46 pool<SigBit> input_bits, output_bits;
47 dict<SigBit, SigBit> not_map, ff_map, alias_map;
48 dict<SigBit, pair<SigBit, SigBit>> and_map;
49 pool<SigBit> initstate_bits;
50 pool<SigBit> ci_bits, co_bits;
51 dict<IdString, unsigned> type_map;
52
53 vector<pair<int, int>> aig_gates;
54 vector<int> aig_latchin, aig_latchinit, aig_outputs;
55 int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
56
57 dict<SigBit, int> aig_map;
58 dict<SigBit, int> ordered_outputs;
59 dict<SigBit, int> ordered_latches;
60
61 dict<SigBit, int> init_inputs;
62 int initstate_ff = 0;
63
64 int mkgate(int a0, int a1)
65 {
66 aig_m++, aig_a++;
67 aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
68 return 2*aig_m;
69 }
70
71 int bit2aig(SigBit bit)
72 {
73 if (aig_map.count(bit) == 0)
74 {
75 aig_map[bit] = -1;
76
77 if (initstate_bits.count(bit)) {
78 log_assert(initstate_ff > 0);
79 aig_map[bit] = initstate_ff;
80 } else
81 if (not_map.count(bit)) {
82 int a = bit2aig(not_map.at(bit)) ^ 1;
83 aig_map[bit] = a;
84 } else
85 if (and_map.count(bit)) {
86 auto args = and_map.at(bit);
87 int a0 = bit2aig(args.first);
88 int a1 = bit2aig(args.second);
89 aig_map[bit] = mkgate(a0, a1);
90 } else
91 if (alias_map.count(bit)) {
92 aig_map[bit] = bit2aig(alias_map.at(bit));
93 }
94
95 if (bit == State::Sx || bit == State::Sz)
96 log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
97 }
98
99 log_assert(aig_map.at(bit) >= 0);
100 return aig_map.at(bit);
101 }
102
103 XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
104 {
105 pool<SigBit> undriven_bits;
106 pool<SigBit> unused_bits;
107
108 // promote public wires
109 for (auto wire : module->wires())
110 if (wire->name[0] == '\\')
111 sigmap.add(wire);
112
113 // promote input wires
114 for (auto wire : module->wires())
115 if (wire->port_input)
116 sigmap.add(wire);
117
118 // promote output wires
119 for (auto wire : module->wires())
120 if (wire->port_output)
121 sigmap.add(wire);
122
123 for (auto wire : module->wires())
124 {
125 if (wire->attributes.count("\\init")) {
126 SigSpec initsig = sigmap(wire);
127 Const initval = wire->attributes.at("\\init");
128 for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
129 if (initval[i] == State::S0 || initval[i] == State::S1)
130 init_map[initsig[i]] = initval[i] == State::S1;
131 }
132
133 for (int i = 0; i < GetSize(wire); i++)
134 {
135 SigBit wirebit(wire, i);
136 SigBit bit = sigmap(wirebit);
137
138 if (bit.wire == nullptr) {
139 if (wire->port_output) {
140 aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
141 output_bits.insert(wirebit);
142 }
143 continue;
144 }
145
146 undriven_bits.insert(bit);
147 unused_bits.insert(bit);
148
149 if (wire->port_input)
150 input_bits.insert(bit);
151
152 if (wire->port_output) {
153 if (bit != wirebit)
154 alias_map[wirebit] = bit;
155 output_bits.insert(wirebit);
156 }
157 }
158 }
159
160 for (auto bit : input_bits) {
161 if (!bit.wire->port_output)
162 undriven_bits.erase(bit);
163 // Erase POs that are also PIs
164 output_bits.erase(bit);
165 }
166
167 for (auto bit : output_bits)
168 if (!bit.wire->port_input)
169 unused_bits.erase(bit);
170
171 for (auto cell : module->cells())
172 {
173 if (cell->type == "$_NOT_")
174 {
175 SigBit A = sigmap(cell->getPort("\\A").as_bit());
176 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
177 unused_bits.erase(A);
178 undriven_bits.erase(Y);
179 not_map[Y] = A;
180 continue;
181 }
182
183 //if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
184 //{
185 // SigBit D = sigmap(cell->getPort("\\D").as_bit());
186 // SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
187 // unused_bits.erase(D);
188 // undriven_bits.erase(Q);
189 // ff_map[Q] = D;
190 // continue;
191 //}
192
193 if (cell->type == "$_AND_")
194 {
195 SigBit A = sigmap(cell->getPort("\\A").as_bit());
196 SigBit B = sigmap(cell->getPort("\\B").as_bit());
197 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
198 unused_bits.erase(A);
199 unused_bits.erase(B);
200 undriven_bits.erase(Y);
201 and_map[Y] = make_pair(A, B);
202 continue;
203 }
204
205 if (cell->type == "$initstate")
206 {
207 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
208 undriven_bits.erase(Y);
209 initstate_bits.insert(Y);
210 continue;
211 }
212
213 for (const auto &c : cell->connections()) {
214 if (c.second.is_fully_const()) continue;
215 for (auto b : c.second.bits()) {
216 Wire *w = b.wire;
217 if (!w) continue;
218 auto is_input = cell->input(c.first);
219 auto is_output = cell->output(c.first);
220 log_assert(is_input || is_output);
221 if (is_input) {
222 if (!w->port_input) {
223 SigBit I = sigmap(b);
224 if (I != b)
225 alias_map[b] = I;
226 if (!output_bits.count(b))
227 co_bits.insert(b);
228 }
229 }
230 if (is_output) {
231 SigBit O = sigmap(b);
232 if (!input_bits.count(O))
233 ci_bits.insert(O);
234 }
235 }
236 if (!type_map.count(cell->type))
237 type_map[cell->type] = type_map.size()+1;
238 }
239 //log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
240 }
241
242 for (auto bit : input_bits) {
243 RTLIL::Wire *wire = bit.wire;
244 // If encountering an inout port, then create a new wire with $inout.out
245 // suffix, make it a CO driven by the existing inout, and inherit existing
246 // inout's drivers
247 if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) {
248 RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
249 if (!new_wire)
250 new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
251 SigBit new_bit(new_wire, bit.offset);
252 module->connect(new_bit, bit);
253 if (not_map.count(bit))
254 not_map[new_bit] = not_map.at(bit);
255 else if (and_map.count(bit))
256 and_map[new_bit] = and_map.at(bit);
257 else if (alias_map.count(bit))
258 alias_map[new_bit] = alias_map.at(bit);
259 co_bits.insert(new_bit);
260 }
261 }
262
263 // Do some CI/CO post-processing:
264 // Erase all POs and COs that are undriven
265 for (auto bit : undriven_bits) {
266 co_bits.erase(bit);
267 output_bits.erase(bit);
268 }
269 // Erase all CIs that are also COs
270 for (auto bit : co_bits)
271 ci_bits.erase(bit);
272 // CIs cannot be undriven
273 for (auto bit : ci_bits)
274 undriven_bits.erase(bit);
275
276 for (auto bit : unused_bits)
277 undriven_bits.erase(bit);
278
279 if (!undriven_bits.empty()) {
280 undriven_bits.sort();
281 for (auto bit : undriven_bits) {
282 log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
283 input_bits.insert(bit);
284 }
285 log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
286 }
287
288 init_map.sort();
289 input_bits.sort();
290 output_bits.sort();
291 not_map.sort();
292 ff_map.sort();
293 and_map.sort();
294
295 aig_map[State::S0] = 0;
296 aig_map[State::S1] = 1;
297
298 for (auto bit : ci_bits) {
299 aig_m++, aig_i++;
300 aig_map[bit] = 2*aig_m;
301 }
302
303 for (auto bit : input_bits) {
304 aig_m++, aig_i++;
305 aig_map[bit] = 2*aig_m;
306 }
307
308 if (imode && input_bits.empty()) {
309 aig_m++, aig_i++;
310 }
311
312 if (zinit_mode)
313 {
314 for (auto it : ff_map) {
315 if (init_map.count(it.first))
316 continue;
317 aig_m++, aig_i++;
318 init_inputs[it.first] = 2*aig_m;
319 }
320 }
321
322 for (auto it : ff_map) {
323 aig_m++, aig_l++;
324 aig_map[it.first] = 2*aig_m;
325 ordered_latches[it.first] = aig_l-1;
326 if (init_map.count(it.first) == 0)
327 aig_latchinit.push_back(2);
328 else
329 aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
330 }
331
332 if (!initstate_bits.empty() || !init_inputs.empty()) {
333 aig_m++, aig_l++;
334 initstate_ff = 2*aig_m+1;
335 aig_latchinit.push_back(0);
336 }
337
338 if (zinit_mode)
339 {
340 for (auto it : ff_map)
341 {
342 int l = ordered_latches[it.first];
343
344 if (aig_latchinit.at(l) == 1)
345 aig_map[it.first] ^= 1;
346
347 if (aig_latchinit.at(l) == 2)
348 {
349 int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
350 int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
351 aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
352 }
353 }
354 }
355
356 for (auto it : ff_map) {
357 int a = bit2aig(it.second);
358 int l = ordered_latches[it.first];
359 if (zinit_mode && aig_latchinit.at(l) == 1)
360 aig_latchin.push_back(a ^ 1);
361 else
362 aig_latchin.push_back(a);
363 }
364
365 if (!initstate_bits.empty() || !init_inputs.empty())
366 aig_latchin.push_back(1);
367
368 for (auto bit : co_bits) {
369 aig_o++;
370 ordered_outputs[bit] = aig_o-1;
371 aig_outputs.push_back(bit2aig(bit));
372 }
373
374 for (auto bit : output_bits) {
375 aig_o++;
376 ordered_outputs[bit] = aig_o-1;
377 aig_outputs.push_back(bit2aig(bit));
378 }
379
380 if (omode && output_bits.empty() && co_bits.empty()) {
381 aig_o++;
382 aig_outputs.push_back(0);
383 }
384
385 if (bmode) {
386 //aig_b++;
387 aig_outputs.push_back(0);
388 }
389 }
390
391 void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
392 {
393 int aig_obc = aig_o;
394 int aig_obcj = aig_obc;
395 int aig_obcjf = aig_obcj;
396
397 log_assert(aig_m == aig_i + aig_l + aig_a);
398 log_assert(aig_l == GetSize(aig_latchin));
399 log_assert(aig_l == GetSize(aig_latchinit));
400 log_assert(aig_obcjf == GetSize(aig_outputs));
401
402 f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
403 f << stringf("\n");
404
405 if (ascii_mode)
406 {
407 for (int i = 0; i < aig_i; i++)
408 f << stringf("%d\n", 2*i+2);
409
410 for (int i = 0; i < aig_l; i++) {
411 if (zinit_mode || aig_latchinit.at(i) == 0)
412 f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
413 else if (aig_latchinit.at(i) == 1)
414 f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
415 else if (aig_latchinit.at(i) == 2)
416 f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
417 }
418
419 for (int i = 0; i < aig_obc; i++)
420 f << stringf("%d\n", aig_outputs.at(i));
421
422 for (int i = aig_obc; i < aig_obcj; i++)
423 f << stringf("1\n");
424
425 for (int i = aig_obc; i < aig_obcj; i++)
426 f << stringf("%d\n", aig_outputs.at(i));
427
428 for (int i = aig_obcj; i < aig_obcjf; i++)
429 f << stringf("%d\n", aig_outputs.at(i));
430
431 for (int i = 0; i < aig_a; i++)
432 f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
433 }
434 else
435 {
436 for (int i = 0; i < aig_l; i++) {
437 if (zinit_mode || aig_latchinit.at(i) == 0)
438 f << stringf("%d\n", aig_latchin.at(i));
439 else if (aig_latchinit.at(i) == 1)
440 f << stringf("%d 1\n", aig_latchin.at(i));
441 else if (aig_latchinit.at(i) == 2)
442 f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
443 }
444
445 for (int i = 0; i < aig_obc; i++)
446 f << stringf("%d\n", aig_outputs.at(i));
447
448 for (int i = aig_obc; i < aig_obcj; i++)
449 f << stringf("1\n");
450
451 for (int i = aig_obc; i < aig_obcj; i++)
452 f << stringf("%d\n", aig_outputs.at(i));
453
454 for (int i = aig_obcj; i < aig_obcjf; i++)
455 f << stringf("%d\n", aig_outputs.at(i));
456
457 for (int i = 0; i < aig_a; i++) {
458 int lhs = 2*(aig_i+aig_l+i)+2;
459 int rhs0 = aig_gates.at(i).first;
460 int rhs1 = aig_gates.at(i).second;
461 int delta0 = lhs - rhs0;
462 int delta1 = rhs0 - rhs1;
463 aiger_encode(f, delta0);
464 aiger_encode(f, delta1);
465 }
466 }
467
468 if (symbols_mode)
469 {
470 dict<string, vector<string>> symbols;
471
472 bool output_seen = false;
473 for (auto wire : module->wires())
474 {
475 //if (wire->name[0] == '$')
476 // continue;
477
478 SigSpec sig = sigmap(wire);
479
480 for (int i = 0; i < GetSize(wire); i++)
481 {
482 RTLIL::SigBit b(wire, i);
483 if (input_bits.count(b) || ci_bits.count(b)) {
484 int a = aig_map.at(sig[i]);
485 log_assert((a & 1) == 0);
486 if (GetSize(wire) != 1)
487 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
488 else
489 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
490 }
491
492 if (output_bits.count(b) || co_bits.count(b)) {
493 int o = ordered_outputs.at(b);
494 output_seen = !miter_mode;
495 if (GetSize(wire) != 1)
496 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
497 else
498 symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
499 }
500
501 if (init_inputs.count(sig[i])) {
502 int a = init_inputs.at(sig[i]);
503 log_assert((a & 1) == 0);
504 if (GetSize(wire) != 1)
505 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
506 else
507 symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
508 }
509
510 if (ordered_latches.count(sig[i])) {
511 int l = ordered_latches.at(sig[i]);
512 const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
513 if (GetSize(wire) != 1)
514 symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
515 else
516 symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
517 }
518 }
519 }
520
521 if (omode && !output_seen)
522 symbols["o0"].push_back("__dummy_o__");
523
524 symbols.sort();
525
526 for (auto &sym : symbols) {
527 f << sym.first;
528 std::sort(sym.second.begin(), sym.second.end());
529 for (auto &s : sym.second)
530 f << " " << s;
531 f << std::endl;
532 }
533 }
534
535 f << stringf("c\nGenerated by %s\n", yosys_version_str);
536 }
537
538 void write_map(std::ostream &f, bool verbose_map, bool omode)
539 {
540 dict<int, string> input_lines;
541 dict<int, string> init_lines;
542 dict<int, string> output_lines;
543 dict<int, string> latch_lines;
544 dict<int, string> wire_lines;
545
546 for (auto wire : module->wires())
547 {
548 //if (!verbose_map && wire->name[0] == '$')
549 // continue;
550
551 SigSpec sig = sigmap(wire);
552
553 for (int i = 0; i < GetSize(wire); i++)
554 {
555 RTLIL::SigBit b(wire, i);
556 if (input_bits.count(b) || ci_bits.count(b)) {
557 int a = aig_map.at(sig[i]);
558 log_assert((a & 1) == 0);
559 input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
560 continue;
561 }
562
563 if (output_bits.count(b) || co_bits.count(b)) {
564 int o = ordered_outputs.at(b);
565 output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
566 continue;
567 }
568
569 if (init_inputs.count(sig[i])) {
570 int a = init_inputs.at(sig[i]);
571 log_assert((a & 1) == 0);
572 init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
573 continue;
574 }
575
576 if (ordered_latches.count(sig[i])) {
577 int l = ordered_latches.at(sig[i]);
578 if (zinit_mode && (aig_latchinit.at(l) == 1))
579 latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
580 else
581 latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
582 continue;
583 }
584
585 if (verbose_map) {
586 if (aig_map.count(sig[i]) == 0)
587 continue;
588
589 int a = aig_map.at(sig[i]);
590 wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
591 }
592 }
593 }
594
595 input_lines.sort();
596 for (auto &it : input_lines)
597 f << it.second;
598 log_assert(input_lines.size() == input_bits.size() + ci_bits.size());
599
600 init_lines.sort();
601 for (auto &it : init_lines)
602 f << it.second;
603
604 output_lines.sort();
605 for (auto &it : output_lines)
606 f << it.second;
607 log_assert(output_lines.size() == output_bits.size() + co_bits.size());
608 if (omode && output_lines.empty())
609 f << "output 0 0 __dummy_o__\n";
610
611 latch_lines.sort();
612 for (auto &it : latch_lines)
613 f << it.second;
614
615 wire_lines.sort();
616 for (auto &it : wire_lines)
617 f << it.second;
618 }
619 };
620
621 struct XAigerBackend : public Backend {
622 XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
623 void help() YS_OVERRIDE
624 {
625 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
626 log("\n");
627 log(" write_xaiger [options] [filename]\n");
628 log("\n");
629 log("Write the current design to an XAIGER file. The design must be flattened and\n");
630 log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
631 log("\n");
632 log(" -ascii\n");
633 log(" write ASCII version of AGIER format\n");
634 log("\n");
635 log(" -zinit\n");
636 log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
637 log(" uninitialized FFs.\n");
638 log("\n");
639 log(" -symbols\n");
640 log(" include a symbol table in the generated AIGER file\n");
641 log("\n");
642 log(" -map <filename>\n");
643 log(" write an extra file with port and latch symbols\n");
644 log("\n");
645 log(" -vmap <filename>\n");
646 log(" like -map, but more verbose\n");
647 log("\n");
648 log(" -I, -O, -B\n");
649 log(" If the design contains no input/output/assert then create one\n");
650 log(" dummy input/output/bad_state pin to make the tools reading the\n");
651 log(" AIGER file happy.\n");
652 log("\n");
653 }
654 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
655 {
656 bool ascii_mode = false;
657 bool zinit_mode = false;
658 bool miter_mode = false;
659 bool symbols_mode = false;
660 bool verbose_map = false;
661 bool imode = false;
662 bool omode = false;
663 bool bmode = false;
664 std::string map_filename;
665
666 log_header(design, "Executing XAIGER backend.\n");
667
668 size_t argidx;
669 for (argidx = 1; argidx < args.size(); argidx++)
670 {
671 if (args[argidx] == "-ascii") {
672 ascii_mode = true;
673 continue;
674 }
675 if (args[argidx] == "-zinit") {
676 zinit_mode = true;
677 continue;
678 }
679 if (args[argidx] == "-symbols") {
680 symbols_mode = true;
681 continue;
682 }
683 if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
684 map_filename = args[++argidx];
685 continue;
686 }
687 if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
688 map_filename = args[++argidx];
689 verbose_map = true;
690 continue;
691 }
692 if (args[argidx] == "-I") {
693 imode = true;
694 continue;
695 }
696 if (args[argidx] == "-O") {
697 omode = true;
698 continue;
699 }
700 if (args[argidx] == "-B") {
701 bmode = true;
702 continue;
703 }
704 break;
705 }
706 extra_args(f, filename, args, argidx);
707
708 Module *top_module = design->top_module();
709
710 if (top_module == nullptr)
711 log_error("Can't find top module in current design!\n");
712
713 XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
714 writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
715
716 if (!map_filename.empty()) {
717 std::ofstream mapf;
718 mapf.open(map_filename.c_str(), std::ofstream::trunc);
719 if (mapf.fail())
720 log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
721 writer.write_map(mapf, verbose_map, omode);
722 }
723 }
724 } XAigerBackend;
725
726 PRIVATE_NAMESPACE_END