2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 // [[CITE]] Berkeley Logic Interchange Format (BLIF)
21 // University of California. Berkeley. July 28, 1992
22 // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
24 #include "kernel/rtlil.h"
25 #include "kernel/register.h"
26 #include "kernel/sigtools.h"
27 #include "kernel/celltypes.h"
28 #include "kernel/log.h"
32 PRIVATE_NAMESPACE_BEGIN
34 struct BlifDumperConfig
48 std::string buf_type
, buf_in
, buf_out
;
49 std::map
<RTLIL::IdString
, std::pair
<RTLIL::IdString
, RTLIL::IdString
>> unbuf_types
;
50 std::string true_type
, true_out
, false_type
, false_out
, undef_type
, undef_out
;
52 BlifDumperConfig() : icells_mode(false), conn_mode(false), impltf_mode(false), gates_mode(false),
53 cname_mode(false), iname_mode(false), param_mode(false), attr_mode(false), iattr_mode(false),
54 blackbox_mode(false), noalias_mode(false) { }
60 RTLIL::Module
*module
;
61 RTLIL::Design
*design
;
62 BlifDumperConfig
*config
;
66 dict
<SigBit
, int> init_bits
;
68 BlifDumper(std::ostream
&f
, RTLIL::Module
*module
, RTLIL::Design
*design
, BlifDumperConfig
*config
) :
69 f(f
), module(module
), design(design
), config(config
), ct(design
), sigmap(module
)
71 for (Wire
*wire
: module
->wires())
72 if (wire
->attributes
.count(ID::init
)) {
73 SigSpec initsig
= sigmap(wire
);
74 Const initval
= wire
->attributes
.at(ID::init
);
75 for (int i
= 0; i
< GetSize(initsig
) && i
< GetSize(initval
); i
++)
78 init_bits
[initsig
[i
]] = 0;
81 init_bits
[initsig
[i
]] = 1;
89 vector
<shared_str
> cstr_buf
;
90 pool
<SigBit
> cstr_bits_seen
;
92 const char *cstr(RTLIL::IdString id
)
94 std::string str
= RTLIL::unescape_id(id
);
95 for (size_t i
= 0; i
< str
.size(); i
++)
96 if (str
[i
] == '#' || str
[i
] == '=' || str
[i
] == '<' || str
[i
] == '>')
98 cstr_buf
.push_back(str
);
99 return cstr_buf
.back().c_str();
102 const char *cstr(RTLIL::SigBit sig
)
104 cstr_bits_seen
.insert(sig
);
106 if (sig
.wire
== NULL
) {
107 if (sig
== RTLIL::State::S0
) return config
->false_type
== "-" || config
->false_type
== "+" ? config
->false_out
.c_str() : "$false";
108 if (sig
== RTLIL::State::S1
) return config
->true_type
== "-" || config
->true_type
== "+" ? config
->true_out
.c_str() : "$true";
109 return config
->undef_type
== "-" || config
->undef_type
== "+" ? config
->undef_out
.c_str() : "$undef";
112 std::string str
= RTLIL::unescape_id(sig
.wire
->name
);
113 for (size_t i
= 0; i
< str
.size(); i
++)
114 if (str
[i
] == '#' || str
[i
] == '=' || str
[i
] == '<' || str
[i
] == '>')
117 if (sig
.wire
->width
!= 1)
118 str
+= stringf("[%d]", sig
.wire
->upto
? sig
.wire
->start_offset
+sig
.wire
->width
-sig
.offset
-1 : sig
.wire
->start_offset
+sig
.offset
);
120 cstr_buf
.push_back(str
);
121 return cstr_buf
.back().c_str();
124 const char *cstr_init(RTLIL::SigBit sig
)
128 if (init_bits
.count(sig
) == 0)
131 string str
= stringf(" %d", init_bits
.at(sig
));
133 cstr_buf
.push_back(str
);
134 return cstr_buf
.back().c_str();
137 const char *subckt_or_gate(std::string cell_type
)
139 if (!config
->gates_mode
)
141 if (design
->module(RTLIL::escape_id(cell_type
)) == nullptr)
143 if (design
->module(RTLIL::escape_id(cell_type
))->get_blackbox_attribute())
148 void dump_params(const char *command
, dict
<IdString
, Const
> ¶ms
)
150 for (auto ¶m
: params
) {
151 f
<< stringf("%s %s ", command
, log_id(param
.first
));
152 if (param
.second
.flags
& RTLIL::CONST_FLAG_STRING
) {
153 std::string str
= param
.second
.decode_string();
156 if (ch
== '"' || ch
== '\\')
157 f
<< stringf("\\%c", ch
);
158 else if (ch
< 32 || ch
>= 127)
159 f
<< stringf("\\%03o", ch
);
161 f
<< stringf("%c", ch
);
162 f
<< stringf("\"\n");
164 f
<< stringf("%s\n", param
.second
.as_string().c_str());
171 f
<< stringf(".model %s\n", cstr(module
->name
));
173 std::map
<int, RTLIL::Wire
*> inputs
, outputs
;
175 for (auto wire
: module
->wires()) {
176 if (wire
->port_input
)
177 inputs
[wire
->port_id
] = wire
;
178 if (wire
->port_output
)
179 outputs
[wire
->port_id
] = wire
;
182 f
<< stringf(".inputs");
183 for (auto &it
: inputs
) {
184 RTLIL::Wire
*wire
= it
.second
;
185 for (int i
= 0; i
< wire
->width
; i
++)
186 f
<< stringf(" %s", cstr(RTLIL::SigSpec(wire
, i
)));
190 f
<< stringf(".outputs");
191 for (auto &it
: outputs
) {
192 RTLIL::Wire
*wire
= it
.second
;
193 for (int i
= 0; i
< wire
->width
; i
++)
194 f
<< stringf(" %s", cstr(RTLIL::SigSpec(wire
, i
)));
198 if (module
->get_blackbox_attribute()) {
199 f
<< stringf(".blackbox\n");
200 f
<< stringf(".end\n");
204 if (!config
->impltf_mode
) {
205 if (!config
->false_type
.empty()) {
206 if (config
->false_type
== "+")
207 f
<< stringf(".names %s\n", config
->false_out
.c_str());
208 else if (config
->false_type
!= "-")
209 f
<< stringf(".%s %s %s=$false\n", subckt_or_gate(config
->false_type
),
210 config
->false_type
.c_str(), config
->false_out
.c_str());
212 f
<< stringf(".names $false\n");
213 if (!config
->true_type
.empty()) {
214 if (config
->true_type
== "+")
215 f
<< stringf(".names %s\n1\n", config
->true_out
.c_str());
216 else if (config
->true_type
!= "-")
217 f
<< stringf(".%s %s %s=$true\n", subckt_or_gate(config
->true_type
),
218 config
->true_type
.c_str(), config
->true_out
.c_str());
220 f
<< stringf(".names $true\n1\n");
221 if (!config
->undef_type
.empty()) {
222 if (config
->undef_type
== "+")
223 f
<< stringf(".names %s\n", config
->undef_out
.c_str());
224 else if (config
->undef_type
!= "-")
225 f
<< stringf(".%s %s %s=$undef\n", subckt_or_gate(config
->undef_type
),
226 config
->undef_type
.c_str(), config
->undef_out
.c_str());
228 f
<< stringf(".names $undef\n");
231 for (auto cell
: module
->cells())
233 if (config
->unbuf_types
.count(cell
->type
)) {
234 auto portnames
= config
->unbuf_types
.at(cell
->type
);
235 f
<< stringf(".names %s %s\n1 1\n",
236 cstr(cell
->getPort(portnames
.first
)), cstr(cell
->getPort(portnames
.second
)));
240 if (!config
->icells_mode
&& cell
->type
== ID($_NOT_
)) {
241 f
<< stringf(".names %s %s\n0 1\n",
242 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::Y
)));
246 if (!config
->icells_mode
&& cell
->type
== ID($_AND_
)) {
247 f
<< stringf(".names %s %s %s\n11 1\n",
248 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::Y
)));
252 if (!config
->icells_mode
&& cell
->type
== ID($_OR_
)) {
253 f
<< stringf(".names %s %s %s\n1- 1\n-1 1\n",
254 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::Y
)));
258 if (!config
->icells_mode
&& cell
->type
== ID($_XOR_
)) {
259 f
<< stringf(".names %s %s %s\n10 1\n01 1\n",
260 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::Y
)));
264 if (!config
->icells_mode
&& cell
->type
== ID($_NAND_
)) {
265 f
<< stringf(".names %s %s %s\n0- 1\n-0 1\n",
266 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::Y
)));
270 if (!config
->icells_mode
&& cell
->type
== ID($_NOR_
)) {
271 f
<< stringf(".names %s %s %s\n00 1\n",
272 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::Y
)));
276 if (!config
->icells_mode
&& cell
->type
== ID($_XNOR_
)) {
277 f
<< stringf(".names %s %s %s\n11 1\n00 1\n",
278 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::Y
)));
282 if (!config
->icells_mode
&& cell
->type
== ID($_ANDNOT_
)) {
283 f
<< stringf(".names %s %s %s\n10 1\n",
284 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::Y
)));
288 if (!config
->icells_mode
&& cell
->type
== ID($_ORNOT_
)) {
289 f
<< stringf(".names %s %s %s\n1- 1\n-0 1\n",
290 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::Y
)));
294 if (!config
->icells_mode
&& cell
->type
== ID($_AOI3_
)) {
295 f
<< stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
296 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::C
)), cstr(cell
->getPort(ID::Y
)));
300 if (!config
->icells_mode
&& cell
->type
== ID($_OAI3_
)) {
301 f
<< stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
302 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)), cstr(cell
->getPort(ID::C
)), cstr(cell
->getPort(ID::Y
)));
306 if (!config
->icells_mode
&& cell
->type
== ID($_AOI4_
)) {
307 f
<< stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
308 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)),
309 cstr(cell
->getPort(ID::C
)), cstr(cell
->getPort(ID::D
)), cstr(cell
->getPort(ID::Y
)));
313 if (!config
->icells_mode
&& cell
->type
== ID($_OAI4_
)) {
314 f
<< stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
315 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)),
316 cstr(cell
->getPort(ID::C
)), cstr(cell
->getPort(ID::D
)), cstr(cell
->getPort(ID::Y
)));
320 if (!config
->icells_mode
&& cell
->type
== ID($_MUX_
)) {
321 f
<< stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
322 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)),
323 cstr(cell
->getPort(ID::S
)), cstr(cell
->getPort(ID::Y
)));
327 if (!config
->icells_mode
&& cell
->type
== ID($_NMUX_
)) {
328 f
<< stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
329 cstr(cell
->getPort(ID::A
)), cstr(cell
->getPort(ID::B
)),
330 cstr(cell
->getPort(ID::S
)), cstr(cell
->getPort(ID::Y
)));
334 if (!config
->icells_mode
&& cell
->type
== ID($_FF_
)) {
335 f
<< stringf(".latch %s %s%s\n", cstr(cell
->getPort(ID::D
)), cstr(cell
->getPort(ID::Q
)),
336 cstr_init(cell
->getPort(ID::Q
)));
340 if (!config
->icells_mode
&& cell
->type
== ID($_DFF_N_
)) {
341 f
<< stringf(".latch %s %s fe %s%s\n", cstr(cell
->getPort(ID::D
)), cstr(cell
->getPort(ID::Q
)),
342 cstr(cell
->getPort(ID::C
)), cstr_init(cell
->getPort(ID::Q
)));
346 if (!config
->icells_mode
&& cell
->type
== ID($_DFF_P_
)) {
347 f
<< stringf(".latch %s %s re %s%s\n", cstr(cell
->getPort(ID::D
)), cstr(cell
->getPort(ID::Q
)),
348 cstr(cell
->getPort(ID::C
)), cstr_init(cell
->getPort(ID::Q
)));
352 if (!config
->icells_mode
&& cell
->type
== ID($_DLATCH_N_
)) {
353 f
<< stringf(".latch %s %s al %s%s\n", cstr(cell
->getPort(ID::D
)), cstr(cell
->getPort(ID::Q
)),
354 cstr(cell
->getPort(ID::E
)), cstr_init(cell
->getPort(ID::Q
)));
358 if (!config
->icells_mode
&& cell
->type
== ID($_DLATCH_P_
)) {
359 f
<< stringf(".latch %s %s ah %s%s\n", cstr(cell
->getPort(ID::D
)), cstr(cell
->getPort(ID::Q
)),
360 cstr(cell
->getPort(ID::E
)), cstr_init(cell
->getPort(ID::Q
)));
364 if (!config
->icells_mode
&& cell
->type
== ID($lut
)) {
365 f
<< stringf(".names");
366 auto &inputs
= cell
->getPort(ID::A
);
367 auto width
= cell
->parameters
.at(ID::WIDTH
).as_int();
368 log_assert(inputs
.size() == width
);
369 for (int i
= width
-1; i
>= 0; i
--)
370 f
<< stringf(" %s", cstr(inputs
.extract(i
, 1)));
371 auto &output
= cell
->getPort(ID::Y
);
372 log_assert(output
.size() == 1);
373 f
<< stringf(" %s", cstr(output
));
375 RTLIL::SigSpec mask
= cell
->parameters
.at(ID::LUT
);
376 for (int i
= 0; i
< (1 << width
); i
++)
377 if (mask
[i
] == State::S1
) {
378 for (int j
= width
-1; j
>= 0; j
--) {
379 f
<< ((i
>>j
)&1 ? '1' : '0');
386 if (!config
->icells_mode
&& cell
->type
== ID($sop
)) {
387 f
<< stringf(".names");
388 auto &inputs
= cell
->getPort(ID::A
);
389 auto width
= cell
->parameters
.at(ID::WIDTH
).as_int();
390 auto depth
= cell
->parameters
.at(ID::DEPTH
).as_int();
391 vector
<State
> table
= cell
->parameters
.at(ID::TABLE
).bits
;
392 while (GetSize(table
) < 2*width
*depth
)
393 table
.push_back(State::S0
);
394 log_assert(inputs
.size() == width
);
395 for (int i
= 0; i
< width
; i
++)
396 f
<< stringf(" %s", cstr(inputs
.extract(i
, 1)));
397 auto &output
= cell
->getPort(ID::Y
);
398 log_assert(output
.size() == 1);
399 f
<< stringf(" %s", cstr(output
));
401 for (int i
= 0; i
< depth
; i
++) {
402 for (int j
= 0; j
< width
; j
++) {
403 bool pat0
= table
.at(2*width
*i
+ 2*j
+ 0) == State::S1
;
404 bool pat1
= table
.at(2*width
*i
+ 2*j
+ 1) == State::S1
;
405 if (pat0
&& !pat1
) f
<< "0";
406 else if (!pat0
&& pat1
) f
<< "1";
414 f
<< stringf(".%s %s", subckt_or_gate(cell
->type
.str()), cstr(cell
->type
));
415 for (auto &conn
: cell
->connections())
417 if (conn
.second
.size() == 1) {
418 f
<< stringf(" %s=%s", cstr(conn
.first
), cstr(conn
.second
[0]));
422 Module
*m
= design
->module(cell
->type
);
423 Wire
*w
= m
? m
->wire(conn
.first
) : nullptr;
426 for (int i
= 0; i
< GetSize(conn
.second
); i
++)
427 f
<< stringf(" %s[%d]=%s", cstr(conn
.first
), i
, cstr(conn
.second
[i
]));
429 for (int i
= 0; i
< std::min(GetSize(conn
.second
), GetSize(w
)); i
++) {
431 f
<< stringf(" %s[%d]=%s", cstr(conn
.first
), sig
.wire
->upto
?
432 sig
.wire
->start_offset
+sig
.wire
->width
-sig
.offset
-1 :
433 sig
.wire
->start_offset
+sig
.offset
, cstr(conn
.second
[i
]));
439 if (config
->cname_mode
)
440 f
<< stringf(".cname %s\n", cstr(cell
->name
));
441 if (config
->attr_mode
)
442 dump_params(".attr", cell
->attributes
);
443 if (config
->param_mode
)
444 dump_params(".param", cell
->parameters
);
448 if (config
->iname_mode
)
449 f
<< stringf(".cname %s\n", cstr(cell
->name
));
450 if (config
->iattr_mode
)
451 dump_params(".attr", cell
->attributes
);
455 for (auto &conn
: module
->connections())
456 for (int i
= 0; i
< conn
.first
.size(); i
++)
458 SigBit lhs_bit
= conn
.first
[i
];
459 SigBit rhs_bit
= conn
.second
[i
];
461 if (config
->noalias_mode
&& cstr_bits_seen
.count(lhs_bit
) == 0)
464 if (config
->conn_mode
)
465 f
<< stringf(".conn %s %s\n", cstr(rhs_bit
), cstr(lhs_bit
));
466 else if (!config
->buf_type
.empty())
467 f
<< stringf(".%s %s %s=%s %s=%s\n", subckt_or_gate(config
->buf_type
), config
->buf_type
.c_str(),
468 config
->buf_in
.c_str(), cstr(rhs_bit
), config
->buf_out
.c_str(), cstr(lhs_bit
));
470 f
<< stringf(".names %s %s\n1 1\n", cstr(rhs_bit
), cstr(lhs_bit
));
473 f
<< stringf(".end\n");
476 static void dump(std::ostream
&f
, RTLIL::Module
*module
, RTLIL::Design
*design
, BlifDumperConfig
&config
)
478 BlifDumper
dumper(f
, module
, design
, &config
);
483 struct BlifBackend
: public Backend
{
484 BlifBackend() : Backend("blif", "write design to BLIF file") { }
487 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
489 log(" write_blif [options] [filename]\n");
491 log("Write the current design to an BLIF file.\n");
493 log(" -top top_module\n");
494 log(" set the specified module as design top module\n");
496 log(" -buf <cell-type> <in-port> <out-port>\n");
497 log(" use cells of type <cell-type> with the specified port names for buffers\n");
499 log(" -unbuf <cell-type> <in-port> <out-port>\n");
500 log(" replace buffer cells with the specified name and port names with\n");
501 log(" a .names statement that models a buffer\n");
503 log(" -true <cell-type> <out-port>\n");
504 log(" -false <cell-type> <out-port>\n");
505 log(" -undef <cell-type> <out-port>\n");
506 log(" use the specified cell types to drive nets that are constant 1, 0, or\n");
507 log(" undefined. when '-' is used as <cell-type>, then <out-port> specifies\n");
508 log(" the wire name to be used for the constant signal and no cell driving\n");
509 log(" that wire is generated. when '+' is used as <cell-type>, then <out-port>\n");
510 log(" specifies the wire name to be used for the constant signal and a .names\n");
511 log(" statement is generated to drive the wire.\n");
514 log(" if a net name is aliasing another net name, then by default a net\n");
515 log(" without fanout is created that is driven by the other net. This option\n");
516 log(" suppresses the generation of this nets without fanout.\n");
518 log("The following options can be useful when the generated file is not going to be\n");
519 log("read by a BLIF parser but a custom tool. It is recommended to not name the output\n");
520 log("file *.blif when any of this options is used.\n");
523 log(" do not translate Yosys's internal gates to generic BLIF logic\n");
524 log(" functions. Instead create .subckt or .gate lines for all cells.\n");
527 log(" print .gate instead of .subckt lines for all cells that are not\n");
528 log(" instantiations of other modules from this design.\n");
531 log(" do not generate buffers for connected wires. instead use the\n");
532 log(" non-standard .conn statement.\n");
535 log(" use the non-standard .attr statement to write cell attributes\n");
538 log(" use the non-standard .param statement to write cell parameters\n");
541 log(" use the non-standard .cname statement to write cell names\n");
543 log(" -iname, -iattr\n");
544 log(" enable -cname and -attr functionality for .names statements\n");
545 log(" (the .cname and .attr statements will be included in the BLIF\n");
546 log(" output after the truth table for the .names statement)\n");
549 log(" write blackbox cells with .blackbox statement.\n");
552 log(" do not write definitions for the $true, $false and $undef wires.\n");
555 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) override
557 std::string top_module_name
;
558 std::string buf_type
, buf_in
, buf_out
;
559 std::string true_type
, true_out
;
560 std::string false_type
, false_out
;
561 BlifDumperConfig config
;
563 log_header(design
, "Executing BLIF backend.\n");
566 for (argidx
= 1; argidx
< args
.size(); argidx
++)
568 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
569 top_module_name
= args
[++argidx
];
572 if (args
[argidx
] == "-buf" && argidx
+3 < args
.size()) {
573 config
.buf_type
= args
[++argidx
];
574 config
.buf_in
= args
[++argidx
];
575 config
.buf_out
= args
[++argidx
];
578 if (args
[argidx
] == "-unbuf" && argidx
+3 < args
.size()) {
579 RTLIL::IdString unbuf_type
= RTLIL::escape_id(args
[++argidx
]);
580 RTLIL::IdString unbuf_in
= RTLIL::escape_id(args
[++argidx
]);
581 RTLIL::IdString unbuf_out
= RTLIL::escape_id(args
[++argidx
]);
582 config
.unbuf_types
[unbuf_type
] = std::pair
<RTLIL::IdString
, RTLIL::IdString
>(unbuf_in
, unbuf_out
);
585 if (args
[argidx
] == "-true" && argidx
+2 < args
.size()) {
586 config
.true_type
= args
[++argidx
];
587 config
.true_out
= args
[++argidx
];
590 if (args
[argidx
] == "-false" && argidx
+2 < args
.size()) {
591 config
.false_type
= args
[++argidx
];
592 config
.false_out
= args
[++argidx
];
595 if (args
[argidx
] == "-undef" && argidx
+2 < args
.size()) {
596 config
.undef_type
= args
[++argidx
];
597 config
.undef_out
= args
[++argidx
];
600 if (args
[argidx
] == "-icells") {
601 config
.icells_mode
= true;
604 if (args
[argidx
] == "-gates") {
605 config
.gates_mode
= true;
608 if (args
[argidx
] == "-conn") {
609 config
.conn_mode
= true;
612 if (args
[argidx
] == "-cname") {
613 config
.cname_mode
= true;
616 if (args
[argidx
] == "-param") {
617 config
.param_mode
= true;
620 if (args
[argidx
] == "-attr") {
621 config
.attr_mode
= true;
624 if (args
[argidx
] == "-iname") {
625 config
.iname_mode
= true;
628 if (args
[argidx
] == "-iattr") {
629 config
.iattr_mode
= true;
632 if (args
[argidx
] == "-blackbox") {
633 config
.blackbox_mode
= true;
636 if (args
[argidx
] == "-impltf") {
637 config
.impltf_mode
= true;
640 if (args
[argidx
] == "-noalias") {
641 config
.noalias_mode
= true;
646 extra_args(f
, filename
, args
, argidx
);
648 if (top_module_name
.empty())
649 for (auto module
: design
->modules())
650 if (module
->get_bool_attribute(ID::top
))
651 top_module_name
= module
->name
.str();
653 *f
<< stringf("# Generated by %s\n", yosys_version_str
);
655 std::vector
<RTLIL::Module
*> mod_list
;
658 for (auto module
: design
->modules())
660 if (module
->get_blackbox_attribute() && !config
.blackbox_mode
)
663 if (module
->processes
.size() != 0)
664 log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", log_id(module
->name
));
665 if (module
->memories
.size() != 0)
666 log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", log_id(module
->name
));
668 if (module
->name
== RTLIL::escape_id(top_module_name
)) {
669 BlifDumper::dump(*f
, module
, design
, config
);
670 top_module_name
.clear();
674 mod_list
.push_back(module
);
677 if (!top_module_name
.empty())
678 log_error("Can't find top module `%s'!\n", top_module_name
.c_str());
680 for (auto module
: mod_list
)
681 BlifDumper::dump(*f
, module
, design
, config
);
685 PRIVATE_NAMESPACE_END