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[yosys.git] / backends / blif / blif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] Berkeley Logic Interchange Format (BLIF)
21 // University of California. Berkeley. July 28, 1992
22 // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
23
24 #include "kernel/rtlil.h"
25 #include "kernel/register.h"
26 #include "kernel/sigtools.h"
27 #include "kernel/celltypes.h"
28 #include "kernel/log.h"
29 #include <string>
30
31 USING_YOSYS_NAMESPACE
32 PRIVATE_NAMESPACE_BEGIN
33
34 struct BlifDumperConfig
35 {
36 bool icells_mode;
37 bool conn_mode;
38 bool impltf_mode;
39 bool gates_mode;
40 bool cname_mode;
41 bool iname_mode;
42 bool param_mode;
43 bool attr_mode;
44 bool iattr_mode;
45 bool blackbox_mode;
46 bool noalias_mode;
47
48 std::string buf_type, buf_in, buf_out;
49 std::map<RTLIL::IdString, std::pair<RTLIL::IdString, RTLIL::IdString>> unbuf_types;
50 std::string true_type, true_out, false_type, false_out, undef_type, undef_out;
51
52 BlifDumperConfig() : icells_mode(false), conn_mode(false), impltf_mode(false), gates_mode(false),
53 cname_mode(false), iname_mode(false), param_mode(false), attr_mode(false), iattr_mode(false),
54 blackbox_mode(false), noalias_mode(false) { }
55 };
56
57 struct BlifDumper
58 {
59 std::ostream &f;
60 RTLIL::Module *module;
61 RTLIL::Design *design;
62 BlifDumperConfig *config;
63 CellTypes ct;
64
65 SigMap sigmap;
66 dict<SigBit, int> init_bits;
67
68 BlifDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BlifDumperConfig *config) :
69 f(f), module(module), design(design), config(config), ct(design), sigmap(module)
70 {
71 for (Wire *wire : module->wires())
72 if (wire->attributes.count("\\init")) {
73 SigSpec initsig = sigmap(wire);
74 Const initval = wire->attributes.at("\\init");
75 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
76 switch (initval[i]) {
77 case State::S0:
78 init_bits[initsig[i]] = 0;
79 break;
80 case State::S1:
81 init_bits[initsig[i]] = 1;
82 break;
83 default:
84 break;
85 }
86 }
87 }
88
89 vector<shared_str> cstr_buf;
90 pool<SigBit> cstr_bits_seen;
91
92 const char *cstr(RTLIL::IdString id)
93 {
94 std::string str = RTLIL::unescape_id(id);
95 for (size_t i = 0; i < str.size(); i++)
96 if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
97 str[i] = '?';
98 cstr_buf.push_back(str);
99 return cstr_buf.back().c_str();
100 }
101
102 const char *cstr(RTLIL::SigBit sig)
103 {
104 cstr_bits_seen.insert(sig);
105
106 if (sig.wire == NULL) {
107 if (sig == RTLIL::State::S0) return config->false_type == "-" || config->false_type == "+" ? config->false_out.c_str() : "$false";
108 if (sig == RTLIL::State::S1) return config->true_type == "-" || config->true_type == "+" ? config->true_out.c_str() : "$true";
109 return config->undef_type == "-" || config->undef_type == "+" ? config->undef_out.c_str() : "$undef";
110 }
111
112 std::string str = RTLIL::unescape_id(sig.wire->name);
113 for (size_t i = 0; i < str.size(); i++)
114 if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
115 str[i] = '?';
116
117 if (sig.wire->width != 1)
118 str += stringf("[%d]", sig.wire->upto ? sig.wire->start_offset+sig.wire->width-sig.offset-1 : sig.wire->start_offset+sig.offset);
119
120 cstr_buf.push_back(str);
121 return cstr_buf.back().c_str();
122 }
123
124 const char *cstr_init(RTLIL::SigBit sig)
125 {
126 sigmap.apply(sig);
127
128 if (init_bits.count(sig) == 0)
129 return " 2";
130
131 string str = stringf(" %d", init_bits.at(sig));
132
133 cstr_buf.push_back(str);
134 return cstr_buf.back().c_str();
135 }
136
137 const char *subckt_or_gate(std::string cell_type)
138 {
139 if (!config->gates_mode)
140 return "subckt";
141 if (!design->modules_.count(RTLIL::escape_id(cell_type)))
142 return "gate";
143 if (design->modules_.at(RTLIL::escape_id(cell_type))->get_blackbox_attribute())
144 return "gate";
145 return "subckt";
146 }
147
148 void dump_params(const char *command, dict<IdString, Const> &params)
149 {
150 for (auto &param : params) {
151 f << stringf("%s %s ", command, RTLIL::id2cstr(param.first));
152 if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
153 std::string str = param.second.decode_string();
154 f << stringf("\"");
155 for (char ch : str)
156 if (ch == '"' || ch == '\\')
157 f << stringf("\\%c", ch);
158 else if (ch < 32 || ch >= 127)
159 f << stringf("\\%03o", ch);
160 else
161 f << stringf("%c", ch);
162 f << stringf("\"\n");
163 } else
164 f << stringf("%s\n", param.second.as_string().c_str());
165 }
166 }
167
168 void dump()
169 {
170 f << stringf("\n");
171 f << stringf(".model %s\n", cstr(module->name));
172
173 std::map<int, RTLIL::Wire*> inputs, outputs;
174
175 for (auto &wire_it : module->wires_) {
176 RTLIL::Wire *wire = wire_it.second;
177 if (wire->port_input)
178 inputs[wire->port_id] = wire;
179 if (wire->port_output)
180 outputs[wire->port_id] = wire;
181 }
182
183 f << stringf(".inputs");
184 for (auto &it : inputs) {
185 RTLIL::Wire *wire = it.second;
186 for (int i = 0; i < wire->width; i++)
187 f << stringf(" %s", cstr(RTLIL::SigSpec(wire, i)));
188 }
189 f << stringf("\n");
190
191 f << stringf(".outputs");
192 for (auto &it : outputs) {
193 RTLIL::Wire *wire = it.second;
194 for (int i = 0; i < wire->width; i++)
195 f << stringf(" %s", cstr(RTLIL::SigSpec(wire, i)));
196 }
197 f << stringf("\n");
198
199 if (module->get_blackbox_attribute()) {
200 f << stringf(".blackbox\n");
201 f << stringf(".end\n");
202 return;
203 }
204
205 if (!config->impltf_mode) {
206 if (!config->false_type.empty()) {
207 if (config->false_type == "+")
208 f << stringf(".names %s\n", config->false_out.c_str());
209 else if (config->false_type != "-")
210 f << stringf(".%s %s %s=$false\n", subckt_or_gate(config->false_type),
211 config->false_type.c_str(), config->false_out.c_str());
212 } else
213 f << stringf(".names $false\n");
214 if (!config->true_type.empty()) {
215 if (config->true_type == "+")
216 f << stringf(".names %s\n1\n", config->true_out.c_str());
217 else if (config->true_type != "-")
218 f << stringf(".%s %s %s=$true\n", subckt_or_gate(config->true_type),
219 config->true_type.c_str(), config->true_out.c_str());
220 } else
221 f << stringf(".names $true\n1\n");
222 if (!config->undef_type.empty()) {
223 if (config->undef_type == "+")
224 f << stringf(".names %s\n", config->undef_out.c_str());
225 else if (config->undef_type != "-")
226 f << stringf(".%s %s %s=$undef\n", subckt_or_gate(config->undef_type),
227 config->undef_type.c_str(), config->undef_out.c_str());
228 } else
229 f << stringf(".names $undef\n");
230 }
231
232 for (auto &cell_it : module->cells_)
233 {
234 RTLIL::Cell *cell = cell_it.second;
235
236 if (config->unbuf_types.count(cell->type)) {
237 auto portnames = config->unbuf_types.at(cell->type);
238 f << stringf(".names %s %s\n1 1\n",
239 cstr(cell->getPort(portnames.first)), cstr(cell->getPort(portnames.second)));
240 continue;
241 }
242
243 if (!config->icells_mode && cell->type == "$_NOT_") {
244 f << stringf(".names %s %s\n0 1\n",
245 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y")));
246 goto internal_cell;
247 }
248
249 if (!config->icells_mode && cell->type == "$_AND_") {
250 f << stringf(".names %s %s %s\n11 1\n",
251 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
252 goto internal_cell;
253 }
254
255 if (!config->icells_mode && cell->type == "$_OR_") {
256 f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
257 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
258 goto internal_cell;
259 }
260
261 if (!config->icells_mode && cell->type == "$_XOR_") {
262 f << stringf(".names %s %s %s\n10 1\n01 1\n",
263 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
264 goto internal_cell;
265 }
266
267 if (!config->icells_mode && cell->type == "$_NAND_") {
268 f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
269 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
270 goto internal_cell;
271 }
272
273 if (!config->icells_mode && cell->type == "$_NOR_") {
274 f << stringf(".names %s %s %s\n00 1\n",
275 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
276 goto internal_cell;
277 }
278
279 if (!config->icells_mode && cell->type == "$_XNOR_") {
280 f << stringf(".names %s %s %s\n11 1\n00 1\n",
281 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
282 goto internal_cell;
283 }
284
285 if (!config->icells_mode && cell->type == "$_ANDNOT_") {
286 f << stringf(".names %s %s %s\n10 1\n",
287 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
288 goto internal_cell;
289 }
290
291 if (!config->icells_mode && cell->type == "$_ORNOT_") {
292 f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
293 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
294 goto internal_cell;
295 }
296
297 if (!config->icells_mode && cell->type == "$_AOI3_") {
298 f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
299 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y")));
300 goto internal_cell;
301 }
302
303 if (!config->icells_mode && cell->type == "$_OAI3_") {
304 f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
305 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y")));
306 goto internal_cell;
307 }
308
309 if (!config->icells_mode && cell->type == "$_AOI4_") {
310 f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
311 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
312 cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y")));
313 goto internal_cell;
314 }
315
316 if (!config->icells_mode && cell->type == "$_OAI4_") {
317 f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
318 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
319 cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y")));
320 goto internal_cell;
321 }
322
323 if (!config->icells_mode && cell->type == "$_MUX_") {
324 f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
325 cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
326 cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y")));
327 goto internal_cell;
328 }
329
330 if (!config->icells_mode && cell->type == "$_FF_") {
331 f << stringf(".latch %s %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
332 cstr_init(cell->getPort("\\Q")));
333 goto internal_cell;
334 }
335
336 if (!config->icells_mode && cell->type == "$_DFF_N_") {
337 f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
338 cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q")));
339 goto internal_cell;
340 }
341
342 if (!config->icells_mode && cell->type == "$_DFF_P_") {
343 f << stringf(".latch %s %s re %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
344 cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q")));
345 goto internal_cell;
346 }
347
348 if (!config->icells_mode && cell->type == "$_DLATCH_N_") {
349 f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
350 cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q")));
351 goto internal_cell;
352 }
353
354 if (!config->icells_mode && cell->type == "$_DLATCH_P_") {
355 f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
356 cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q")));
357 goto internal_cell;
358 }
359
360 if (!config->icells_mode && cell->type == "$lut") {
361 f << stringf(".names");
362 auto &inputs = cell->getPort("\\A");
363 auto width = cell->parameters.at("\\WIDTH").as_int();
364 log_assert(inputs.size() == width);
365 for (int i = width-1; i >= 0; i--)
366 f << stringf(" %s", cstr(inputs.extract(i, 1)));
367 auto &output = cell->getPort("\\Y");
368 log_assert(output.size() == 1);
369 f << stringf(" %s", cstr(output));
370 f << stringf("\n");
371 RTLIL::SigSpec mask = cell->parameters.at("\\LUT");
372 for (int i = 0; i < (1 << width); i++)
373 if (mask[i] == RTLIL::S1) {
374 for (int j = width-1; j >= 0; j--) {
375 f << ((i>>j)&1 ? '1' : '0');
376 }
377 f << " 1\n";
378 }
379 goto internal_cell;
380 }
381
382 if (!config->icells_mode && cell->type == "$sop") {
383 f << stringf(".names");
384 auto &inputs = cell->getPort("\\A");
385 auto width = cell->parameters.at("\\WIDTH").as_int();
386 auto depth = cell->parameters.at("\\DEPTH").as_int();
387 vector<State> table = cell->parameters.at("\\TABLE").bits;
388 while (GetSize(table) < 2*width*depth)
389 table.push_back(State::S0);
390 log_assert(inputs.size() == width);
391 for (int i = 0; i < width; i++)
392 f << stringf(" %s", cstr(inputs.extract(i, 1)));
393 auto &output = cell->getPort("\\Y");
394 log_assert(output.size() == 1);
395 f << stringf(" %s", cstr(output));
396 f << stringf("\n");
397 for (int i = 0; i < depth; i++) {
398 for (int j = 0; j < width; j++) {
399 bool pat0 = table.at(2*width*i + 2*j + 0) == State::S1;
400 bool pat1 = table.at(2*width*i + 2*j + 1) == State::S1;
401 if (pat0 && !pat1) f << "0";
402 else if (!pat0 && pat1) f << "1";
403 else f << "-";
404 }
405 f << " 1\n";
406 }
407 goto internal_cell;
408 }
409
410 f << stringf(".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type));
411 for (auto &conn : cell->connections())
412 {
413 if (conn.second.size() == 1) {
414 f << stringf(" %s=%s", cstr(conn.first), cstr(conn.second[0]));
415 continue;
416 }
417
418 Module *m = design->module(cell->type);
419 Wire *w = m ? m->wire(conn.first) : nullptr;
420
421 if (w == nullptr) {
422 for (int i = 0; i < GetSize(conn.second); i++)
423 f << stringf(" %s[%d]=%s", cstr(conn.first), i, cstr(conn.second[i]));
424 } else {
425 for (int i = 0; i < std::min(GetSize(conn.second), GetSize(w)); i++) {
426 SigBit sig(w, i);
427 f << stringf(" %s[%d]=%s", cstr(conn.first), sig.wire->upto ?
428 sig.wire->start_offset+sig.wire->width-sig.offset-1 :
429 sig.wire->start_offset+sig.offset, cstr(conn.second[i]));
430 }
431 }
432 }
433 f << stringf("\n");
434
435 if (config->cname_mode)
436 f << stringf(".cname %s\n", cstr(cell->name));
437 if (config->attr_mode)
438 dump_params(".attr", cell->attributes);
439 if (config->param_mode)
440 dump_params(".param", cell->parameters);
441
442 if (0) {
443 internal_cell:
444 if (config->iname_mode)
445 f << stringf(".cname %s\n", cstr(cell->name));
446 if (config->iattr_mode)
447 dump_params(".attr", cell->attributes);
448 }
449 }
450
451 for (auto &conn : module->connections())
452 for (int i = 0; i < conn.first.size(); i++)
453 {
454 SigBit lhs_bit = conn.first[i];
455 SigBit rhs_bit = conn.second[i];
456
457 if (config->noalias_mode && cstr_bits_seen.count(lhs_bit) == 0)
458 continue;
459
460 if (config->conn_mode)
461 f << stringf(".conn %s %s\n", cstr(rhs_bit), cstr(lhs_bit));
462 else if (!config->buf_type.empty())
463 f << stringf(".%s %s %s=%s %s=%s\n", subckt_or_gate(config->buf_type), config->buf_type.c_str(),
464 config->buf_in.c_str(), cstr(rhs_bit), config->buf_out.c_str(), cstr(lhs_bit));
465 else
466 f << stringf(".names %s %s\n1 1\n", cstr(rhs_bit), cstr(lhs_bit));
467 }
468
469 f << stringf(".end\n");
470 }
471
472 static void dump(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BlifDumperConfig &config)
473 {
474 BlifDumper dumper(f, module, design, &config);
475 dumper.dump();
476 }
477 };
478
479 struct BlifBackend : public Backend {
480 BlifBackend() : Backend("blif", "write design to BLIF file") { }
481 void help() YS_OVERRIDE
482 {
483 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
484 log("\n");
485 log(" write_blif [options] [filename]\n");
486 log("\n");
487 log("Write the current design to an BLIF file.\n");
488 log("\n");
489 log(" -top top_module\n");
490 log(" set the specified module as design top module\n");
491 log("\n");
492 log(" -buf <cell-type> <in-port> <out-port>\n");
493 log(" use cells of type <cell-type> with the specified port names for buffers\n");
494 log("\n");
495 log(" -unbuf <cell-type> <in-port> <out-port>\n");
496 log(" replace buffer cells with the specified name and port names with\n");
497 log(" a .names statement that models a buffer\n");
498 log("\n");
499 log(" -true <cell-type> <out-port>\n");
500 log(" -false <cell-type> <out-port>\n");
501 log(" -undef <cell-type> <out-port>\n");
502 log(" use the specified cell types to drive nets that are constant 1, 0, or\n");
503 log(" undefined. when '-' is used as <cell-type>, then <out-port> specifies\n");
504 log(" the wire name to be used for the constant signal and no cell driving\n");
505 log(" that wire is generated. when '+' is used as <cell-type>, then <out-port>\n");
506 log(" specifies the wire name to be used for the constant signal and a .names\n");
507 log(" statement is generated to drive the wire.\n");
508 log("\n");
509 log(" -noalias\n");
510 log(" if a net name is aliasing another net name, then by default a net\n");
511 log(" without fanout is created that is driven by the other net. This option\n");
512 log(" suppresses the generation of this nets without fanout.\n");
513 log("\n");
514 log("The following options can be useful when the generated file is not going to be\n");
515 log("read by a BLIF parser but a custom tool. It is recommended to not name the output\n");
516 log("file *.blif when any of this options is used.\n");
517 log("\n");
518 log(" -icells\n");
519 log(" do not translate Yosys's internal gates to generic BLIF logic\n");
520 log(" functions. Instead create .subckt or .gate lines for all cells.\n");
521 log("\n");
522 log(" -gates\n");
523 log(" print .gate instead of .subckt lines for all cells that are not\n");
524 log(" instantiations of other modules from this design.\n");
525 log("\n");
526 log(" -conn\n");
527 log(" do not generate buffers for connected wires. instead use the\n");
528 log(" non-standard .conn statement.\n");
529 log("\n");
530 log(" -attr\n");
531 log(" use the non-standard .attr statement to write cell attributes\n");
532 log("\n");
533 log(" -param\n");
534 log(" use the non-standard .param statement to write cell parameters\n");
535 log("\n");
536 log(" -cname\n");
537 log(" use the non-standard .cname statement to write cell names\n");
538 log("\n");
539 log(" -iname, -iattr\n");
540 log(" enable -cname and -attr functionality for .names statements\n");
541 log(" (the .cname and .attr statements will be included in the BLIF\n");
542 log(" output after the truth table for the .names statement)\n");
543 log("\n");
544 log(" -blackbox\n");
545 log(" write blackbox cells with .blackbox statement.\n");
546 log("\n");
547 log(" -impltf\n");
548 log(" do not write definitions for the $true, $false and $undef wires.\n");
549 log("\n");
550 }
551 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
552 {
553 std::string top_module_name;
554 std::string buf_type, buf_in, buf_out;
555 std::string true_type, true_out;
556 std::string false_type, false_out;
557 BlifDumperConfig config;
558
559 log_header(design, "Executing BLIF backend.\n");
560
561 size_t argidx;
562 for (argidx = 1; argidx < args.size(); argidx++)
563 {
564 if (args[argidx] == "-top" && argidx+1 < args.size()) {
565 top_module_name = args[++argidx];
566 continue;
567 }
568 if (args[argidx] == "-buf" && argidx+3 < args.size()) {
569 config.buf_type = args[++argidx];
570 config.buf_in = args[++argidx];
571 config.buf_out = args[++argidx];
572 continue;
573 }
574 if (args[argidx] == "-unbuf" && argidx+3 < args.size()) {
575 RTLIL::IdString unbuf_type = RTLIL::escape_id(args[++argidx]);
576 RTLIL::IdString unbuf_in = RTLIL::escape_id(args[++argidx]);
577 RTLIL::IdString unbuf_out = RTLIL::escape_id(args[++argidx]);
578 config.unbuf_types[unbuf_type] = std::pair<RTLIL::IdString, RTLIL::IdString>(unbuf_in, unbuf_out);
579 continue;
580 }
581 if (args[argidx] == "-true" && argidx+2 < args.size()) {
582 config.true_type = args[++argidx];
583 config.true_out = args[++argidx];
584 continue;
585 }
586 if (args[argidx] == "-false" && argidx+2 < args.size()) {
587 config.false_type = args[++argidx];
588 config.false_out = args[++argidx];
589 continue;
590 }
591 if (args[argidx] == "-undef" && argidx+2 < args.size()) {
592 config.undef_type = args[++argidx];
593 config.undef_out = args[++argidx];
594 continue;
595 }
596 if (args[argidx] == "-icells") {
597 config.icells_mode = true;
598 continue;
599 }
600 if (args[argidx] == "-gates") {
601 config.gates_mode = true;
602 continue;
603 }
604 if (args[argidx] == "-conn") {
605 config.conn_mode = true;
606 continue;
607 }
608 if (args[argidx] == "-cname") {
609 config.cname_mode = true;
610 continue;
611 }
612 if (args[argidx] == "-param") {
613 config.param_mode = true;
614 continue;
615 }
616 if (args[argidx] == "-attr") {
617 config.attr_mode = true;
618 continue;
619 }
620 if (args[argidx] == "-iname") {
621 config.iname_mode = true;
622 continue;
623 }
624 if (args[argidx] == "-iattr") {
625 config.iattr_mode = true;
626 continue;
627 }
628 if (args[argidx] == "-blackbox") {
629 config.blackbox_mode = true;
630 continue;
631 }
632 if (args[argidx] == "-impltf") {
633 config.impltf_mode = true;
634 continue;
635 }
636 if (args[argidx] == "-noalias") {
637 config.noalias_mode = true;
638 continue;
639 }
640 break;
641 }
642 extra_args(f, filename, args, argidx);
643
644 if (top_module_name.empty())
645 for (auto & mod_it:design->modules_)
646 if (mod_it.second->get_bool_attribute("\\top"))
647 top_module_name = mod_it.first.str();
648
649 *f << stringf("# Generated by %s\n", yosys_version_str);
650
651 std::vector<RTLIL::Module*> mod_list;
652
653 design->sort();
654 for (auto module_it : design->modules_)
655 {
656 RTLIL::Module *module = module_it.second;
657 if (module->get_blackbox_attribute() && !config.blackbox_mode)
658 continue;
659
660 if (module->processes.size() != 0)
661 log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
662 if (module->memories.size() != 0)
663 log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
664
665 if (module->name == RTLIL::escape_id(top_module_name)) {
666 BlifDumper::dump(*f, module, design, config);
667 top_module_name.clear();
668 continue;
669 }
670
671 mod_list.push_back(module);
672 }
673
674 if (!top_module_name.empty())
675 log_error("Can't find top module `%s'!\n", top_module_name.c_str());
676
677 for (auto module : mod_list)
678 BlifDumper::dump(*f, module, design, config);
679 }
680 } BlifBackend;
681
682 PRIVATE_NAMESPACE_END