projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Try way that doesn't involve creating a new wire
[yosys.git] / backends / btor / btor.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
25 #include <string>
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
30 struct BtorWorker
31 {
32 std::ostream &f;
33 SigMap sigmap;
34 RTLIL::Module *module;
35 bool verbose;
36 bool single_bad;
37
38 int next_nid = 1;
39 int initstate_nid = -1;
40
41 // <width> => <sid>
42 dict<int, int> sorts_bv;
43
44 // (<address-width>, <data-width>) => <sid>
45 dict<pair<int, int>, int> sorts_mem;
46
47 // SigBit => (<nid>, <bitidx>)
48 dict<SigBit, pair<int, int>> bit_nid;
49
50 // <nid> => <bvwidth>
51 dict<int, int> nid_width;
52
53 // SigSpec => <nid>
54 dict<SigSpec, int> sig_nid;
55
56 // bit to driving cell
57 dict<SigBit, Cell*> bit_cell;
58
59 // nids for constants
60 dict<Const, int> consts;
61
62 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
63 vector<pair<int, Cell*>> ff_todo;
64
65 pool<Cell*> cell_recursion_guard;
66 vector<int> bad_properties;
67 dict<SigBit, bool> initbits;
68 pool<Wire*> statewires;
69 string indent;
70
71 void btorf(const char *fmt, ...)
72 {
73 va_list ap;
74 va_start(ap, fmt);
75 f << indent << vstringf(fmt, ap);
76 va_end(ap);
77 }
78
79 void btorf_push(const string &id)
80 {
81 if (verbose) {
82 f << indent << stringf(" ; begin %s\n", id.c_str());
83 indent += " ";
84 }
85 }
86
87 void btorf_pop(const string &id)
88 {
89 if (verbose) {
90 indent = indent.substr(4);
91 f << indent << stringf(" ; end %s\n", id.c_str());
92 }
93 }
94
95 int get_bv_sid(int width)
96 {
97 if (sorts_bv.count(width) == 0) {
98 int nid = next_nid++;
99 btorf("%d sort bitvec %d\n", nid, width);
100 sorts_bv[width] = nid;
101 }
102 return sorts_bv.at(width);
103 }
104
105 int get_mem_sid(int abits, int dbits)
106 {
107 pair<int, int> key(abits, dbits);
108 if (sorts_mem.count(key) == 0) {
109 int addr_sid = get_bv_sid(abits);
110 int data_sid = get_bv_sid(dbits);
111 int nid = next_nid++;
112 btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
113 sorts_mem[key] = nid;
114 }
115 return sorts_mem.at(key);
116 }
117
118 void add_nid_sig(int nid, const SigSpec &sig)
119 {
120 if (verbose)
121 f << indent << stringf("; %d %s\n", nid, log_signal(sig));
122
123 for (int i = 0; i < GetSize(sig); i++)
124 bit_nid[sig[i]] = make_pair(nid, i);
125
126 sig_nid[sig] = nid;
127 nid_width[nid] = GetSize(sig);
128 }
129
130 void export_cell(Cell *cell)
131 {
132 if (cell_recursion_guard.count(cell)) {
133 string cell_list;
134 for (auto c : cell_recursion_guard)
135 cell_list += stringf("\n %s", log_id(c));
136 log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
137 }
138
139 cell_recursion_guard.insert(cell);
140 btorf_push(log_id(cell));
141
142 if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
143 "$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
144 {
145 string btor_op;
146 if (cell->type == "$add") btor_op = "add";
147 if (cell->type == "$sub") btor_op = "sub";
148 if (cell->type == "$mul") btor_op = "mul";
149 if (cell->type.in("$shl", "$sshl")) btor_op = "sll";
150 if (cell->type == "$shr") btor_op = "srl";
151 if (cell->type == "$sshr") btor_op = "sra";
152 if (cell->type.in("$shift", "$shiftx")) btor_op = "shift";
153 if (cell->type.in("$and", "$_AND_")) btor_op = "and";
154 if (cell->type.in("$or", "$_OR_")) btor_op = "or";
155 if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor";
156 if (cell->type == "$concat") btor_op = "concat";
157 if (cell->type == "$_NAND_") btor_op = "nand";
158 if (cell->type == "$_NOR_") btor_op = "nor";
159 if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
160 log_assert(!btor_op.empty());
161
162 int width = GetSize(cell->getPort("\\Y"));
163 width = std::max(width, GetSize(cell->getPort("\\A")));
164 width = std::max(width, GetSize(cell->getPort("\\B")));
165
166 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
167 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
168
169 if (btor_op == "shift" && !b_signed)
170 btor_op = "srl";
171
172 if (cell->type.in("$shl", "$sshl", "$shr", "$sshr"))
173 b_signed = false;
174
175 if (cell->type == "$sshr" && !a_signed)
176 btor_op = "srl";
177
178 int sid = get_bv_sid(width);
179 int nid;
180
181 if (btor_op == "shift")
182 {
183 int nid_a = get_sig_nid(cell->getPort("\\A"), width, false);
184 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
185
186 int nid_r = next_nid++;
187 btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);
188
189 int nid_b_neg = next_nid++;
190 btorf("%d neg %d %d\n", nid_b_neg, sid, nid_b);
191
192 int nid_l = next_nid++;
193 btorf("%d sll %d %d %d\n", nid_l, sid, nid_a, nid_b_neg);
194
195 int sid_bit = get_bv_sid(1);
196 int nid_zero = get_sig_nid(Const(0, width));
197 int nid_b_ltz = next_nid++;
198 btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
199
200 nid = next_nid++;
201 btorf("%d ite %d %d %d %d\n", nid, sid, nid_b_ltz, nid_l, nid_r);
202 }
203 else
204 {
205 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
206 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
207
208 nid = next_nid++;
209 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
210 }
211
212 SigSpec sig = sigmap(cell->getPort("\\Y"));
213
214 if (GetSize(sig) < width) {
215 int sid = get_bv_sid(GetSize(sig));
216 int nid2 = next_nid++;
217 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
218 nid = nid2;
219 }
220
221 add_nid_sig(nid, sig);
222 goto okay;
223 }
224
225 if (cell->type.in("$div", "$mod"))
226 {
227 string btor_op;
228 if (cell->type == "$div") btor_op = "div";
229 if (cell->type == "$mod") btor_op = "rem";
230 log_assert(!btor_op.empty());
231
232 int width = GetSize(cell->getPort("\\Y"));
233 width = std::max(width, GetSize(cell->getPort("\\A")));
234 width = std::max(width, GetSize(cell->getPort("\\B")));
235
236 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
237 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
238
239 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
240 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
241
242 int sid = get_bv_sid(width);
243 int nid = next_nid++;
244 btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);
245
246 SigSpec sig = sigmap(cell->getPort("\\Y"));
247
248 if (GetSize(sig) < width) {
249 int sid = get_bv_sid(GetSize(sig));
250 int nid2 = next_nid++;
251 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
252 nid = nid2;
253 }
254
255 add_nid_sig(nid, sig);
256 goto okay;
257 }
258
259 if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
260 {
261 int sid = get_bv_sid(1);
262 int nid_a = get_sig_nid(cell->getPort("\\A"));
263 int nid_b = get_sig_nid(cell->getPort("\\B"));
264
265 int nid1 = next_nid++;
266 int nid2 = next_nid++;
267
268 if (cell->type == "$_ANDNOT_") {
269 btorf("%d not %d %d\n", nid1, sid, nid_b);
270 btorf("%d and %d %d %d\n", nid2, sid, nid_a, nid1);
271 }
272
273 if (cell->type == "$_ORNOT_") {
274 btorf("%d not %d %d\n", nid1, sid, nid_b);
275 btorf("%d or %d %d %d\n", nid2, sid, nid_a, nid1);
276 }
277
278 SigSpec sig = sigmap(cell->getPort("\\Y"));
279 add_nid_sig(nid2, sig);
280 goto okay;
281 }
282
283 if (cell->type.in("$_OAI3_", "$_AOI3_"))
284 {
285 int sid = get_bv_sid(1);
286 int nid_a = get_sig_nid(cell->getPort("\\A"));
287 int nid_b = get_sig_nid(cell->getPort("\\B"));
288 int nid_c = get_sig_nid(cell->getPort("\\C"));
289
290 int nid1 = next_nid++;
291 int nid2 = next_nid++;
292 int nid3 = next_nid++;
293
294 if (cell->type == "$_OAI3_") {
295 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
296 btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
297 btorf("%d not %d %d\n", nid3, sid, nid2);
298 }
299
300 if (cell->type == "$_AOI3_") {
301 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
302 btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
303 btorf("%d not %d %d\n", nid3, sid, nid2);
304 }
305
306 SigSpec sig = sigmap(cell->getPort("\\Y"));
307 add_nid_sig(nid3, sig);
308 goto okay;
309 }
310
311 if (cell->type.in("$_OAI4_", "$_AOI4_"))
312 {
313 int sid = get_bv_sid(1);
314 int nid_a = get_sig_nid(cell->getPort("\\A"));
315 int nid_b = get_sig_nid(cell->getPort("\\B"));
316 int nid_c = get_sig_nid(cell->getPort("\\C"));
317 int nid_d = get_sig_nid(cell->getPort("\\D"));
318
319 int nid1 = next_nid++;
320 int nid2 = next_nid++;
321 int nid3 = next_nid++;
322 int nid4 = next_nid++;
323
324 if (cell->type == "$_OAI4_") {
325 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
326 btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
327 btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
328 btorf("%d not %d %d\n", nid4, sid, nid3);
329 }
330
331 if (cell->type == "$_AOI4_") {
332 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
333 btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
334 btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
335 btorf("%d not %d %d\n", nid4, sid, nid3);
336 }
337
338 SigSpec sig = sigmap(cell->getPort("\\Y"));
339 add_nid_sig(nid4, sig);
340 goto okay;
341 }
342
343 if (cell->type.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt"))
344 {
345 string btor_op;
346 if (cell->type == "$lt") btor_op = "lt";
347 if (cell->type == "$le") btor_op = "lte";
348 if (cell->type.in("$eq", "$eqx")) btor_op = "eq";
349 if (cell->type.in("$ne", "$nex")) btor_op = "neq";
350 if (cell->type == "$ge") btor_op = "gte";
351 if (cell->type == "$gt") btor_op = "gt";
352 log_assert(!btor_op.empty());
353
354 int width = 1;
355 width = std::max(width, GetSize(cell->getPort("\\A")));
356 width = std::max(width, GetSize(cell->getPort("\\B")));
357
358 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
359 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
360
361 int sid = get_bv_sid(1);
362 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
363 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
364
365 int nid = next_nid++;
366 if (cell->type.in("$lt", "$le", "$ge", "$gt")) {
367 btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);
368 } else {
369 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
370 }
371
372 SigSpec sig = sigmap(cell->getPort("\\Y"));
373
374 if (GetSize(sig) > 1) {
375 int sid = get_bv_sid(GetSize(sig));
376 int nid2 = next_nid++;
377 btorf("%d uext %d %d %d\n", nid2, sid, nid, GetSize(sig) - 1);
378 nid = nid2;
379 }
380
381 add_nid_sig(nid, sig);
382 goto okay;
383 }
384
385 if (cell->type.in("$not", "$neg", "$_NOT_"))
386 {
387 string btor_op;
388 if (cell->type.in("$not", "$_NOT_")) btor_op = "not";
389 if (cell->type == "$neg") btor_op = "neg";
390 log_assert(!btor_op.empty());
391
392 int width = GetSize(cell->getPort("\\Y"));
393 width = std::max(width, GetSize(cell->getPort("\\A")));
394
395 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
396
397 int sid = get_bv_sid(width);
398 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
399
400 int nid = next_nid++;
401 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
402
403 SigSpec sig = sigmap(cell->getPort("\\Y"));
404
405 if (GetSize(sig) < width) {
406 int sid = get_bv_sid(GetSize(sig));
407 int nid2 = next_nid++;
408 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
409 nid = nid2;
410 }
411
412 add_nid_sig(nid, sig);
413 goto okay;
414 }
415
416 if (cell->type.in("$logic_and", "$logic_or", "$logic_not"))
417 {
418 string btor_op;
419 if (cell->type == "$logic_and") btor_op = "and";
420 if (cell->type == "$logic_or") btor_op = "or";
421 if (cell->type == "$logic_not") btor_op = "not";
422 log_assert(!btor_op.empty());
423
424 int sid = get_bv_sid(1);
425 int nid_a = get_sig_nid(cell->getPort("\\A"));
426 int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort("\\B")) : 0;
427
428 if (GetSize(cell->getPort("\\A")) > 1) {
429 int nid_red_a = next_nid++;
430 btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
431 nid_a = nid_red_a;
432 }
433
434 if (btor_op != "not" && GetSize(cell->getPort("\\B")) > 1) {
435 int nid_red_b = next_nid++;
436 btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
437 nid_b = nid_red_b;
438 }
439
440 int nid = next_nid++;
441 if (btor_op != "not")
442 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
443 else
444 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
445
446 SigSpec sig = sigmap(cell->getPort("\\Y"));
447
448 if (GetSize(sig) > 1) {
449 int sid = get_bv_sid(GetSize(sig));
450 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
451 int nid2 = next_nid++;
452 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
453 nid = nid2;
454 }
455
456 add_nid_sig(nid, sig);
457 goto okay;
458 }
459
460 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor"))
461 {
462 string btor_op;
463 if (cell->type == "$reduce_and") btor_op = "redand";
464 if (cell->type.in("$reduce_or", "$reduce_bool")) btor_op = "redor";
465 if (cell->type.in("$reduce_xor", "$reduce_xnor")) btor_op = "redxor";
466 log_assert(!btor_op.empty());
467
468 int sid = get_bv_sid(1);
469 int nid_a = get_sig_nid(cell->getPort("\\A"));
470
471 int nid = next_nid++;
472 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
473
474 if (cell->type == "$reduce_xnor") {
475 int nid2 = next_nid++;
476 btorf("%d not %d %d %d\n", nid2, sid, nid);
477 nid = nid2;
478 }
479
480 SigSpec sig = sigmap(cell->getPort("\\Y"));
481
482 if (GetSize(sig) > 1) {
483 int sid = get_bv_sid(GetSize(sig));
484 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
485 int nid2 = next_nid++;
486 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
487 nid = nid2;
488 }
489
490 add_nid_sig(nid, sig);
491 goto okay;
492 }
493
494 if (cell->type.in("$mux", "$_MUX_"))
495 {
496 SigSpec sig_a = sigmap(cell->getPort("\\A"));
497 SigSpec sig_b = sigmap(cell->getPort("\\B"));
498 SigSpec sig_s = sigmap(cell->getPort("\\S"));
499 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
500
501 int nid_a = get_sig_nid(sig_a);
502 int nid_b = get_sig_nid(sig_b);
503 int nid_s = get_sig_nid(sig_s);
504
505 int sid = get_bv_sid(GetSize(sig_y));
506 int nid = next_nid++;
507 btorf("%d ite %d %d %d %d\n", nid, sid, nid_s, nid_b, nid_a);
508
509 add_nid_sig(nid, sig_y);
510 goto okay;
511 }
512
513 if (cell->type == "$pmux")
514 {
515 SigSpec sig_a = sigmap(cell->getPort("\\A"));
516 SigSpec sig_b = sigmap(cell->getPort("\\B"));
517 SigSpec sig_s = sigmap(cell->getPort("\\S"));
518 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
519
520 int width = GetSize(sig_a);
521 int sid = get_bv_sid(width);
522 int nid = get_sig_nid(sig_a);
523
524 for (int i = 0; i < GetSize(sig_s); i++) {
525 int nid_b = get_sig_nid(sig_b.extract(i*width, width));
526 int nid_s = get_sig_nid(sig_s.extract(i));
527 int nid2 = next_nid++;
528 btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
529 nid = nid2;
530 }
531
532 add_nid_sig(nid, sig_y);
533 goto okay;
534 }
535
536 if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N", "$_FF_"))
537 {
538 SigSpec sig_d = sigmap(cell->getPort("\\D"));
539 SigSpec sig_q = sigmap(cell->getPort("\\Q"));
540
541 IdString symbol;
542
543 if (sig_q.is_wire()) {
544 Wire *w = sig_q.as_wire();
545 if (w->port_id == 0) {
546 statewires.insert(w);
547 symbol = w->name;
548 }
549 }
550
551 Const initval;
552 for (int i = 0; i < GetSize(sig_q); i++)
553 if (initbits.count(sig_q[i]))
554 initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
555 else
556 initval.bits.push_back(State::Sx);
557
558 int nid_init_val = -1;
559
560 if (!initval.is_fully_undef())
561 nid_init_val = get_sig_nid(initval);
562
563 int sid = get_bv_sid(GetSize(sig_q));
564 int nid = next_nid++;
565
566 if (symbol.empty())
567 btorf("%d state %d\n", nid, sid);
568 else
569 btorf("%d state %d %s\n", nid, sid, log_id(symbol));
570
571 if (nid_init_val >= 0) {
572 int nid_init = next_nid++;
573 if (verbose)
574 btorf("; initval = %s\n", log_signal(initval));
575 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
576 }
577
578 ff_todo.push_back(make_pair(nid, cell));
579 add_nid_sig(nid, sig_q);
580 goto okay;
581 }
582
583 if (cell->type.in("$anyconst", "$anyseq"))
584 {
585 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
586
587 int sid = get_bv_sid(GetSize(sig_y));
588 int nid = next_nid++;
589
590 btorf("%d state %d\n", nid, sid);
591
592 if (cell->type == "$anyconst") {
593 int nid2 = next_nid++;
594 btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
595 }
596
597 add_nid_sig(nid, sig_y);
598 goto okay;
599 }
600
601 if (cell->type == "$initstate")
602 {
603 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
604
605 if (initstate_nid < 0)
606 {
607 int sid = get_bv_sid(1);
608 int one_nid = get_sig_nid(Const(1, 1));
609 int zero_nid = get_sig_nid(Const(0, 1));
610 initstate_nid = next_nid++;
611 btorf("%d state %d\n", initstate_nid, sid);
612 btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
613 btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
614 }
615
616 add_nid_sig(initstate_nid, sig_y);
617 goto okay;
618 }
619
620 if (cell->type == "$mem")
621 {
622 int abits = cell->getParam("\\ABITS").as_int();
623 int width = cell->getParam("\\WIDTH").as_int();
624 int nwords = cell->getParam("\\SIZE").as_int();
625 int rdports = cell->getParam("\\RD_PORTS").as_int();
626 int wrports = cell->getParam("\\WR_PORTS").as_int();
627
628 Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE");
629 Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE");
630
631 bool asyncwr = wr_clk_en.is_fully_zero();
632
633 if (!asyncwr && !wr_clk_en.is_fully_ones())
634 log_error("Memory %s.%s has mixed async/sync write ports.\n",
635 log_id(module), log_id(cell));
636
637 if (!rd_clk_en.is_fully_zero())
638 log_error("Memory %s.%s has sync read ports.\n",
639 log_id(module), log_id(cell));
640
641 SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR"));
642 SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA"));
643
644 SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
645 SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
646 SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
647
648 int data_sid = get_bv_sid(width);
649 int bool_sid = get_bv_sid(1);
650 int sid = get_mem_sid(abits, width);
651
652 Const initdata = cell->getParam("\\INIT");
653 initdata.exts(nwords*width);
654 int nid_init_val = -1;
655
656 if (!initdata.is_fully_undef())
657 {
658 bool constword = true;
659 Const firstword = initdata.extract(0, width);
660
661 for (int i = 1; i < nwords; i++) {
662 Const thisword = initdata.extract(i*width, width);
663 if (thisword != firstword) {
664 constword = false;
665 break;
666 }
667 }
668
669 if (constword)
670 {
671 if (verbose)
672 btorf("; initval = %s\n", log_signal(firstword));
673 nid_init_val = get_sig_nid(firstword);
674 }
675 else
676 {
677 int nid_init_val = next_nid++;
678 btorf("%d state %d\n", nid_init_val, sid);
679
680 for (int i = 0; i < nwords; i++) {
681 Const thisword = initdata.extract(i*width, width);
682 if (thisword.is_fully_undef())
683 continue;
684 Const thisaddr(i, abits);
685 int nid_thisword = get_sig_nid(thisword);
686 int nid_thisaddr = get_sig_nid(thisaddr);
687 int last_nid_init_val = nid_init_val;
688 nid_init_val = next_nid++;
689 if (verbose)
690 btorf("; initval[%d] = %s\n", i, log_signal(thisword));
691 btorf("%d write %d %d %d %d\n", nid_init_val, sid, last_nid_init_val, nid_thisaddr, nid_thisword);
692 }
693 }
694 }
695
696
697 int nid = next_nid++;
698 int nid_head = nid;
699
700 if (cell->name[0] == '$')
701 btorf("%d state %d\n", nid, sid);
702 else
703 btorf("%d state %d %s\n", nid, sid, log_id(cell));
704
705 if (nid_init_val >= 0)
706 {
707 int nid_init = next_nid++;
708 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
709 }
710
711 if (asyncwr)
712 {
713 for (int port = 0; port < wrports; port++)
714 {
715 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
716 SigSpec wd = sig_wr_data.extract(port*width, width);
717 SigSpec we = sig_wr_en.extract(port*width, width);
718
719 int wa_nid = get_sig_nid(wa);
720 int wd_nid = get_sig_nid(wd);
721 int we_nid = get_sig_nid(we);
722
723 int nid2 = next_nid++;
724 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
725
726 int nid3 = next_nid++;
727 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
728
729 int nid4 = next_nid++;
730 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
731
732 int nid5 = next_nid++;
733 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
734
735 int nid6 = next_nid++;
736 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
737
738 int nid7 = next_nid++;
739 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
740
741 int nid8 = next_nid++;
742 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
743
744 int nid9 = next_nid++;
745 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
746
747 nid_head = nid9;
748 }
749 }
750
751 for (int port = 0; port < rdports; port++)
752 {
753 SigSpec ra = sig_rd_addr.extract(port*abits, abits);
754 SigSpec rd = sig_rd_data.extract(port*width, width);
755
756 int ra_nid = get_sig_nid(ra);
757 int rd_nid = next_nid++;
758
759 btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);
760
761 add_nid_sig(rd_nid, rd);
762 }
763
764 if (!asyncwr)
765 {
766 ff_todo.push_back(make_pair(nid, cell));
767 }
768 else
769 {
770 int nid2 = next_nid++;
771 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
772 }
773
774 goto okay;
775 }
776
777 log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
778
779 okay:
780 btorf_pop(log_id(cell));
781 cell_recursion_guard.erase(cell);
782 }
783
784 int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false)
785 {
786 int nid = -1;
787 sigmap.apply(sig);
788
789 for (auto bit : sig)
790 if (bit == State::Sx)
791 goto has_undef_bits;
792
793 if (0)
794 {
795 has_undef_bits:
796 SigSpec sig_mask_undef, sig_noundef;
797 int first_undef = -1;
798
799 for (int i = 0; i < GetSize(sig); i++)
800 if (sig[i] == State::Sx) {
801 if (first_undef < 0)
802 first_undef = i;
803 sig_mask_undef.append(State::S1);
804 sig_noundef.append(State::S0);
805 } else {
806 sig_mask_undef.append(State::S0);
807 sig_noundef.append(sig[i]);
808 }
809
810 if (to_width < 0 || first_undef < to_width)
811 {
812 int sid = get_bv_sid(GetSize(sig));
813
814 int nid_input = next_nid++;
815 btorf("%d input %d\n", nid_input, sid);
816
817 int nid_masked_input;
818 if (sig_mask_undef.is_fully_ones()) {
819 nid_masked_input = nid_input;
820 } else {
821 int nid_mask_undef = get_sig_nid(sig_mask_undef);
822 nid_masked_input = next_nid++;
823 btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
824 }
825
826 if (sig_noundef.is_fully_zero()) {
827 nid = nid_masked_input;
828 } else {
829 int nid_noundef = get_sig_nid(sig_noundef);
830 nid = next_nid++;
831 btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
832 }
833
834 goto extend_or_trim;
835 }
836
837 sig = sig_noundef;
838 }
839
840 if (sig_nid.count(sig) == 0)
841 {
842 // <nid>, <bitidx>
843 vector<pair<int, int>> nidbits;
844
845 // collect all bits
846 for (int i = 0; i < GetSize(sig); i++)
847 {
848 SigBit bit = sig[i];
849
850 if (bit_nid.count(bit) == 0)
851 {
852 if (bit.wire == nullptr)
853 {
854 Const c(bit.data);
855
856 while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
857 c.bits.push_back(sig[i+GetSize(c)].data);
858
859 if (consts.count(c) == 0) {
860 int sid = get_bv_sid(GetSize(c));
861 int nid = next_nid++;
862 btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
863 consts[c] = nid;
864 nid_width[nid] = GetSize(c);
865 }
866
867 int nid = consts.at(c);
868
869 for (int j = 0; j < GetSize(c); j++)
870 nidbits.push_back(make_pair(nid, j));
871
872 i += GetSize(c)-1;
873 continue;
874 }
875 else
876 {
877 if (bit_cell.count(bit) == 0)
878 log_error("No driver for signal bit %s.\n", log_signal(bit));
879 export_cell(bit_cell.at(bit));
880 log_assert(bit_nid.count(bit));
881 }
882 }
883
884 nidbits.push_back(bit_nid.at(bit));
885 }
886
887 int width = 0;
888 int nid = -1;
889
890 // group bits and emit slice-concat chain
891 for (int i = 0; i < GetSize(nidbits); i++)
892 {
893 int nid2 = nidbits[i].first;
894 int lower = nidbits[i].second;
895 int upper = lower;
896
897 while (i+1 < GetSize(nidbits) && nidbits[i+1].first == nidbits[i].first &&
898 nidbits[i+1].second == nidbits[i].second+1)
899 upper++, i++;
900
901 int nid3 = nid2;
902
903 if (lower != 0 || upper+1 != nid_width.at(nid2)) {
904 int sid = get_bv_sid(upper-lower+1);
905 nid3 = next_nid++;
906 btorf("%d slice %d %d %d %d\n", nid3, sid, nid2, upper, lower);
907 }
908
909 int nid4 = nid3;
910
911 if (nid >= 0) {
912 int sid = get_bv_sid(width+upper-lower+1);
913 nid4 = next_nid++;
914 btorf("%d concat %d %d %d\n", nid4, sid, nid3, nid);
915 }
916
917 width += upper-lower+1;
918 nid = nid4;
919 }
920
921 sig_nid[sig] = nid;
922 nid_width[nid] = width;
923 }
924
925 nid = sig_nid.at(sig);
926
927 extend_or_trim:
928 if (to_width >= 0 && to_width != GetSize(sig))
929 {
930 if (to_width < GetSize(sig))
931 {
932 int sid = get_bv_sid(to_width);
933 int nid2 = next_nid++;
934 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, to_width-1);
935 nid = nid2;
936 }
937 else
938 {
939 int sid = get_bv_sid(to_width);
940 int nid2 = next_nid++;
941 btorf("%d %s %d %d %d\n", nid2, is_signed ? "sext" : "uext",
942 sid, nid, to_width - GetSize(sig));
943 nid = nid2;
944 }
945 }
946
947 return nid;
948 }
949
950 BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad) :
951 f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad)
952 {
953 btorf_push("inputs");
954
955 for (auto wire : module->wires())
956 {
957 if (wire->attributes.count("\\init")) {
958 Const attrval = wire->attributes.at("\\init");
959 for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
960 if (attrval[i] == State::S0 || attrval[i] == State::S1)
961 initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
962 }
963
964 if (!wire->port_id || !wire->port_input)
965 continue;
966
967 SigSpec sig = sigmap(wire);
968 int sid = get_bv_sid(GetSize(sig));
969 int nid = next_nid++;
970
971 btorf("%d input %d %s\n", nid, sid, log_id(wire));
972 add_nid_sig(nid, sig);
973 }
974
975 btorf_pop("inputs");
976
977 for (auto cell : module->cells())
978 for (auto &conn : cell->connections())
979 {
980 if (!cell->output(conn.first))
981 continue;
982
983 for (auto bit : sigmap(conn.second))
984 bit_cell[bit] = cell;
985 }
986
987 for (auto wire : module->wires())
988 {
989 if (!wire->port_id || !wire->port_output)
990 continue;
991
992 btorf_push(stringf("output %s", log_id(wire)));
993
994 int nid = get_sig_nid(wire);
995 btorf("%d output %d %s\n", next_nid++, nid, log_id(wire));
996
997 btorf_pop(stringf("output %s", log_id(wire)));
998 }
999
1000 for (auto cell : module->cells())
1001 {
1002 if (cell->type == "$assume")
1003 {
1004 btorf_push(log_id(cell));
1005
1006 int sid = get_bv_sid(1);
1007 int nid_a = get_sig_nid(cell->getPort("\\A"));
1008 int nid_en = get_sig_nid(cell->getPort("\\EN"));
1009 int nid_not_en = next_nid++;
1010 int nid_a_or_not_en = next_nid++;
1011 int nid = next_nid++;
1012
1013 btorf("%d not %d %d\n", nid_not_en, sid, nid_en);
1014 btorf("%d or %d %d %d\n", nid_a_or_not_en, sid, nid_a, nid_not_en);
1015 btorf("%d constraint %d\n", nid, nid_a_or_not_en);
1016
1017 btorf_pop(log_id(cell));
1018 }
1019
1020 if (cell->type == "$assert")
1021 {
1022 btorf_push(log_id(cell));
1023
1024 int sid = get_bv_sid(1);
1025 int nid_a = get_sig_nid(cell->getPort("\\A"));
1026 int nid_en = get_sig_nid(cell->getPort("\\EN"));
1027 int nid_not_a = next_nid++;
1028 int nid_en_and_not_a = next_nid++;
1029
1030 btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
1031 btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);
1032
1033 if (single_bad) {
1034 bad_properties.push_back(nid_en_and_not_a);
1035 } else {
1036 int nid = next_nid++;
1037 btorf("%d bad %d\n", nid, nid_en_and_not_a);
1038 }
1039
1040 btorf_pop(log_id(cell));
1041 }
1042 }
1043
1044 for (auto wire : module->wires())
1045 {
1046 if (wire->port_id || wire->name[0] == '$')
1047 continue;
1048
1049 btorf_push(stringf("wire %s", log_id(wire)));
1050
1051 int sid = get_bv_sid(GetSize(wire));
1052 int nid = get_sig_nid(sigmap(wire));
1053
1054 if (statewires.count(wire))
1055 continue;
1056
1057 int this_nid = next_nid++;
1058 btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, log_id(wire));
1059
1060 btorf_pop(stringf("wire %s", log_id(wire)));
1061 continue;
1062 }
1063
1064 while (!ff_todo.empty())
1065 {
1066 vector<pair<int, Cell*>> todo;
1067 todo.swap(ff_todo);
1068
1069 for (auto &it : todo)
1070 {
1071 int nid = it.first;
1072 Cell *cell = it.second;
1073
1074 btorf_push(stringf("next %s", log_id(cell)));
1075
1076 if (cell->type == "$mem")
1077 {
1078 int abits = cell->getParam("\\ABITS").as_int();
1079 int width = cell->getParam("\\WIDTH").as_int();
1080 int wrports = cell->getParam("\\WR_PORTS").as_int();
1081
1082 SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
1083 SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
1084 SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
1085
1086 int data_sid = get_bv_sid(width);
1087 int bool_sid = get_bv_sid(1);
1088 int sid = get_mem_sid(abits, width);
1089 int nid_head = nid;
1090
1091 for (int port = 0; port < wrports; port++)
1092 {
1093 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
1094 SigSpec wd = sig_wr_data.extract(port*width, width);
1095 SigSpec we = sig_wr_en.extract(port*width, width);
1096
1097 int wa_nid = get_sig_nid(wa);
1098 int wd_nid = get_sig_nid(wd);
1099 int we_nid = get_sig_nid(we);
1100
1101 int nid2 = next_nid++;
1102 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
1103
1104 int nid3 = next_nid++;
1105 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
1106
1107 int nid4 = next_nid++;
1108 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
1109
1110 int nid5 = next_nid++;
1111 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
1112
1113 int nid6 = next_nid++;
1114 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
1115
1116 int nid7 = next_nid++;
1117 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
1118
1119 int nid8 = next_nid++;
1120 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
1121
1122 int nid9 = next_nid++;
1123 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
1124
1125 nid_head = nid9;
1126 }
1127
1128 int nid2 = next_nid++;
1129 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
1130 }
1131 else
1132 {
1133 SigSpec sig = sigmap(cell->getPort("\\D"));
1134 int nid_q = get_sig_nid(sig);
1135 int sid = get_bv_sid(GetSize(sig));
1136 btorf("%d next %d %d %d\n", next_nid++, sid, nid, nid_q);
1137 }
1138
1139 btorf_pop(stringf("next %s", log_id(cell)));
1140 }
1141 }
1142
1143 while (!bad_properties.empty())
1144 {
1145 vector<int> todo;
1146 bad_properties.swap(todo);
1147
1148 int sid = get_bv_sid(1);
1149 int cursor = 0;
1150
1151 while (cursor+1 < GetSize(todo))
1152 {
1153 int nid_a = todo[cursor++];
1154 int nid_b = todo[cursor++];
1155 int nid = next_nid++;
1156
1157 bad_properties.push_back(nid);
1158 btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
1159 }
1160
1161 if (!bad_properties.empty()) {
1162 if (cursor < GetSize(todo))
1163 bad_properties.push_back(todo[cursor++]);
1164 log_assert(cursor == GetSize(todo));
1165 } else {
1166 int nid = next_nid++;
1167 log_assert(cursor == 0);
1168 log_assert(GetSize(todo) == 1);
1169 btorf("%d bad %d\n", nid, todo[cursor]);
1170 }
1171 }
1172 }
1173 };
1174
1175 struct BtorBackend : public Backend {
1176 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1177 void help() YS_OVERRIDE
1178 {
1179 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1180 log("\n");
1181 log(" write_btor [options] [filename]\n");
1182 log("\n");
1183 log("Write a BTOR description of the current design.\n");
1184 log("\n");
1185 log(" -v\n");
1186 log(" Add comments and indentation to BTOR output file\n");
1187 log("\n");
1188 log(" -s\n");
1189 log(" Output only a single bad property for all asserts\n");
1190 log("\n");
1191 }
1192 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1193 {
1194 bool verbose = false, single_bad = false;
1195
1196 log_header(design, "Executing BTOR backend.\n");
1197
1198 size_t argidx;
1199 for (argidx = 1; argidx < args.size(); argidx++)
1200 {
1201 if (args[argidx] == "-v") {
1202 verbose = true;
1203 continue;
1204 }
1205 if (args[argidx] == "-s") {
1206 single_bad = true;
1207 continue;
1208 }
1209 break;
1210 }
1211 extra_args(f, filename, args, argidx);
1212
1213 RTLIL::Module *topmod = design->top_module();
1214
1215 if (topmod == nullptr)
1216 log_cmd_error("No top module found.\n");
1217
1218 *f << stringf("; BTOR description generated by %s for module %s.\n",
1219 yosys_version_str, log_id(topmod));
1220
1221 BtorWorker(*f, topmod, verbose, single_bad);
1222
1223 *f << stringf("; end of yosys output\n");
1224 }
1225 } BtorBackend;
1226
1227 PRIVATE_NAMESPACE_END