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Merge pull request #2089 from rswarbrick/modports
[yosys.git] / backends / btor / btor.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] Btor2 , BtorMC and Boolector 3.0
21 // Aina Niemetz, Mathias Preiner, Clifford Wolf, Armin Biere
22 // Computer Aided Verification - 30th International Conference, CAV 2018
23 // https://cs.stanford.edu/people/niemetz/publication/2018/niemetzpreinerwolfbiere-cav18/
24
25 #include "kernel/rtlil.h"
26 #include "kernel/register.h"
27 #include "kernel/sigtools.h"
28 #include "kernel/celltypes.h"
29 #include "kernel/log.h"
30 #include <string>
31
32 USING_YOSYS_NAMESPACE
33 PRIVATE_NAMESPACE_BEGIN
34
35 struct BtorWorker
36 {
37 std::ostream &f;
38 SigMap sigmap;
39 RTLIL::Module *module;
40 bool verbose;
41 bool single_bad;
42 bool cover_mode;
43 bool print_internal_names;
44
45 int next_nid = 1;
46 int initstate_nid = -1;
47
48 // <width> => <sid>
49 dict<int, int> sorts_bv;
50
51 // (<address-width>, <data-width>) => <sid>
52 dict<pair<int, int>, int> sorts_mem;
53
54 // SigBit => (<nid>, <bitidx>)
55 dict<SigBit, pair<int, int>> bit_nid;
56
57 // <nid> => <bvwidth>
58 dict<int, int> nid_width;
59
60 // SigSpec => <nid>
61 dict<SigSpec, int> sig_nid;
62
63 // bit to driving cell
64 dict<SigBit, Cell*> bit_cell;
65
66 // nids for constants
67 dict<Const, int> consts;
68
69 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
70 vector<pair<int, Cell*>> ff_todo;
71
72 pool<Cell*> cell_recursion_guard;
73 vector<int> bad_properties;
74 dict<SigBit, bool> initbits;
75 pool<Wire*> statewires;
76 pool<string> srcsymbols;
77
78 string indent, info_filename;
79 vector<string> info_lines;
80 dict<int, int> info_clocks;
81
82 void btorf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
83 {
84 va_list ap;
85 va_start(ap, fmt);
86 f << indent << vstringf(fmt, ap);
87 va_end(ap);
88 }
89
90 void infof(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
91 {
92 va_list ap;
93 va_start(ap, fmt);
94 info_lines.push_back(vstringf(fmt, ap));
95 va_end(ap);
96 }
97
98 template<typename T>
99 string getinfo(T *obj, bool srcsym = false)
100 {
101 string infostr = log_id(obj);
102 if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
103 if (obj->attributes.count(ID::src)) {
104 string src = obj->attributes.at(ID::src).decode_string().c_str();
105 if (srcsym && infostr[0] == '$') {
106 std::replace(src.begin(), src.end(), ' ', '_');
107 if (srcsymbols.count(src) || module->count_id("\\" + src)) {
108 for (int i = 1;; i++) {
109 string s = stringf("%s-%d", src.c_str(), i);
110 if (!srcsymbols.count(s) && !module->count_id("\\" + s)) {
111 src = s;
112 break;
113 }
114 }
115 }
116 srcsymbols.insert(src);
117 infostr = src;
118 } else {
119 infostr += " ; " + src;
120 }
121 }
122 return " " + infostr;
123 }
124
125 void btorf_push(const string &id)
126 {
127 if (verbose) {
128 f << indent << stringf(" ; begin %s\n", id.c_str());
129 indent += " ";
130 }
131 }
132
133 void btorf_pop(const string &id)
134 {
135 if (verbose) {
136 indent = indent.substr(4);
137 f << indent << stringf(" ; end %s\n", id.c_str());
138 }
139 }
140
141 int get_bv_sid(int width)
142 {
143 if (sorts_bv.count(width) == 0) {
144 int nid = next_nid++;
145 btorf("%d sort bitvec %d\n", nid, width);
146 sorts_bv[width] = nid;
147 }
148 return sorts_bv.at(width);
149 }
150
151 int get_mem_sid(int abits, int dbits)
152 {
153 pair<int, int> key(abits, dbits);
154 if (sorts_mem.count(key) == 0) {
155 int addr_sid = get_bv_sid(abits);
156 int data_sid = get_bv_sid(dbits);
157 int nid = next_nid++;
158 btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
159 sorts_mem[key] = nid;
160 }
161 return sorts_mem.at(key);
162 }
163
164 void add_nid_sig(int nid, const SigSpec &sig)
165 {
166 if (verbose)
167 f << indent << stringf("; %d %s\n", nid, log_signal(sig));
168
169 for (int i = 0; i < GetSize(sig); i++)
170 bit_nid[sig[i]] = make_pair(nid, i);
171
172 sig_nid[sig] = nid;
173 nid_width[nid] = GetSize(sig);
174 }
175
176 void export_cell(Cell *cell)
177 {
178 if (cell_recursion_guard.count(cell)) {
179 string cell_list;
180 for (auto c : cell_recursion_guard)
181 cell_list += stringf("\n %s", log_id(c));
182 log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
183 }
184
185 cell_recursion_guard.insert(cell);
186 btorf_push(log_id(cell));
187
188 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
189 ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
190 {
191 string btor_op;
192 if (cell->type == ID($add)) btor_op = "add";
193 if (cell->type == ID($sub)) btor_op = "sub";
194 if (cell->type == ID($mul)) btor_op = "mul";
195 if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
196 if (cell->type == ID($shr)) btor_op = "srl";
197 if (cell->type == ID($sshr)) btor_op = "sra";
198 if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
199 if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
200 if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
201 if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
202 if (cell->type == ID($concat)) btor_op = "concat";
203 if (cell->type == ID($_NAND_)) btor_op = "nand";
204 if (cell->type == ID($_NOR_)) btor_op = "nor";
205 if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
206 log_assert(!btor_op.empty());
207
208 int width = GetSize(cell->getPort(ID::Y));
209 width = std::max(width, GetSize(cell->getPort(ID::A)));
210 width = std::max(width, GetSize(cell->getPort(ID::B)));
211
212 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
213 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
214
215 if (btor_op == "shift" && !b_signed)
216 btor_op = "srl";
217
218 if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
219 b_signed = false;
220
221 if (cell->type == ID($sshr) && !a_signed)
222 btor_op = "srl";
223
224 int sid = get_bv_sid(width);
225 int nid;
226
227 if (btor_op == "shift")
228 {
229 int nid_a = get_sig_nid(cell->getPort(ID::A), width, false);
230 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
231
232 int nid_r = next_nid++;
233 btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);
234
235 int nid_b_neg = next_nid++;
236 btorf("%d neg %d %d\n", nid_b_neg, sid, nid_b);
237
238 int nid_l = next_nid++;
239 btorf("%d sll %d %d %d\n", nid_l, sid, nid_a, nid_b_neg);
240
241 int sid_bit = get_bv_sid(1);
242 int nid_zero = get_sig_nid(Const(0, width));
243 int nid_b_ltz = next_nid++;
244 btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
245
246 nid = next_nid++;
247 btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell).c_str());
248 }
249 else
250 {
251 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
252 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
253
254 nid = next_nid++;
255 btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
256 }
257
258 SigSpec sig = sigmap(cell->getPort(ID::Y));
259
260 if (GetSize(sig) < width) {
261 int sid = get_bv_sid(GetSize(sig));
262 int nid2 = next_nid++;
263 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
264 nid = nid2;
265 }
266
267 add_nid_sig(nid, sig);
268 goto okay;
269 }
270
271 if (cell->type.in(ID($div), ID($mod), ID($modfloor)))
272 {
273 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
274 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
275
276 string btor_op;
277 if (cell->type == ID($div)) btor_op = "div";
278 // "rem" = truncating modulo
279 if (cell->type == ID($mod)) btor_op = "rem";
280 // "mod" = flooring modulo
281 if (cell->type == ID($modfloor)) {
282 // "umod" doesn't exist because it's the same as "urem"
283 btor_op = a_signed || b_signed ? "mod" : "rem";
284 }
285 log_assert(!btor_op.empty());
286
287 int width = GetSize(cell->getPort(ID::Y));
288 width = std::max(width, GetSize(cell->getPort(ID::A)));
289 width = std::max(width, GetSize(cell->getPort(ID::B)));
290
291 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
292 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
293
294 int sid = get_bv_sid(width);
295 int nid = next_nid++;
296 btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
297
298 SigSpec sig = sigmap(cell->getPort(ID::Y));
299
300 if (GetSize(sig) < width) {
301 int sid = get_bv_sid(GetSize(sig));
302 int nid2 = next_nid++;
303 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
304 nid = nid2;
305 }
306
307 add_nid_sig(nid, sig);
308 goto okay;
309 }
310
311 if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
312 {
313 int sid = get_bv_sid(1);
314 int nid_a = get_sig_nid(cell->getPort(ID::A));
315 int nid_b = get_sig_nid(cell->getPort(ID::B));
316
317 int nid1 = next_nid++;
318 int nid2 = next_nid++;
319
320 if (cell->type == ID($_ANDNOT_)) {
321 btorf("%d not %d %d\n", nid1, sid, nid_b);
322 btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
323 }
324
325 if (cell->type == ID($_ORNOT_)) {
326 btorf("%d not %d %d\n", nid1, sid, nid_b);
327 btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
328 }
329
330 SigSpec sig = sigmap(cell->getPort(ID::Y));
331 add_nid_sig(nid2, sig);
332 goto okay;
333 }
334
335 if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
336 {
337 int sid = get_bv_sid(1);
338 int nid_a = get_sig_nid(cell->getPort(ID::A));
339 int nid_b = get_sig_nid(cell->getPort(ID::B));
340 int nid_c = get_sig_nid(cell->getPort(ID::C));
341
342 int nid1 = next_nid++;
343 int nid2 = next_nid++;
344 int nid3 = next_nid++;
345
346 if (cell->type == ID($_OAI3_)) {
347 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
348 btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
349 btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
350 }
351
352 if (cell->type == ID($_AOI3_)) {
353 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
354 btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
355 btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
356 }
357
358 SigSpec sig = sigmap(cell->getPort(ID::Y));
359 add_nid_sig(nid3, sig);
360 goto okay;
361 }
362
363 if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
364 {
365 int sid = get_bv_sid(1);
366 int nid_a = get_sig_nid(cell->getPort(ID::A));
367 int nid_b = get_sig_nid(cell->getPort(ID::B));
368 int nid_c = get_sig_nid(cell->getPort(ID::C));
369 int nid_d = get_sig_nid(cell->getPort(ID::D));
370
371 int nid1 = next_nid++;
372 int nid2 = next_nid++;
373 int nid3 = next_nid++;
374 int nid4 = next_nid++;
375
376 if (cell->type == ID($_OAI4_)) {
377 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
378 btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
379 btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
380 btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
381 }
382
383 if (cell->type == ID($_AOI4_)) {
384 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
385 btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
386 btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
387 btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
388 }
389
390 SigSpec sig = sigmap(cell->getPort(ID::Y));
391 add_nid_sig(nid4, sig);
392 goto okay;
393 }
394
395 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
396 {
397 string btor_op;
398 if (cell->type == ID($lt)) btor_op = "lt";
399 if (cell->type == ID($le)) btor_op = "lte";
400 if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
401 if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
402 if (cell->type == ID($ge)) btor_op = "gte";
403 if (cell->type == ID($gt)) btor_op = "gt";
404 log_assert(!btor_op.empty());
405
406 int width = 1;
407 width = std::max(width, GetSize(cell->getPort(ID::A)));
408 width = std::max(width, GetSize(cell->getPort(ID::B)));
409
410 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
411 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
412
413 int sid = get_bv_sid(1);
414 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
415 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
416
417 int nid = next_nid++;
418 if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
419 btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
420 } else {
421 btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
422 }
423
424 SigSpec sig = sigmap(cell->getPort(ID::Y));
425
426 if (GetSize(sig) > 1) {
427 int sid = get_bv_sid(GetSize(sig));
428 int nid2 = next_nid++;
429 btorf("%d uext %d %d %d\n", nid2, sid, nid, GetSize(sig) - 1);
430 nid = nid2;
431 }
432
433 add_nid_sig(nid, sig);
434 goto okay;
435 }
436
437 if (cell->type.in(ID($not), ID($neg), ID($_NOT_)))
438 {
439 string btor_op;
440 if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
441 if (cell->type == ID($neg)) btor_op = "neg";
442 log_assert(!btor_op.empty());
443
444 int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
445
446 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
447
448 int sid = get_bv_sid(width);
449 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
450
451 int nid = next_nid++;
452 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
453
454 SigSpec sig = sigmap(cell->getPort(ID::Y));
455
456 if (GetSize(sig) < width) {
457 int sid = get_bv_sid(GetSize(sig));
458 int nid2 = next_nid++;
459 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
460 nid = nid2;
461 }
462
463 add_nid_sig(nid, sig);
464 goto okay;
465 }
466
467 if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
468 {
469 string btor_op;
470 if (cell->type == ID($logic_and)) btor_op = "and";
471 if (cell->type == ID($logic_or)) btor_op = "or";
472 if (cell->type == ID($logic_not)) btor_op = "not";
473 log_assert(!btor_op.empty());
474
475 int sid = get_bv_sid(1);
476 int nid_a = get_sig_nid(cell->getPort(ID::A));
477 int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0;
478
479 if (GetSize(cell->getPort(ID::A)) > 1) {
480 int nid_red_a = next_nid++;
481 btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
482 nid_a = nid_red_a;
483 }
484
485 if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) {
486 int nid_red_b = next_nid++;
487 btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
488 nid_b = nid_red_b;
489 }
490
491 int nid = next_nid++;
492 if (btor_op != "not")
493 btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
494 else
495 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
496
497 SigSpec sig = sigmap(cell->getPort(ID::Y));
498
499 if (GetSize(sig) > 1) {
500 int sid = get_bv_sid(GetSize(sig));
501 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
502 int nid2 = next_nid++;
503 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
504 nid = nid2;
505 }
506
507 add_nid_sig(nid, sig);
508 goto okay;
509 }
510
511 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
512 {
513 string btor_op;
514 if (cell->type == ID($reduce_and)) btor_op = "redand";
515 if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
516 if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
517 log_assert(!btor_op.empty());
518
519 int sid = get_bv_sid(1);
520 int nid_a = get_sig_nid(cell->getPort(ID::A));
521
522 int nid = next_nid++;
523
524 if (cell->type == ID($reduce_xnor)) {
525 int nid2 = next_nid++;
526 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
527 btorf("%d not %d %d\n", nid2, sid, nid);
528 nid = nid2;
529 } else {
530 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
531 }
532
533 SigSpec sig = sigmap(cell->getPort(ID::Y));
534
535 if (GetSize(sig) > 1) {
536 int sid = get_bv_sid(GetSize(sig));
537 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
538 int nid2 = next_nid++;
539 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
540 nid = nid2;
541 }
542
543 add_nid_sig(nid, sig);
544 goto okay;
545 }
546
547 if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
548 {
549 SigSpec sig_a = sigmap(cell->getPort(ID::A));
550 SigSpec sig_b = sigmap(cell->getPort(ID::B));
551 SigSpec sig_s = sigmap(cell->getPort(ID::S));
552 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
553
554 int nid_a = get_sig_nid(sig_a);
555 int nid_b = get_sig_nid(sig_b);
556 int nid_s = get_sig_nid(sig_s);
557
558 int sid = get_bv_sid(GetSize(sig_y));
559 int nid = next_nid++;
560
561 if (cell->type == ID($_NMUX_)) {
562 int tmp = nid;
563 nid = next_nid++;
564 btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
565 btorf("%d not %d %d%s\n", nid, sid, tmp, getinfo(cell).c_str());
566 } else {
567 btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell).c_str());
568 }
569
570 add_nid_sig(nid, sig_y);
571 goto okay;
572 }
573
574 if (cell->type == ID($pmux))
575 {
576 SigSpec sig_a = sigmap(cell->getPort(ID::A));
577 SigSpec sig_b = sigmap(cell->getPort(ID::B));
578 SigSpec sig_s = sigmap(cell->getPort(ID::S));
579 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
580
581 int width = GetSize(sig_a);
582 int sid = get_bv_sid(width);
583 int nid = get_sig_nid(sig_a);
584
585 for (int i = 0; i < GetSize(sig_s); i++) {
586 int nid_b = get_sig_nid(sig_b.extract(i*width, width));
587 int nid_s = get_sig_nid(sig_s.extract(i));
588 int nid2 = next_nid++;
589 if (i == GetSize(sig_s)-1)
590 btorf("%d ite %d %d %d %d%s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell).c_str());
591 else
592 btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
593 nid = nid2;
594 }
595
596 add_nid_sig(nid, sig_y);
597 goto okay;
598 }
599
600 if (cell->type.in(ID($dff), ID($ff), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
601 {
602 SigSpec sig_d = sigmap(cell->getPort(ID::D));
603 SigSpec sig_q = sigmap(cell->getPort(ID::Q));
604
605 if (!info_filename.empty() && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
606 {
607 SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C));
608 int nid = get_sig_nid(sig_c);
609 bool negedge = false;
610
611 if (cell->type == ID($_DFF_N_))
612 negedge = true;
613
614 if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
615 negedge = true;
616
617 info_clocks[nid] |= negedge ? 2 : 1;
618 }
619
620 IdString symbol;
621
622 if (sig_q.is_wire()) {
623 Wire *w = sig_q.as_wire();
624 if (w->port_id == 0) {
625 statewires.insert(w);
626 symbol = w->name;
627 }
628 }
629
630 Const initval;
631 for (int i = 0; i < GetSize(sig_q); i++)
632 if (initbits.count(sig_q[i]))
633 initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
634 else
635 initval.bits.push_back(State::Sx);
636
637 int nid_init_val = -1;
638
639 if (!initval.is_fully_undef())
640 nid_init_val = get_sig_nid(initval, -1, false, true);
641
642 int sid = get_bv_sid(GetSize(sig_q));
643 int nid = next_nid++;
644
645 if (symbol.empty() || (!print_internal_names && symbol[0] == '$'))
646 btorf("%d state %d\n", nid, sid);
647 else
648 btorf("%d state %d %s\n", nid, sid, log_id(symbol));
649
650 if (nid_init_val >= 0) {
651 int nid_init = next_nid++;
652 if (verbose)
653 btorf("; initval = %s\n", log_signal(initval));
654 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
655 }
656
657 ff_todo.push_back(make_pair(nid, cell));
658 add_nid_sig(nid, sig_q);
659 goto okay;
660 }
661
662 if (cell->type.in(ID($anyconst), ID($anyseq)))
663 {
664 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
665
666 int sid = get_bv_sid(GetSize(sig_y));
667 int nid = next_nid++;
668
669 btorf("%d state %d\n", nid, sid);
670
671 if (cell->type == ID($anyconst)) {
672 int nid2 = next_nid++;
673 btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
674 }
675
676 add_nid_sig(nid, sig_y);
677 goto okay;
678 }
679
680 if (cell->type == ID($initstate))
681 {
682 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
683
684 if (initstate_nid < 0)
685 {
686 int sid = get_bv_sid(1);
687 int one_nid = get_sig_nid(State::S1);
688 int zero_nid = get_sig_nid(State::S0);
689 initstate_nid = next_nid++;
690 btorf("%d state %d\n", initstate_nid, sid);
691 btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
692 btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
693 }
694
695 add_nid_sig(initstate_nid, sig_y);
696 goto okay;
697 }
698
699 if (cell->type == ID($mem))
700 {
701 int abits = cell->getParam(ID::ABITS).as_int();
702 int width = cell->getParam(ID::WIDTH).as_int();
703 int nwords = cell->getParam(ID::SIZE).as_int();
704 int rdports = cell->getParam(ID::RD_PORTS).as_int();
705 int wrports = cell->getParam(ID::WR_PORTS).as_int();
706
707 Const wr_clk_en = cell->getParam(ID::WR_CLK_ENABLE);
708 Const rd_clk_en = cell->getParam(ID::RD_CLK_ENABLE);
709
710 bool asyncwr = wr_clk_en.is_fully_zero();
711
712 if (!asyncwr && !wr_clk_en.is_fully_ones())
713 log_error("Memory %s.%s has mixed async/sync write ports.\n",
714 log_id(module), log_id(cell));
715
716 if (!rd_clk_en.is_fully_zero())
717 log_error("Memory %s.%s has sync read ports.\n",
718 log_id(module), log_id(cell));
719
720 SigSpec sig_rd_addr = sigmap(cell->getPort(ID::RD_ADDR));
721 SigSpec sig_rd_data = sigmap(cell->getPort(ID::RD_DATA));
722
723 SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
724 SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
725 SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
726
727 int data_sid = get_bv_sid(width);
728 int bool_sid = get_bv_sid(1);
729 int sid = get_mem_sid(abits, width);
730
731 Const initdata = cell->getParam(ID::INIT);
732 initdata.exts(nwords*width);
733 int nid_init_val = -1;
734
735 if (!initdata.is_fully_undef())
736 {
737 bool constword = true;
738 Const firstword = initdata.extract(0, width);
739
740 for (int i = 1; i < nwords; i++) {
741 Const thisword = initdata.extract(i*width, width);
742 if (thisword != firstword) {
743 constword = false;
744 break;
745 }
746 }
747
748 if (constword)
749 {
750 if (verbose)
751 btorf("; initval = %s\n", log_signal(firstword));
752 nid_init_val = get_sig_nid(firstword, -1, false, true);
753 }
754 else
755 {
756 nid_init_val = next_nid++;
757 btorf("%d state %d\n", nid_init_val, sid);
758
759 for (int i = 0; i < nwords; i++) {
760 Const thisword = initdata.extract(i*width, width);
761 if (thisword.is_fully_undef())
762 continue;
763 Const thisaddr(i, abits);
764 int nid_thisword = get_sig_nid(thisword, -1, false, true);
765 int nid_thisaddr = get_sig_nid(thisaddr, -1, false, true);
766 int last_nid_init_val = nid_init_val;
767 nid_init_val = next_nid++;
768 if (verbose)
769 btorf("; initval[%d] = %s\n", i, log_signal(thisword));
770 btorf("%d write %d %d %d %d\n", nid_init_val, sid, last_nid_init_val, nid_thisaddr, nid_thisword);
771 }
772 }
773 }
774
775
776 int nid = next_nid++;
777 int nid_head = nid;
778
779 if (cell->name[0] == '$')
780 btorf("%d state %d\n", nid, sid);
781 else
782 btorf("%d state %d %s\n", nid, sid, log_id(cell));
783
784 if (nid_init_val >= 0)
785 {
786 int nid_init = next_nid++;
787 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
788 }
789
790 if (asyncwr)
791 {
792 for (int port = 0; port < wrports; port++)
793 {
794 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
795 SigSpec wd = sig_wr_data.extract(port*width, width);
796 SigSpec we = sig_wr_en.extract(port*width, width);
797
798 int wa_nid = get_sig_nid(wa);
799 int wd_nid = get_sig_nid(wd);
800 int we_nid = get_sig_nid(we);
801
802 int nid2 = next_nid++;
803 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
804
805 int nid3 = next_nid++;
806 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
807
808 int nid4 = next_nid++;
809 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
810
811 int nid5 = next_nid++;
812 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
813
814 int nid6 = next_nid++;
815 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
816
817 int nid7 = next_nid++;
818 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
819
820 int nid8 = next_nid++;
821 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
822
823 int nid9 = next_nid++;
824 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
825
826 nid_head = nid9;
827 }
828 }
829
830 for (int port = 0; port < rdports; port++)
831 {
832 SigSpec ra = sig_rd_addr.extract(port*abits, abits);
833 SigSpec rd = sig_rd_data.extract(port*width, width);
834
835 int ra_nid = get_sig_nid(ra);
836 int rd_nid = next_nid++;
837
838 btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);
839
840 add_nid_sig(rd_nid, rd);
841 }
842
843 if (!asyncwr)
844 {
845 ff_todo.push_back(make_pair(nid, cell));
846 }
847 else
848 {
849 int nid2 = next_nid++;
850 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
851 }
852
853 goto okay;
854 }
855
856 log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
857
858 okay:
859 btorf_pop(log_id(cell));
860 cell_recursion_guard.erase(cell);
861 }
862
863 int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false, bool is_init = false)
864 {
865 int nid = -1;
866 sigmap.apply(sig);
867
868 for (auto bit : sig)
869 if (bit == State::Sx)
870 goto has_undef_bits;
871
872 if (0)
873 {
874 has_undef_bits:
875 SigSpec sig_mask_undef, sig_noundef;
876 int first_undef = -1;
877
878 for (int i = 0; i < GetSize(sig); i++)
879 if (sig[i] == State::Sx) {
880 if (first_undef < 0)
881 first_undef = i;
882 sig_mask_undef.append(State::S1);
883 sig_noundef.append(State::S0);
884 } else {
885 sig_mask_undef.append(State::S0);
886 sig_noundef.append(sig[i]);
887 }
888
889 if (to_width < 0 || first_undef < to_width)
890 {
891 int sid = get_bv_sid(GetSize(sig));
892
893 int nid_input = next_nid++;
894 if (is_init)
895 btorf("%d state %d\n", nid_input, sid);
896 else
897 btorf("%d input %d\n", nid_input, sid);
898
899 int nid_masked_input;
900 if (sig_mask_undef.is_fully_ones()) {
901 nid_masked_input = nid_input;
902 } else {
903 int nid_mask_undef = get_sig_nid(sig_mask_undef);
904 nid_masked_input = next_nid++;
905 btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
906 }
907
908 if (sig_noundef.is_fully_zero()) {
909 nid = nid_masked_input;
910 } else {
911 int nid_noundef = get_sig_nid(sig_noundef);
912 nid = next_nid++;
913 btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
914 }
915
916 goto extend_or_trim;
917 }
918
919 sig = sig_noundef;
920 }
921
922 if (sig_nid.count(sig) == 0)
923 {
924 // <nid>, <bitidx>
925 vector<pair<int, int>> nidbits;
926
927 // collect all bits
928 for (int i = 0; i < GetSize(sig); i++)
929 {
930 SigBit bit = sig[i];
931
932 if (bit_nid.count(bit) == 0)
933 {
934 if (bit.wire == nullptr)
935 {
936 Const c(bit.data);
937
938 while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
939 c.bits.push_back(sig[i+GetSize(c)].data);
940
941 if (consts.count(c) == 0) {
942 int sid = get_bv_sid(GetSize(c));
943 int nid = next_nid++;
944 btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
945 consts[c] = nid;
946 nid_width[nid] = GetSize(c);
947 }
948
949 int nid = consts.at(c);
950
951 for (int j = 0; j < GetSize(c); j++)
952 nidbits.push_back(make_pair(nid, j));
953
954 i += GetSize(c)-1;
955 continue;
956 }
957 else
958 {
959 if (bit_cell.count(bit) == 0)
960 {
961 SigSpec s = bit;
962
963 while (i+GetSize(s) < GetSize(sig) && sig[i+GetSize(s)].wire != nullptr &&
964 bit_cell.count(sig[i+GetSize(s)]) == 0)
965 s.append(sig[i+GetSize(s)]);
966
967 log_warning("No driver for signal %s.\n", log_signal(s));
968
969 int sid = get_bv_sid(GetSize(s));
970 int nid = next_nid++;
971 btorf("%d input %d\n", nid, sid);
972 nid_width[nid] = GetSize(s);
973
974 for (int j = 0; j < GetSize(s); j++)
975 nidbits.push_back(make_pair(nid, j));
976
977 i += GetSize(s)-1;
978 continue;
979 }
980 else
981 {
982 export_cell(bit_cell.at(bit));
983 log_assert(bit_nid.count(bit));
984 }
985 }
986 }
987
988 nidbits.push_back(bit_nid.at(bit));
989 }
990
991 int width = 0;
992 int nid = -1;
993
994 // group bits and emit slice-concat chain
995 for (int i = 0; i < GetSize(nidbits); i++)
996 {
997 int nid2 = nidbits[i].first;
998 int lower = nidbits[i].second;
999 int upper = lower;
1000
1001 while (i+1 < GetSize(nidbits) && nidbits[i+1].first == nidbits[i].first &&
1002 nidbits[i+1].second == nidbits[i].second+1)
1003 upper++, i++;
1004
1005 int nid3 = nid2;
1006
1007 if (lower != 0 || upper+1 != nid_width.at(nid2)) {
1008 int sid = get_bv_sid(upper-lower+1);
1009 nid3 = next_nid++;
1010 btorf("%d slice %d %d %d %d\n", nid3, sid, nid2, upper, lower);
1011 }
1012
1013 int nid4 = nid3;
1014
1015 if (nid >= 0) {
1016 int sid = get_bv_sid(width+upper-lower+1);
1017 nid4 = next_nid++;
1018 btorf("%d concat %d %d %d\n", nid4, sid, nid3, nid);
1019 }
1020
1021 width += upper-lower+1;
1022 nid = nid4;
1023 }
1024
1025 sig_nid[sig] = nid;
1026 nid_width[nid] = width;
1027 }
1028
1029 nid = sig_nid.at(sig);
1030
1031 extend_or_trim:
1032 if (to_width >= 0 && to_width != GetSize(sig))
1033 {
1034 if (to_width < GetSize(sig))
1035 {
1036 int sid = get_bv_sid(to_width);
1037 int nid2 = next_nid++;
1038 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, to_width-1);
1039 nid = nid2;
1040 }
1041 else
1042 {
1043 int sid = get_bv_sid(to_width);
1044 int nid2 = next_nid++;
1045 btorf("%d %s %d %d %d\n", nid2, is_signed ? "sext" : "uext",
1046 sid, nid, to_width - GetSize(sig));
1047 nid = nid2;
1048 }
1049 }
1050
1051 return nid;
1052 }
1053
1054 BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad, bool cover_mode, bool print_internal_names, string info_filename) :
1055 f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad), cover_mode(cover_mode), print_internal_names(print_internal_names), info_filename(info_filename)
1056 {
1057 if (!info_filename.empty())
1058 infof("name %s\n", log_id(module));
1059
1060 btorf_push("inputs");
1061
1062 for (auto wire : module->wires())
1063 {
1064 if (wire->attributes.count(ID::init)) {
1065 Const attrval = wire->attributes.at(ID::init);
1066 for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
1067 if (attrval[i] == State::S0 || attrval[i] == State::S1)
1068 initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
1069 }
1070
1071 if (!wire->port_id || !wire->port_input)
1072 continue;
1073
1074 SigSpec sig = sigmap(wire);
1075 int sid = get_bv_sid(GetSize(sig));
1076 int nid = next_nid++;
1077
1078 btorf("%d input %d%s\n", nid, sid, getinfo(wire).c_str());
1079 add_nid_sig(nid, sig);
1080 }
1081
1082 btorf_pop("inputs");
1083
1084 for (auto cell : module->cells())
1085 for (auto &conn : cell->connections())
1086 {
1087 if (!cell->output(conn.first))
1088 continue;
1089
1090 for (auto bit : sigmap(conn.second))
1091 bit_cell[bit] = cell;
1092 }
1093
1094 for (auto wire : module->wires())
1095 {
1096 if (!wire->port_id || !wire->port_output)
1097 continue;
1098
1099 btorf_push(stringf("output %s", log_id(wire)));
1100
1101 int nid = get_sig_nid(wire);
1102 btorf("%d output %d%s\n", next_nid++, nid, getinfo(wire).c_str());
1103
1104 btorf_pop(stringf("output %s", log_id(wire)));
1105 }
1106
1107 for (auto cell : module->cells())
1108 {
1109 if (cell->type == ID($assume))
1110 {
1111 btorf_push(log_id(cell));
1112
1113 int sid = get_bv_sid(1);
1114 int nid_a = get_sig_nid(cell->getPort(ID::A));
1115 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1116 int nid_not_en = next_nid++;
1117 int nid_a_or_not_en = next_nid++;
1118 int nid = next_nid++;
1119
1120 btorf("%d not %d %d\n", nid_not_en, sid, nid_en);
1121 btorf("%d or %d %d %d\n", nid_a_or_not_en, sid, nid_a, nid_not_en);
1122 btorf("%d constraint %d\n", nid, nid_a_or_not_en);
1123
1124 btorf_pop(log_id(cell));
1125 }
1126
1127 if (cell->type == ID($assert))
1128 {
1129 btorf_push(log_id(cell));
1130
1131 int sid = get_bv_sid(1);
1132 int nid_a = get_sig_nid(cell->getPort(ID::A));
1133 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1134 int nid_not_a = next_nid++;
1135 int nid_en_and_not_a = next_nid++;
1136
1137 btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
1138 btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);
1139
1140 if (single_bad && !cover_mode) {
1141 bad_properties.push_back(nid_en_and_not_a);
1142 } else {
1143 if (cover_mode) {
1144 infof("bad %d%s\n", nid_en_and_not_a, getinfo(cell, true).c_str());
1145 } else {
1146 int nid = next_nid++;
1147 btorf("%d bad %d%s\n", nid, nid_en_and_not_a, getinfo(cell, true).c_str());
1148 }
1149 }
1150
1151 btorf_pop(log_id(cell));
1152 }
1153
1154 if (cell->type == ID($cover) && cover_mode)
1155 {
1156 btorf_push(log_id(cell));
1157
1158 int sid = get_bv_sid(1);
1159 int nid_a = get_sig_nid(cell->getPort(ID::A));
1160 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1161 int nid_en_and_a = next_nid++;
1162
1163 btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a);
1164
1165 if (single_bad) {
1166 bad_properties.push_back(nid_en_and_a);
1167 } else {
1168 int nid = next_nid++;
1169 btorf("%d bad %d%s\n", nid, nid_en_and_a, getinfo(cell, true).c_str());
1170 }
1171
1172 btorf_pop(log_id(cell));
1173 }
1174 }
1175
1176 for (auto wire : module->wires())
1177 {
1178 if (wire->port_id || wire->name[0] == '$')
1179 continue;
1180
1181 btorf_push(stringf("wire %s", log_id(wire)));
1182
1183 int sid = get_bv_sid(GetSize(wire));
1184 int nid = get_sig_nid(sigmap(wire));
1185
1186 if (statewires.count(wire))
1187 continue;
1188
1189 int this_nid = next_nid++;
1190 btorf("%d uext %d %d %d%s\n", this_nid, sid, nid, 0, getinfo(wire).c_str());
1191
1192 btorf_pop(stringf("wire %s", log_id(wire)));
1193 continue;
1194 }
1195
1196 while (!ff_todo.empty())
1197 {
1198 vector<pair<int, Cell*>> todo;
1199 todo.swap(ff_todo);
1200
1201 for (auto &it : todo)
1202 {
1203 int nid = it.first;
1204 Cell *cell = it.second;
1205
1206 btorf_push(stringf("next %s", log_id(cell)));
1207
1208 if (cell->type == ID($mem))
1209 {
1210 int abits = cell->getParam(ID::ABITS).as_int();
1211 int width = cell->getParam(ID::WIDTH).as_int();
1212 int wrports = cell->getParam(ID::WR_PORTS).as_int();
1213
1214 SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
1215 SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
1216 SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
1217
1218 int data_sid = get_bv_sid(width);
1219 int bool_sid = get_bv_sid(1);
1220 int sid = get_mem_sid(abits, width);
1221 int nid_head = nid;
1222
1223 for (int port = 0; port < wrports; port++)
1224 {
1225 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
1226 SigSpec wd = sig_wr_data.extract(port*width, width);
1227 SigSpec we = sig_wr_en.extract(port*width, width);
1228
1229 int wa_nid = get_sig_nid(wa);
1230 int wd_nid = get_sig_nid(wd);
1231 int we_nid = get_sig_nid(we);
1232
1233 int nid2 = next_nid++;
1234 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
1235
1236 int nid3 = next_nid++;
1237 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
1238
1239 int nid4 = next_nid++;
1240 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
1241
1242 int nid5 = next_nid++;
1243 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
1244
1245 int nid6 = next_nid++;
1246 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
1247
1248 int nid7 = next_nid++;
1249 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
1250
1251 int nid8 = next_nid++;
1252 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
1253
1254 int nid9 = next_nid++;
1255 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
1256
1257 nid_head = nid9;
1258 }
1259
1260 int nid2 = next_nid++;
1261 btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, getinfo(cell).c_str());
1262 }
1263 else
1264 {
1265 SigSpec sig = sigmap(cell->getPort(ID::D));
1266 int nid_q = get_sig_nid(sig);
1267 int sid = get_bv_sid(GetSize(sig));
1268 btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());
1269 }
1270
1271 btorf_pop(stringf("next %s", log_id(cell)));
1272 }
1273 }
1274
1275 while (!bad_properties.empty())
1276 {
1277 vector<int> todo;
1278 bad_properties.swap(todo);
1279
1280 int sid = get_bv_sid(1);
1281 int cursor = 0;
1282
1283 while (cursor+1 < GetSize(todo))
1284 {
1285 int nid_a = todo[cursor++];
1286 int nid_b = todo[cursor++];
1287 int nid = next_nid++;
1288
1289 bad_properties.push_back(nid);
1290 btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
1291 }
1292
1293 if (!bad_properties.empty()) {
1294 if (cursor < GetSize(todo))
1295 bad_properties.push_back(todo[cursor++]);
1296 log_assert(cursor == GetSize(todo));
1297 } else {
1298 int nid = next_nid++;
1299 log_assert(cursor == 0);
1300 log_assert(GetSize(todo) == 1);
1301 btorf("%d bad %d\n", nid, todo[cursor]);
1302 }
1303 }
1304
1305 if (!info_filename.empty())
1306 {
1307 for (auto &it : info_clocks)
1308 {
1309 switch (it.second)
1310 {
1311 case 1:
1312 infof("posedge %d\n", it.first);
1313 break;
1314 case 2:
1315 infof("negedge %d\n", it.first);
1316 break;
1317 case 3:
1318 infof("event %d\n", it.first);
1319 break;
1320 default:
1321 log_abort();
1322 }
1323 }
1324
1325 std::ofstream f;
1326 f.open(info_filename.c_str(), std::ofstream::trunc);
1327 if (f.fail())
1328 log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno));
1329 for (auto &it : info_lines)
1330 f << it;
1331 f.close();
1332 }
1333 }
1334 };
1335
1336 struct BtorBackend : public Backend {
1337 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1338 void help() YS_OVERRIDE
1339 {
1340 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1341 log("\n");
1342 log(" write_btor [options] [filename]\n");
1343 log("\n");
1344 log("Write a BTOR description of the current design.\n");
1345 log("\n");
1346 log(" -v\n");
1347 log(" Add comments and indentation to BTOR output file\n");
1348 log("\n");
1349 log(" -s\n");
1350 log(" Output only a single bad property for all asserts\n");
1351 log("\n");
1352 log(" -c\n");
1353 log(" Output cover properties using 'bad' statements instead of asserts\n");
1354 log("\n");
1355 log(" -i <filename>\n");
1356 log(" Create additional info file with auxiliary information\n");
1357 log("\n");
1358 log(" -x\n");
1359 log(" Output symbols for internal netnames (starting with '$')\n");
1360 log("\n");
1361 }
1362 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1363 {
1364 bool verbose = false, single_bad = false, cover_mode = false, print_internal_names = false;
1365 string info_filename;
1366
1367 log_header(design, "Executing BTOR backend.\n");
1368
1369 size_t argidx;
1370 for (argidx = 1; argidx < args.size(); argidx++)
1371 {
1372 if (args[argidx] == "-v") {
1373 verbose = true;
1374 continue;
1375 }
1376 if (args[argidx] == "-s") {
1377 single_bad = true;
1378 continue;
1379 }
1380 if (args[argidx] == "-c") {
1381 cover_mode = true;
1382 continue;
1383 }
1384 if (args[argidx] == "-i" && argidx+1 < args.size()) {
1385 info_filename = args[++argidx];
1386 continue;
1387 }
1388 if (args[argidx] == "-x") {
1389 print_internal_names = true;
1390 continue;
1391 }
1392 break;
1393 }
1394 extra_args(f, filename, args, argidx);
1395
1396 RTLIL::Module *topmod = design->top_module();
1397
1398 if (topmod == nullptr)
1399 log_cmd_error("No top module found.\n");
1400
1401 *f << stringf("; BTOR description generated by %s for module %s.\n",
1402 yosys_version_str, log_id(topmod));
1403
1404 BtorWorker(*f, topmod, verbose, single_bad, cover_mode, print_internal_names, info_filename);
1405
1406 *f << stringf("; end of yosys output\n");
1407 }
1408 } BtorBackend;
1409
1410 PRIVATE_NAMESPACE_END