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Merge pull request #2337 from YosysHQ/mwk/clean-keep-wire
[yosys.git] / backends / btor / btor.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] Btor2 , BtorMC and Boolector 3.0
21 // Aina Niemetz, Mathias Preiner, Clifford Wolf, Armin Biere
22 // Computer Aided Verification - 30th International Conference, CAV 2018
23 // https://cs.stanford.edu/people/niemetz/publication/2018/niemetzpreinerwolfbiere-cav18/
24
25 #include "kernel/rtlil.h"
26 #include "kernel/register.h"
27 #include "kernel/sigtools.h"
28 #include "kernel/celltypes.h"
29 #include "kernel/log.h"
30 #include <string>
31
32 USING_YOSYS_NAMESPACE
33 PRIVATE_NAMESPACE_BEGIN
34
35 struct BtorWorker
36 {
37 std::ostream &f;
38 SigMap sigmap;
39 RTLIL::Module *module;
40 bool verbose;
41 bool single_bad;
42 bool cover_mode;
43 bool print_internal_names;
44
45 int next_nid = 1;
46 int initstate_nid = -1;
47
48 // <width> => <sid>
49 dict<int, int> sorts_bv;
50
51 // (<address-width>, <data-width>) => <sid>
52 dict<pair<int, int>, int> sorts_mem;
53
54 // SigBit => (<nid>, <bitidx>)
55 dict<SigBit, pair<int, int>> bit_nid;
56
57 // <nid> => <bvwidth>
58 dict<int, int> nid_width;
59
60 // SigSpec => <nid>
61 dict<SigSpec, int> sig_nid;
62
63 // bit to driving cell
64 dict<SigBit, Cell*> bit_cell;
65
66 // nids for constants
67 dict<Const, int> consts;
68
69 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
70 vector<pair<int, Cell*>> ff_todo;
71
72 pool<Cell*> cell_recursion_guard;
73 vector<int> bad_properties;
74 dict<SigBit, bool> initbits;
75 pool<Wire*> statewires;
76 pool<string> srcsymbols;
77
78 string indent, info_filename;
79 vector<string> info_lines;
80 dict<int, int> info_clocks;
81
82 void btorf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
83 {
84 va_list ap;
85 va_start(ap, fmt);
86 f << indent << vstringf(fmt, ap);
87 va_end(ap);
88 }
89
90 void infof(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
91 {
92 va_list ap;
93 va_start(ap, fmt);
94 info_lines.push_back(vstringf(fmt, ap));
95 va_end(ap);
96 }
97
98 template<typename T>
99 string getinfo(T *obj, bool srcsym = false)
100 {
101 string infostr = log_id(obj);
102 if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
103 if (obj->attributes.count(ID::src)) {
104 string src = obj->attributes.at(ID::src).decode_string().c_str();
105 if (srcsym && infostr[0] == '$') {
106 std::replace(src.begin(), src.end(), ' ', '_');
107 if (srcsymbols.count(src) || module->count_id("\\" + src)) {
108 for (int i = 1;; i++) {
109 string s = stringf("%s-%d", src.c_str(), i);
110 if (!srcsymbols.count(s) && !module->count_id("\\" + s)) {
111 src = s;
112 break;
113 }
114 }
115 }
116 srcsymbols.insert(src);
117 infostr = src;
118 } else {
119 infostr += " ; " + src;
120 }
121 }
122 return " " + infostr;
123 }
124
125 void btorf_push(const string &id)
126 {
127 if (verbose) {
128 f << indent << stringf(" ; begin %s\n", id.c_str());
129 indent += " ";
130 }
131 }
132
133 void btorf_pop(const string &id)
134 {
135 if (verbose) {
136 indent = indent.substr(4);
137 f << indent << stringf(" ; end %s\n", id.c_str());
138 }
139 }
140
141 int get_bv_sid(int width)
142 {
143 if (sorts_bv.count(width) == 0) {
144 int nid = next_nid++;
145 btorf("%d sort bitvec %d\n", nid, width);
146 sorts_bv[width] = nid;
147 }
148 return sorts_bv.at(width);
149 }
150
151 int get_mem_sid(int abits, int dbits)
152 {
153 pair<int, int> key(abits, dbits);
154 if (sorts_mem.count(key) == 0) {
155 int addr_sid = get_bv_sid(abits);
156 int data_sid = get_bv_sid(dbits);
157 int nid = next_nid++;
158 btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
159 sorts_mem[key] = nid;
160 }
161 return sorts_mem.at(key);
162 }
163
164 void add_nid_sig(int nid, const SigSpec &sig)
165 {
166 if (verbose)
167 f << indent << stringf("; %d %s\n", nid, log_signal(sig));
168
169 for (int i = 0; i < GetSize(sig); i++)
170 bit_nid[sig[i]] = make_pair(nid, i);
171
172 sig_nid[sig] = nid;
173 nid_width[nid] = GetSize(sig);
174 }
175
176 void export_cell(Cell *cell)
177 {
178 if (cell_recursion_guard.count(cell)) {
179 string cell_list;
180 for (auto c : cell_recursion_guard)
181 cell_list += stringf("\n %s", log_id(c));
182 log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
183 }
184
185 cell_recursion_guard.insert(cell);
186 btorf_push(log_id(cell));
187
188 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
189 ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
190 {
191 string btor_op;
192 if (cell->type == ID($add)) btor_op = "add";
193 if (cell->type == ID($sub)) btor_op = "sub";
194 if (cell->type == ID($mul)) btor_op = "mul";
195 if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
196 if (cell->type == ID($shr)) btor_op = "srl";
197 if (cell->type == ID($sshr)) btor_op = "sra";
198 if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
199 if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
200 if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
201 if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
202 if (cell->type == ID($concat)) btor_op = "concat";
203 if (cell->type == ID($_NAND_)) btor_op = "nand";
204 if (cell->type == ID($_NOR_)) btor_op = "nor";
205 if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
206 log_assert(!btor_op.empty());
207
208 int width_ay = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
209 int width = std::max(width_ay, GetSize(cell->getPort(ID::B)));
210
211 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
212 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
213
214 if (btor_op == "shift" && !b_signed)
215 btor_op = "srl";
216
217 if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
218 b_signed = false;
219
220 if (cell->type == ID($sshr) && !a_signed)
221 btor_op = "srl";
222
223 int sid = get_bv_sid(width);
224 int nid;
225
226 int nid_a;
227 if (cell->type.in(ID($shl), ID($shr), ID($shift), ID($shiftx)) && a_signed && width_ay < width) {
228 // sign-extend A up to the width of Y
229 int nid_a_padded = get_sig_nid(cell->getPort(ID::A), width_ay, a_signed);
230
231 // zero-extend the rest
232 int zeroes = get_sig_nid(Const(0, width-width_ay));
233 nid_a = next_nid++;
234 btorf("%d concat %d %d %d\n", nid_a, sid, zeroes, nid_a_padded);
235 } else {
236 nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
237 }
238
239 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
240
241 if (btor_op == "shift")
242 {
243 int nid_r = next_nid++;
244 btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);
245
246 int nid_b_neg = next_nid++;
247 btorf("%d neg %d %d\n", nid_b_neg, sid, nid_b);
248
249 int nid_l = next_nid++;
250 btorf("%d sll %d %d %d\n", nid_l, sid, nid_a, nid_b_neg);
251
252 int sid_bit = get_bv_sid(1);
253 int nid_zero = get_sig_nid(Const(0, width));
254 int nid_b_ltz = next_nid++;
255 btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
256
257 nid = next_nid++;
258 btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell).c_str());
259 }
260 else
261 {
262 nid = next_nid++;
263 btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
264 }
265
266 SigSpec sig = sigmap(cell->getPort(ID::Y));
267
268 if (GetSize(sig) < width) {
269 int sid = get_bv_sid(GetSize(sig));
270 int nid2 = next_nid++;
271 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
272 nid = nid2;
273 }
274
275 add_nid_sig(nid, sig);
276 goto okay;
277 }
278
279 if (cell->type.in(ID($div), ID($mod), ID($modfloor)))
280 {
281 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
282 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
283
284 string btor_op;
285 if (cell->type == ID($div)) btor_op = "div";
286 // "rem" = truncating modulo
287 if (cell->type == ID($mod)) btor_op = "rem";
288 // "mod" = flooring modulo
289 if (cell->type == ID($modfloor)) {
290 // "umod" doesn't exist because it's the same as "urem"
291 btor_op = a_signed || b_signed ? "mod" : "rem";
292 }
293 log_assert(!btor_op.empty());
294
295 int width = GetSize(cell->getPort(ID::Y));
296 width = std::max(width, GetSize(cell->getPort(ID::A)));
297 width = std::max(width, GetSize(cell->getPort(ID::B)));
298
299 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
300 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
301
302 int sid = get_bv_sid(width);
303 int nid = next_nid++;
304 btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
305
306 SigSpec sig = sigmap(cell->getPort(ID::Y));
307
308 if (GetSize(sig) < width) {
309 int sid = get_bv_sid(GetSize(sig));
310 int nid2 = next_nid++;
311 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
312 nid = nid2;
313 }
314
315 add_nid_sig(nid, sig);
316 goto okay;
317 }
318
319 if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
320 {
321 int sid = get_bv_sid(1);
322 int nid_a = get_sig_nid(cell->getPort(ID::A));
323 int nid_b = get_sig_nid(cell->getPort(ID::B));
324
325 int nid1 = next_nid++;
326 int nid2 = next_nid++;
327
328 if (cell->type == ID($_ANDNOT_)) {
329 btorf("%d not %d %d\n", nid1, sid, nid_b);
330 btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
331 }
332
333 if (cell->type == ID($_ORNOT_)) {
334 btorf("%d not %d %d\n", nid1, sid, nid_b);
335 btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
336 }
337
338 SigSpec sig = sigmap(cell->getPort(ID::Y));
339 add_nid_sig(nid2, sig);
340 goto okay;
341 }
342
343 if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
344 {
345 int sid = get_bv_sid(1);
346 int nid_a = get_sig_nid(cell->getPort(ID::A));
347 int nid_b = get_sig_nid(cell->getPort(ID::B));
348 int nid_c = get_sig_nid(cell->getPort(ID::C));
349
350 int nid1 = next_nid++;
351 int nid2 = next_nid++;
352 int nid3 = next_nid++;
353
354 if (cell->type == ID($_OAI3_)) {
355 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
356 btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
357 btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
358 }
359
360 if (cell->type == ID($_AOI3_)) {
361 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
362 btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
363 btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
364 }
365
366 SigSpec sig = sigmap(cell->getPort(ID::Y));
367 add_nid_sig(nid3, sig);
368 goto okay;
369 }
370
371 if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
372 {
373 int sid = get_bv_sid(1);
374 int nid_a = get_sig_nid(cell->getPort(ID::A));
375 int nid_b = get_sig_nid(cell->getPort(ID::B));
376 int nid_c = get_sig_nid(cell->getPort(ID::C));
377 int nid_d = get_sig_nid(cell->getPort(ID::D));
378
379 int nid1 = next_nid++;
380 int nid2 = next_nid++;
381 int nid3 = next_nid++;
382 int nid4 = next_nid++;
383
384 if (cell->type == ID($_OAI4_)) {
385 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
386 btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
387 btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
388 btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
389 }
390
391 if (cell->type == ID($_AOI4_)) {
392 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
393 btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
394 btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
395 btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
396 }
397
398 SigSpec sig = sigmap(cell->getPort(ID::Y));
399 add_nid_sig(nid4, sig);
400 goto okay;
401 }
402
403 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
404 {
405 string btor_op;
406 if (cell->type == ID($lt)) btor_op = "lt";
407 if (cell->type == ID($le)) btor_op = "lte";
408 if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
409 if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
410 if (cell->type == ID($ge)) btor_op = "gte";
411 if (cell->type == ID($gt)) btor_op = "gt";
412 log_assert(!btor_op.empty());
413
414 int width = 1;
415 width = std::max(width, GetSize(cell->getPort(ID::A)));
416 width = std::max(width, GetSize(cell->getPort(ID::B)));
417
418 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
419 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
420
421 int sid = get_bv_sid(1);
422 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
423 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
424
425 int nid = next_nid++;
426 if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
427 btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
428 } else {
429 btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
430 }
431
432 SigSpec sig = sigmap(cell->getPort(ID::Y));
433
434 if (GetSize(sig) > 1) {
435 int sid = get_bv_sid(GetSize(sig));
436 int nid2 = next_nid++;
437 btorf("%d uext %d %d %d\n", nid2, sid, nid, GetSize(sig) - 1);
438 nid = nid2;
439 }
440
441 add_nid_sig(nid, sig);
442 goto okay;
443 }
444
445 if (cell->type.in(ID($not), ID($neg), ID($_NOT_)))
446 {
447 string btor_op;
448 if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
449 if (cell->type == ID($neg)) btor_op = "neg";
450 log_assert(!btor_op.empty());
451
452 int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
453
454 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
455
456 int sid = get_bv_sid(width);
457 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
458
459 int nid = next_nid++;
460 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
461
462 SigSpec sig = sigmap(cell->getPort(ID::Y));
463
464 if (GetSize(sig) < width) {
465 int sid = get_bv_sid(GetSize(sig));
466 int nid2 = next_nid++;
467 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
468 nid = nid2;
469 }
470
471 add_nid_sig(nid, sig);
472 goto okay;
473 }
474
475 if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
476 {
477 string btor_op;
478 if (cell->type == ID($logic_and)) btor_op = "and";
479 if (cell->type == ID($logic_or)) btor_op = "or";
480 if (cell->type == ID($logic_not)) btor_op = "not";
481 log_assert(!btor_op.empty());
482
483 int sid = get_bv_sid(1);
484 int nid_a = get_sig_nid(cell->getPort(ID::A));
485 int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0;
486
487 if (GetSize(cell->getPort(ID::A)) > 1) {
488 int nid_red_a = next_nid++;
489 btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
490 nid_a = nid_red_a;
491 }
492
493 if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) {
494 int nid_red_b = next_nid++;
495 btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
496 nid_b = nid_red_b;
497 }
498
499 int nid = next_nid++;
500 if (btor_op != "not")
501 btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
502 else
503 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
504
505 SigSpec sig = sigmap(cell->getPort(ID::Y));
506
507 if (GetSize(sig) > 1) {
508 int sid = get_bv_sid(GetSize(sig));
509 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
510 int nid2 = next_nid++;
511 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
512 nid = nid2;
513 }
514
515 add_nid_sig(nid, sig);
516 goto okay;
517 }
518
519 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
520 {
521 string btor_op;
522 if (cell->type == ID($reduce_and)) btor_op = "redand";
523 if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
524 if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
525 log_assert(!btor_op.empty());
526
527 int sid = get_bv_sid(1);
528 int nid_a = get_sig_nid(cell->getPort(ID::A));
529
530 int nid = next_nid++;
531
532 if (cell->type == ID($reduce_xnor)) {
533 int nid2 = next_nid++;
534 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
535 btorf("%d not %d %d\n", nid2, sid, nid);
536 nid = nid2;
537 } else {
538 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
539 }
540
541 SigSpec sig = sigmap(cell->getPort(ID::Y));
542
543 if (GetSize(sig) > 1) {
544 int sid = get_bv_sid(GetSize(sig));
545 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
546 int nid2 = next_nid++;
547 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
548 nid = nid2;
549 }
550
551 add_nid_sig(nid, sig);
552 goto okay;
553 }
554
555 if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
556 {
557 SigSpec sig_a = sigmap(cell->getPort(ID::A));
558 SigSpec sig_b = sigmap(cell->getPort(ID::B));
559 SigSpec sig_s = sigmap(cell->getPort(ID::S));
560 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
561
562 int nid_a = get_sig_nid(sig_a);
563 int nid_b = get_sig_nid(sig_b);
564 int nid_s = get_sig_nid(sig_s);
565
566 int sid = get_bv_sid(GetSize(sig_y));
567 int nid = next_nid++;
568
569 if (cell->type == ID($_NMUX_)) {
570 int tmp = nid;
571 nid = next_nid++;
572 btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
573 btorf("%d not %d %d%s\n", nid, sid, tmp, getinfo(cell).c_str());
574 } else {
575 btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell).c_str());
576 }
577
578 add_nid_sig(nid, sig_y);
579 goto okay;
580 }
581
582 if (cell->type == ID($pmux))
583 {
584 SigSpec sig_a = sigmap(cell->getPort(ID::A));
585 SigSpec sig_b = sigmap(cell->getPort(ID::B));
586 SigSpec sig_s = sigmap(cell->getPort(ID::S));
587 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
588
589 int width = GetSize(sig_a);
590 int sid = get_bv_sid(width);
591 int nid = get_sig_nid(sig_a);
592
593 for (int i = 0; i < GetSize(sig_s); i++) {
594 int nid_b = get_sig_nid(sig_b.extract(i*width, width));
595 int nid_s = get_sig_nid(sig_s.extract(i));
596 int nid2 = next_nid++;
597 if (i == GetSize(sig_s)-1)
598 btorf("%d ite %d %d %d %d%s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell).c_str());
599 else
600 btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
601 nid = nid2;
602 }
603
604 add_nid_sig(nid, sig_y);
605 goto okay;
606 }
607
608 if (cell->type.in(ID($dff), ID($ff), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
609 {
610 SigSpec sig_d = sigmap(cell->getPort(ID::D));
611 SigSpec sig_q = sigmap(cell->getPort(ID::Q));
612
613 if (!info_filename.empty() && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
614 {
615 SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C));
616 int nid = get_sig_nid(sig_c);
617 bool negedge = false;
618
619 if (cell->type == ID($_DFF_N_))
620 negedge = true;
621
622 if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
623 negedge = true;
624
625 info_clocks[nid] |= negedge ? 2 : 1;
626 }
627
628 IdString symbol;
629
630 if (sig_q.is_wire()) {
631 Wire *w = sig_q.as_wire();
632 if (w->port_id == 0) {
633 statewires.insert(w);
634 symbol = w->name;
635 }
636 }
637
638 Const initval;
639 for (int i = 0; i < GetSize(sig_q); i++)
640 if (initbits.count(sig_q[i]))
641 initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
642 else
643 initval.bits.push_back(State::Sx);
644
645 int nid_init_val = -1;
646
647 if (!initval.is_fully_undef())
648 nid_init_val = get_sig_nid(initval, -1, false, true);
649
650 int sid = get_bv_sid(GetSize(sig_q));
651 int nid = next_nid++;
652
653 if (symbol.empty() || (!print_internal_names && symbol[0] == '$'))
654 btorf("%d state %d\n", nid, sid);
655 else
656 btorf("%d state %d %s\n", nid, sid, log_id(symbol));
657
658 if (nid_init_val >= 0) {
659 int nid_init = next_nid++;
660 if (verbose)
661 btorf("; initval = %s\n", log_signal(initval));
662 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
663 }
664
665 ff_todo.push_back(make_pair(nid, cell));
666 add_nid_sig(nid, sig_q);
667 goto okay;
668 }
669
670 if (cell->type.in(ID($anyconst), ID($anyseq)))
671 {
672 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
673
674 int sid = get_bv_sid(GetSize(sig_y));
675 int nid = next_nid++;
676
677 btorf("%d state %d\n", nid, sid);
678
679 if (cell->type == ID($anyconst)) {
680 int nid2 = next_nid++;
681 btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
682 }
683
684 add_nid_sig(nid, sig_y);
685 goto okay;
686 }
687
688 if (cell->type == ID($initstate))
689 {
690 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
691
692 if (initstate_nid < 0)
693 {
694 int sid = get_bv_sid(1);
695 int one_nid = get_sig_nid(State::S1);
696 int zero_nid = get_sig_nid(State::S0);
697 initstate_nid = next_nid++;
698 btorf("%d state %d\n", initstate_nid, sid);
699 btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
700 btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
701 }
702
703 add_nid_sig(initstate_nid, sig_y);
704 goto okay;
705 }
706
707 if (cell->type == ID($mem))
708 {
709 int abits = cell->getParam(ID::ABITS).as_int();
710 int width = cell->getParam(ID::WIDTH).as_int();
711 int nwords = cell->getParam(ID::SIZE).as_int();
712 int rdports = cell->getParam(ID::RD_PORTS).as_int();
713 int wrports = cell->getParam(ID::WR_PORTS).as_int();
714
715 Const wr_clk_en = cell->getParam(ID::WR_CLK_ENABLE);
716 Const rd_clk_en = cell->getParam(ID::RD_CLK_ENABLE);
717
718 bool asyncwr = wr_clk_en.is_fully_zero();
719
720 if (!asyncwr && !wr_clk_en.is_fully_ones())
721 log_error("Memory %s.%s has mixed async/sync write ports.\n",
722 log_id(module), log_id(cell));
723
724 if (!rd_clk_en.is_fully_zero())
725 log_error("Memory %s.%s has sync read ports.\n",
726 log_id(module), log_id(cell));
727
728 SigSpec sig_rd_addr = sigmap(cell->getPort(ID::RD_ADDR));
729 SigSpec sig_rd_data = sigmap(cell->getPort(ID::RD_DATA));
730
731 SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
732 SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
733 SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
734
735 int data_sid = get_bv_sid(width);
736 int bool_sid = get_bv_sid(1);
737 int sid = get_mem_sid(abits, width);
738
739 Const initdata = cell->getParam(ID::INIT);
740 initdata.exts(nwords*width);
741 int nid_init_val = -1;
742
743 if (!initdata.is_fully_undef())
744 {
745 bool constword = true;
746 Const firstword = initdata.extract(0, width);
747
748 for (int i = 1; i < nwords; i++) {
749 Const thisword = initdata.extract(i*width, width);
750 if (thisword != firstword) {
751 constword = false;
752 break;
753 }
754 }
755
756 if (constword)
757 {
758 if (verbose)
759 btorf("; initval = %s\n", log_signal(firstword));
760 nid_init_val = get_sig_nid(firstword, -1, false, true);
761 }
762 else
763 {
764 nid_init_val = next_nid++;
765 btorf("%d state %d\n", nid_init_val, sid);
766
767 for (int i = 0; i < nwords; i++) {
768 Const thisword = initdata.extract(i*width, width);
769 if (thisword.is_fully_undef())
770 continue;
771 Const thisaddr(i, abits);
772 int nid_thisword = get_sig_nid(thisword, -1, false, true);
773 int nid_thisaddr = get_sig_nid(thisaddr, -1, false, true);
774 int last_nid_init_val = nid_init_val;
775 nid_init_val = next_nid++;
776 if (verbose)
777 btorf("; initval[%d] = %s\n", i, log_signal(thisword));
778 btorf("%d write %d %d %d %d\n", nid_init_val, sid, last_nid_init_val, nid_thisaddr, nid_thisword);
779 }
780 }
781 }
782
783
784 int nid = next_nid++;
785 int nid_head = nid;
786
787 if (cell->name[0] == '$')
788 btorf("%d state %d\n", nid, sid);
789 else
790 btorf("%d state %d %s\n", nid, sid, log_id(cell));
791
792 if (nid_init_val >= 0)
793 {
794 int nid_init = next_nid++;
795 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
796 }
797
798 if (asyncwr)
799 {
800 for (int port = 0; port < wrports; port++)
801 {
802 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
803 SigSpec wd = sig_wr_data.extract(port*width, width);
804 SigSpec we = sig_wr_en.extract(port*width, width);
805
806 int wa_nid = get_sig_nid(wa);
807 int wd_nid = get_sig_nid(wd);
808 int we_nid = get_sig_nid(we);
809
810 int nid2 = next_nid++;
811 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
812
813 int nid3 = next_nid++;
814 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
815
816 int nid4 = next_nid++;
817 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
818
819 int nid5 = next_nid++;
820 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
821
822 int nid6 = next_nid++;
823 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
824
825 int nid7 = next_nid++;
826 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
827
828 int nid8 = next_nid++;
829 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
830
831 int nid9 = next_nid++;
832 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
833
834 nid_head = nid9;
835 }
836 }
837
838 for (int port = 0; port < rdports; port++)
839 {
840 SigSpec ra = sig_rd_addr.extract(port*abits, abits);
841 SigSpec rd = sig_rd_data.extract(port*width, width);
842
843 int ra_nid = get_sig_nid(ra);
844 int rd_nid = next_nid++;
845
846 btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);
847
848 add_nid_sig(rd_nid, rd);
849 }
850
851 if (!asyncwr)
852 {
853 ff_todo.push_back(make_pair(nid, cell));
854 }
855 else
856 {
857 int nid2 = next_nid++;
858 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
859 }
860
861 goto okay;
862 }
863
864 log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
865
866 okay:
867 btorf_pop(log_id(cell));
868 cell_recursion_guard.erase(cell);
869 }
870
871 int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false, bool is_init = false)
872 {
873 int nid = -1;
874 sigmap.apply(sig);
875
876 for (auto bit : sig)
877 if (bit == State::Sx)
878 goto has_undef_bits;
879
880 if (0)
881 {
882 has_undef_bits:
883 SigSpec sig_mask_undef, sig_noundef;
884 int first_undef = -1;
885
886 for (int i = 0; i < GetSize(sig); i++)
887 if (sig[i] == State::Sx) {
888 if (first_undef < 0)
889 first_undef = i;
890 sig_mask_undef.append(State::S1);
891 sig_noundef.append(State::S0);
892 } else {
893 sig_mask_undef.append(State::S0);
894 sig_noundef.append(sig[i]);
895 }
896
897 if (to_width < 0 || first_undef < to_width)
898 {
899 int sid = get_bv_sid(GetSize(sig));
900
901 int nid_input = next_nid++;
902 if (is_init)
903 btorf("%d state %d\n", nid_input, sid);
904 else
905 btorf("%d input %d\n", nid_input, sid);
906
907 int nid_masked_input;
908 if (sig_mask_undef.is_fully_ones()) {
909 nid_masked_input = nid_input;
910 } else {
911 int nid_mask_undef = get_sig_nid(sig_mask_undef);
912 nid_masked_input = next_nid++;
913 btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
914 }
915
916 if (sig_noundef.is_fully_zero()) {
917 nid = nid_masked_input;
918 } else {
919 int nid_noundef = get_sig_nid(sig_noundef);
920 nid = next_nid++;
921 btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
922 }
923
924 goto extend_or_trim;
925 }
926
927 sig = sig_noundef;
928 }
929
930 if (sig_nid.count(sig) == 0)
931 {
932 // <nid>, <bitidx>
933 vector<pair<int, int>> nidbits;
934
935 // collect all bits
936 for (int i = 0; i < GetSize(sig); i++)
937 {
938 SigBit bit = sig[i];
939
940 if (bit_nid.count(bit) == 0)
941 {
942 if (bit.wire == nullptr)
943 {
944 Const c(bit.data);
945
946 while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
947 c.bits.push_back(sig[i+GetSize(c)].data);
948
949 if (consts.count(c) == 0) {
950 int sid = get_bv_sid(GetSize(c));
951 int nid = next_nid++;
952 btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
953 consts[c] = nid;
954 nid_width[nid] = GetSize(c);
955 }
956
957 int nid = consts.at(c);
958
959 for (int j = 0; j < GetSize(c); j++)
960 nidbits.push_back(make_pair(nid, j));
961
962 i += GetSize(c)-1;
963 continue;
964 }
965 else
966 {
967 if (bit_cell.count(bit) == 0)
968 {
969 SigSpec s = bit;
970
971 while (i+GetSize(s) < GetSize(sig) && sig[i+GetSize(s)].wire != nullptr &&
972 bit_cell.count(sig[i+GetSize(s)]) == 0)
973 s.append(sig[i+GetSize(s)]);
974
975 log_warning("No driver for signal %s.\n", log_signal(s));
976
977 int sid = get_bv_sid(GetSize(s));
978 int nid = next_nid++;
979 btorf("%d input %d\n", nid, sid);
980 nid_width[nid] = GetSize(s);
981
982 for (int j = 0; j < GetSize(s); j++)
983 nidbits.push_back(make_pair(nid, j));
984
985 i += GetSize(s)-1;
986 continue;
987 }
988 else
989 {
990 export_cell(bit_cell.at(bit));
991 log_assert(bit_nid.count(bit));
992 }
993 }
994 }
995
996 nidbits.push_back(bit_nid.at(bit));
997 }
998
999 int width = 0;
1000 int nid = -1;
1001
1002 // group bits and emit slice-concat chain
1003 for (int i = 0; i < GetSize(nidbits); i++)
1004 {
1005 int nid2 = nidbits[i].first;
1006 int lower = nidbits[i].second;
1007 int upper = lower;
1008
1009 while (i+1 < GetSize(nidbits) && nidbits[i+1].first == nidbits[i].first &&
1010 nidbits[i+1].second == nidbits[i].second+1)
1011 upper++, i++;
1012
1013 int nid3 = nid2;
1014
1015 if (lower != 0 || upper+1 != nid_width.at(nid2)) {
1016 int sid = get_bv_sid(upper-lower+1);
1017 nid3 = next_nid++;
1018 btorf("%d slice %d %d %d %d\n", nid3, sid, nid2, upper, lower);
1019 }
1020
1021 int nid4 = nid3;
1022
1023 if (nid >= 0) {
1024 int sid = get_bv_sid(width+upper-lower+1);
1025 nid4 = next_nid++;
1026 btorf("%d concat %d %d %d\n", nid4, sid, nid3, nid);
1027 }
1028
1029 width += upper-lower+1;
1030 nid = nid4;
1031 }
1032
1033 sig_nid[sig] = nid;
1034 nid_width[nid] = width;
1035 }
1036
1037 nid = sig_nid.at(sig);
1038
1039 extend_or_trim:
1040 if (to_width >= 0 && to_width != GetSize(sig))
1041 {
1042 if (to_width < GetSize(sig))
1043 {
1044 int sid = get_bv_sid(to_width);
1045 int nid2 = next_nid++;
1046 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, to_width-1);
1047 nid = nid2;
1048 }
1049 else
1050 {
1051 int sid = get_bv_sid(to_width);
1052 int nid2 = next_nid++;
1053 btorf("%d %s %d %d %d\n", nid2, is_signed ? "sext" : "uext",
1054 sid, nid, to_width - GetSize(sig));
1055 nid = nid2;
1056 }
1057 }
1058
1059 return nid;
1060 }
1061
1062 BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad, bool cover_mode, bool print_internal_names, string info_filename) :
1063 f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad), cover_mode(cover_mode), print_internal_names(print_internal_names), info_filename(info_filename)
1064 {
1065 if (!info_filename.empty())
1066 infof("name %s\n", log_id(module));
1067
1068 btorf_push("inputs");
1069
1070 for (auto wire : module->wires())
1071 {
1072 if (wire->attributes.count(ID::init)) {
1073 Const attrval = wire->attributes.at(ID::init);
1074 for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
1075 if (attrval[i] == State::S0 || attrval[i] == State::S1)
1076 initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
1077 }
1078
1079 if (!wire->port_id || !wire->port_input)
1080 continue;
1081
1082 SigSpec sig = sigmap(wire);
1083 int sid = get_bv_sid(GetSize(sig));
1084 int nid = next_nid++;
1085
1086 btorf("%d input %d%s\n", nid, sid, getinfo(wire).c_str());
1087 add_nid_sig(nid, sig);
1088 }
1089
1090 btorf_pop("inputs");
1091
1092 for (auto cell : module->cells())
1093 for (auto &conn : cell->connections())
1094 {
1095 if (!cell->output(conn.first))
1096 continue;
1097
1098 for (auto bit : sigmap(conn.second))
1099 bit_cell[bit] = cell;
1100 }
1101
1102 for (auto wire : module->wires())
1103 {
1104 if (!wire->port_id || !wire->port_output)
1105 continue;
1106
1107 btorf_push(stringf("output %s", log_id(wire)));
1108
1109 int nid = get_sig_nid(wire);
1110 btorf("%d output %d%s\n", next_nid++, nid, getinfo(wire).c_str());
1111
1112 btorf_pop(stringf("output %s", log_id(wire)));
1113 }
1114
1115 for (auto cell : module->cells())
1116 {
1117 if (cell->type == ID($assume))
1118 {
1119 btorf_push(log_id(cell));
1120
1121 int sid = get_bv_sid(1);
1122 int nid_a = get_sig_nid(cell->getPort(ID::A));
1123 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1124 int nid_not_en = next_nid++;
1125 int nid_a_or_not_en = next_nid++;
1126 int nid = next_nid++;
1127
1128 btorf("%d not %d %d\n", nid_not_en, sid, nid_en);
1129 btorf("%d or %d %d %d\n", nid_a_or_not_en, sid, nid_a, nid_not_en);
1130 btorf("%d constraint %d\n", nid, nid_a_or_not_en);
1131
1132 btorf_pop(log_id(cell));
1133 }
1134
1135 if (cell->type == ID($assert))
1136 {
1137 btorf_push(log_id(cell));
1138
1139 int sid = get_bv_sid(1);
1140 int nid_a = get_sig_nid(cell->getPort(ID::A));
1141 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1142 int nid_not_a = next_nid++;
1143 int nid_en_and_not_a = next_nid++;
1144
1145 btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
1146 btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);
1147
1148 if (single_bad && !cover_mode) {
1149 bad_properties.push_back(nid_en_and_not_a);
1150 } else {
1151 if (cover_mode) {
1152 infof("bad %d%s\n", nid_en_and_not_a, getinfo(cell, true).c_str());
1153 } else {
1154 int nid = next_nid++;
1155 btorf("%d bad %d%s\n", nid, nid_en_and_not_a, getinfo(cell, true).c_str());
1156 }
1157 }
1158
1159 btorf_pop(log_id(cell));
1160 }
1161
1162 if (cell->type == ID($cover) && cover_mode)
1163 {
1164 btorf_push(log_id(cell));
1165
1166 int sid = get_bv_sid(1);
1167 int nid_a = get_sig_nid(cell->getPort(ID::A));
1168 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1169 int nid_en_and_a = next_nid++;
1170
1171 btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a);
1172
1173 if (single_bad) {
1174 bad_properties.push_back(nid_en_and_a);
1175 } else {
1176 int nid = next_nid++;
1177 btorf("%d bad %d%s\n", nid, nid_en_and_a, getinfo(cell, true).c_str());
1178 }
1179
1180 btorf_pop(log_id(cell));
1181 }
1182 }
1183
1184 for (auto wire : module->wires())
1185 {
1186 if (wire->port_id || wire->name[0] == '$')
1187 continue;
1188
1189 btorf_push(stringf("wire %s", log_id(wire)));
1190
1191 int sid = get_bv_sid(GetSize(wire));
1192 int nid = get_sig_nid(sigmap(wire));
1193
1194 if (statewires.count(wire))
1195 continue;
1196
1197 int this_nid = next_nid++;
1198 btorf("%d uext %d %d %d%s\n", this_nid, sid, nid, 0, getinfo(wire).c_str());
1199
1200 btorf_pop(stringf("wire %s", log_id(wire)));
1201 continue;
1202 }
1203
1204 while (!ff_todo.empty())
1205 {
1206 vector<pair<int, Cell*>> todo;
1207 todo.swap(ff_todo);
1208
1209 for (auto &it : todo)
1210 {
1211 int nid = it.first;
1212 Cell *cell = it.second;
1213
1214 btorf_push(stringf("next %s", log_id(cell)));
1215
1216 if (cell->type == ID($mem))
1217 {
1218 int abits = cell->getParam(ID::ABITS).as_int();
1219 int width = cell->getParam(ID::WIDTH).as_int();
1220 int wrports = cell->getParam(ID::WR_PORTS).as_int();
1221
1222 SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
1223 SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
1224 SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
1225
1226 int data_sid = get_bv_sid(width);
1227 int bool_sid = get_bv_sid(1);
1228 int sid = get_mem_sid(abits, width);
1229 int nid_head = nid;
1230
1231 for (int port = 0; port < wrports; port++)
1232 {
1233 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
1234 SigSpec wd = sig_wr_data.extract(port*width, width);
1235 SigSpec we = sig_wr_en.extract(port*width, width);
1236
1237 int wa_nid = get_sig_nid(wa);
1238 int wd_nid = get_sig_nid(wd);
1239 int we_nid = get_sig_nid(we);
1240
1241 int nid2 = next_nid++;
1242 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
1243
1244 int nid3 = next_nid++;
1245 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
1246
1247 int nid4 = next_nid++;
1248 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
1249
1250 int nid5 = next_nid++;
1251 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
1252
1253 int nid6 = next_nid++;
1254 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
1255
1256 int nid7 = next_nid++;
1257 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
1258
1259 int nid8 = next_nid++;
1260 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
1261
1262 int nid9 = next_nid++;
1263 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
1264
1265 nid_head = nid9;
1266 }
1267
1268 int nid2 = next_nid++;
1269 btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, getinfo(cell).c_str());
1270 }
1271 else
1272 {
1273 SigSpec sig = sigmap(cell->getPort(ID::D));
1274 int nid_q = get_sig_nid(sig);
1275 int sid = get_bv_sid(GetSize(sig));
1276 btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());
1277 }
1278
1279 btorf_pop(stringf("next %s", log_id(cell)));
1280 }
1281 }
1282
1283 while (!bad_properties.empty())
1284 {
1285 vector<int> todo;
1286 bad_properties.swap(todo);
1287
1288 int sid = get_bv_sid(1);
1289 int cursor = 0;
1290
1291 while (cursor+1 < GetSize(todo))
1292 {
1293 int nid_a = todo[cursor++];
1294 int nid_b = todo[cursor++];
1295 int nid = next_nid++;
1296
1297 bad_properties.push_back(nid);
1298 btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
1299 }
1300
1301 if (!bad_properties.empty()) {
1302 if (cursor < GetSize(todo))
1303 bad_properties.push_back(todo[cursor++]);
1304 log_assert(cursor == GetSize(todo));
1305 } else {
1306 int nid = next_nid++;
1307 log_assert(cursor == 0);
1308 log_assert(GetSize(todo) == 1);
1309 btorf("%d bad %d\n", nid, todo[cursor]);
1310 }
1311 }
1312
1313 if (!info_filename.empty())
1314 {
1315 for (auto &it : info_clocks)
1316 {
1317 switch (it.second)
1318 {
1319 case 1:
1320 infof("posedge %d\n", it.first);
1321 break;
1322 case 2:
1323 infof("negedge %d\n", it.first);
1324 break;
1325 case 3:
1326 infof("event %d\n", it.first);
1327 break;
1328 default:
1329 log_abort();
1330 }
1331 }
1332
1333 std::ofstream f;
1334 f.open(info_filename.c_str(), std::ofstream::trunc);
1335 if (f.fail())
1336 log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno));
1337 for (auto &it : info_lines)
1338 f << it;
1339 f.close();
1340 }
1341 }
1342 };
1343
1344 struct BtorBackend : public Backend {
1345 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1346 void help() override
1347 {
1348 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1349 log("\n");
1350 log(" write_btor [options] [filename]\n");
1351 log("\n");
1352 log("Write a BTOR description of the current design.\n");
1353 log("\n");
1354 log(" -v\n");
1355 log(" Add comments and indentation to BTOR output file\n");
1356 log("\n");
1357 log(" -s\n");
1358 log(" Output only a single bad property for all asserts\n");
1359 log("\n");
1360 log(" -c\n");
1361 log(" Output cover properties using 'bad' statements instead of asserts\n");
1362 log("\n");
1363 log(" -i <filename>\n");
1364 log(" Create additional info file with auxiliary information\n");
1365 log("\n");
1366 log(" -x\n");
1367 log(" Output symbols for internal netnames (starting with '$')\n");
1368 log("\n");
1369 }
1370 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
1371 {
1372 bool verbose = false, single_bad = false, cover_mode = false, print_internal_names = false;
1373 string info_filename;
1374
1375 log_header(design, "Executing BTOR backend.\n");
1376
1377 size_t argidx;
1378 for (argidx = 1; argidx < args.size(); argidx++)
1379 {
1380 if (args[argidx] == "-v") {
1381 verbose = true;
1382 continue;
1383 }
1384 if (args[argidx] == "-s") {
1385 single_bad = true;
1386 continue;
1387 }
1388 if (args[argidx] == "-c") {
1389 cover_mode = true;
1390 continue;
1391 }
1392 if (args[argidx] == "-i" && argidx+1 < args.size()) {
1393 info_filename = args[++argidx];
1394 continue;
1395 }
1396 if (args[argidx] == "-x") {
1397 print_internal_names = true;
1398 continue;
1399 }
1400 break;
1401 }
1402 extra_args(f, filename, args, argidx);
1403
1404 RTLIL::Module *topmod = design->top_module();
1405
1406 if (topmod == nullptr)
1407 log_cmd_error("No top module found.\n");
1408
1409 *f << stringf("; BTOR description generated by %s for module %s.\n",
1410 yosys_version_str, log_id(topmod));
1411
1412 BtorWorker(*f, topmod, verbose, single_bad, cover_mode, print_internal_names, info_filename);
1413
1414 *f << stringf("; end of yosys output\n");
1415 }
1416 } BtorBackend;
1417
1418 PRIVATE_NAMESPACE_END