2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
28 PRIVATE_NAMESPACE_BEGIN
34 RTLIL::Module
*module
;
39 int initstate_nid
= -1;
42 dict
<int, int> sorts_bv
;
44 // (<address-width>, <data-width>) => <sid>
45 dict
<pair
<int, int>, int> sorts_mem
;
47 // SigBit => (<nid>, <bitidx>)
48 dict
<SigBit
, pair
<int, int>> bit_nid
;
51 dict
<int, int> nid_width
;
54 dict
<SigSpec
, int> sig_nid
;
56 // bit to driving cell
57 dict
<SigBit
, Cell
*> bit_cell
;
60 dict
<Const
, int> consts
;
62 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
63 vector
<pair
<int, Cell
*>> ff_todo
;
65 pool
<Cell
*> cell_recursion_guard
;
66 vector
<int> bad_properties
;
67 dict
<SigBit
, bool> initbits
;
68 pool
<Wire
*> statewires
;
71 void btorf(const char *fmt
, ...)
75 f
<< indent
<< vstringf(fmt
, ap
);
79 void btorf_push(const string
&id
)
82 f
<< indent
<< stringf(" ; begin %s\n", id
.c_str());
87 void btorf_pop(const string
&id
)
90 indent
= indent
.substr(4);
91 f
<< indent
<< stringf(" ; end %s\n", id
.c_str());
95 int get_bv_sid(int width
)
97 if (sorts_bv
.count(width
) == 0) {
99 btorf("%d sort bitvec %d\n", nid
, width
);
100 sorts_bv
[width
] = nid
;
102 return sorts_bv
.at(width
);
105 int get_mem_sid(int abits
, int dbits
)
107 pair
<int, int> key(abits
, dbits
);
108 if (sorts_mem
.count(key
) == 0) {
109 int addr_sid
= get_bv_sid(abits
);
110 int data_sid
= get_bv_sid(dbits
);
111 int nid
= next_nid
++;
112 btorf("%d sort array %d %d\n", nid
, addr_sid
, data_sid
);
113 sorts_mem
[key
] = nid
;
115 return sorts_mem
.at(key
);
118 void add_nid_sig(int nid
, const SigSpec
&sig
)
121 f
<< indent
<< stringf("; %d %s\n", nid
, log_signal(sig
));
123 for (int i
= 0; i
< GetSize(sig
); i
++)
124 bit_nid
[sig
[i
]] = make_pair(nid
, i
);
127 nid_width
[nid
] = GetSize(sig
);
130 void export_cell(Cell
*cell
)
132 log_assert(cell_recursion_guard
.count(cell
) == 0);
133 cell_recursion_guard
.insert(cell
);
134 btorf_push(log_id(cell
));
136 if (cell
->type
.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
137 "$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
140 if (cell
->type
== "$add") btor_op
= "add";
141 if (cell
->type
== "$sub") btor_op
= "sub";
142 if (cell
->type
== "$mul") btor_op
= "mul";
143 if (cell
->type
.in("$shl", "$sshl")) btor_op
= "sll";
144 if (cell
->type
== "$shr") btor_op
= "srl";
145 if (cell
->type
== "$sshr") btor_op
= "sra";
146 if (cell
->type
.in("$shift", "$shiftx")) btor_op
= "shift";
147 if (cell
->type
.in("$and", "$_AND_")) btor_op
= "and";
148 if (cell
->type
.in("$or", "$_OR_")) btor_op
= "or";
149 if (cell
->type
.in("$xor", "$_XOR_")) btor_op
= "xor";
150 if (cell
->type
== "$concat") btor_op
= "concat";
151 if (cell
->type
== "$_NAND_") btor_op
= "nand";
152 if (cell
->type
== "$_NOR_") btor_op
= "nor";
153 if (cell
->type
.in("$xnor", "$_XNOR_")) btor_op
= "xnor";
154 log_assert(!btor_op
.empty());
156 int width
= GetSize(cell
->getPort("\\Y"));
157 width
= std::max(width
, GetSize(cell
->getPort("\\A")));
158 width
= std::max(width
, GetSize(cell
->getPort("\\B")));
160 bool a_signed
= cell
->hasParam("\\A_SIGNED") ? cell
->getParam("\\A_SIGNED").as_bool() : false;
161 bool b_signed
= cell
->hasParam("\\B_SIGNED") ? cell
->getParam("\\B_SIGNED").as_bool() : false;
163 if (btor_op
== "shift" && !b_signed
)
166 if (cell
->type
.in("$shl", "$sshl", "$shr", "$sshr"))
169 if (cell
->type
== "$sshr" && !a_signed
)
172 int sid
= get_bv_sid(width
);
175 if (btor_op
== "shift")
177 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, false);
178 int nid_b
= get_sig_nid(cell
->getPort("\\B"), width
, b_signed
);
180 int nid_r
= next_nid
++;
181 btorf("%d srl %d %d %d\n", nid_r
, sid
, nid_a
, nid_b
);
183 int nid_b_neg
= next_nid
++;
184 btorf("%d neg %d %d\n", nid_b_neg
, sid
, nid_b
);
186 int nid_l
= next_nid
++;
187 btorf("%d sll %d %d %d\n", nid_l
, sid
, nid_a
, nid_b_neg
);
189 int sid_bit
= get_bv_sid(1);
190 int nid_zero
= get_sig_nid(Const(0, width
));
191 int nid_b_ltz
= next_nid
++;
192 btorf("%d slt %d %d %d\n", nid_b_ltz
, sid_bit
, nid_b
, nid_zero
);
195 btorf("%d ite %d %d %d %d\n", nid
, sid
, nid_b_ltz
, nid_l
, nid_r
);
199 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, a_signed
);
200 int nid_b
= get_sig_nid(cell
->getPort("\\B"), width
, b_signed
);
203 btorf("%d %s %d %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
, nid_b
);
206 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
208 if (GetSize(sig
) < width
) {
209 int sid
= get_bv_sid(GetSize(sig
));
210 int nid2
= next_nid
++;
211 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, GetSize(sig
)-1);
215 add_nid_sig(nid
, sig
);
219 if (cell
->type
.in("$div", "$mod"))
222 if (cell
->type
== "$div") btor_op
= "div";
223 if (cell
->type
== "$mod") btor_op
= "rem";
224 log_assert(!btor_op
.empty());
226 int width
= GetSize(cell
->getPort("\\Y"));
227 width
= std::max(width
, GetSize(cell
->getPort("\\A")));
228 width
= std::max(width
, GetSize(cell
->getPort("\\B")));
230 bool a_signed
= cell
->hasParam("\\A_SIGNED") ? cell
->getParam("\\A_SIGNED").as_bool() : false;
231 bool b_signed
= cell
->hasParam("\\B_SIGNED") ? cell
->getParam("\\B_SIGNED").as_bool() : false;
233 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, a_signed
);
234 int nid_b
= get_sig_nid(cell
->getPort("\\B"), width
, b_signed
);
236 int sid
= get_bv_sid(width
);
237 int nid
= next_nid
++;
238 btorf("%d %c%s %d %d %d\n", nid
, a_signed
|| b_signed
? 's' : 'u', btor_op
.c_str(), sid
, nid_a
, nid_b
);
240 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
242 if (GetSize(sig
) < width
) {
243 int sid
= get_bv_sid(GetSize(sig
));
244 int nid2
= next_nid
++;
245 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, GetSize(sig
)-1);
249 add_nid_sig(nid
, sig
);
253 if (cell
->type
.in("$_ANDNOT_", "$_ORNOT_"))
255 int sid
= get_bv_sid(1);
256 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
257 int nid_b
= get_sig_nid(cell
->getPort("\\B"));
259 int nid1
= next_nid
++;
260 int nid2
= next_nid
++;
262 if (cell
->type
== "$_ANDNOT_") {
263 btorf("%d not %d %d\n", nid1
, sid
, nid_b
);
264 btorf("%d and %d %d %d\n", nid2
, sid
, nid_a
, nid1
);
267 if (cell
->type
== "$_ORNOT_") {
268 btorf("%d not %d %d\n", nid1
, sid
, nid_b
);
269 btorf("%d or %d %d %d\n", nid2
, sid
, nid_a
, nid1
);
272 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
273 add_nid_sig(nid2
, sig
);
277 if (cell
->type
.in("$_OAI3_", "$_AOI3_"))
279 int sid
= get_bv_sid(1);
280 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
281 int nid_b
= get_sig_nid(cell
->getPort("\\B"));
282 int nid_c
= get_sig_nid(cell
->getPort("\\C"));
284 int nid1
= next_nid
++;
285 int nid2
= next_nid
++;
286 int nid3
= next_nid
++;
288 if (cell
->type
== "$_OAI3_") {
289 btorf("%d or %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
290 btorf("%d and %d %d %d\n", nid2
, sid
, nid1
, nid_c
);
291 btorf("%d not %d %d\n", nid3
, sid
, nid2
);
294 if (cell
->type
== "$_AOI3_") {
295 btorf("%d and %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
296 btorf("%d or %d %d %d\n", nid2
, sid
, nid1
, nid_c
);
297 btorf("%d not %d %d\n", nid3
, sid
, nid2
);
300 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
301 add_nid_sig(nid3
, sig
);
305 if (cell
->type
.in("$_OAI4_", "$_AOI4_"))
307 int sid
= get_bv_sid(1);
308 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
309 int nid_b
= get_sig_nid(cell
->getPort("\\B"));
310 int nid_c
= get_sig_nid(cell
->getPort("\\C"));
311 int nid_d
= get_sig_nid(cell
->getPort("\\D"));
313 int nid1
= next_nid
++;
314 int nid2
= next_nid
++;
315 int nid3
= next_nid
++;
316 int nid4
= next_nid
++;
318 if (cell
->type
== "$_OAI4_") {
319 btorf("%d or %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
320 btorf("%d or %d %d %d\n", nid2
, sid
, nid_c
, nid_d
);
321 btorf("%d and %d %d %d\n", nid3
, sid
, nid1
, nid2
);
322 btorf("%d not %d %d\n", nid4
, sid
, nid3
);
325 if (cell
->type
== "$_AOI4_") {
326 btorf("%d and %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
327 btorf("%d and %d %d %d\n", nid2
, sid
, nid_c
, nid_d
);
328 btorf("%d or %d %d %d\n", nid3
, sid
, nid1
, nid2
);
329 btorf("%d not %d %d\n", nid4
, sid
, nid3
);
332 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
333 add_nid_sig(nid4
, sig
);
337 if (cell
->type
.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt"))
340 if (cell
->type
== "$lt") btor_op
= "lt";
341 if (cell
->type
== "$le") btor_op
= "lte";
342 if (cell
->type
.in("$eq", "$eqx")) btor_op
= "eq";
343 if (cell
->type
.in("$ne", "$nex")) btor_op
= "ne";
344 if (cell
->type
== "$ge") btor_op
= "gte";
345 if (cell
->type
== "$gt") btor_op
= "gt";
346 log_assert(!btor_op
.empty());
349 width
= std::max(width
, GetSize(cell
->getPort("\\A")));
350 width
= std::max(width
, GetSize(cell
->getPort("\\B")));
352 bool a_signed
= cell
->hasParam("\\A_SIGNED") ? cell
->getParam("\\A_SIGNED").as_bool() : false;
353 bool b_signed
= cell
->hasParam("\\B_SIGNED") ? cell
->getParam("\\B_SIGNED").as_bool() : false;
355 int sid
= get_bv_sid(1);
356 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, a_signed
);
357 int nid_b
= get_sig_nid(cell
->getPort("\\B"), width
, b_signed
);
359 int nid
= next_nid
++;
360 if (cell
->type
.in("$lt", "$le", "$ge", "$gt")) {
361 btorf("%d %c%s %d %d %d\n", nid
, a_signed
|| b_signed
? 's' : 'u', btor_op
.c_str(), sid
, nid_a
, nid_b
);
363 btorf("%d %s %d %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
, nid_b
);
366 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
368 if (GetSize(sig
) > 1) {
369 int sid
= get_bv_sid(GetSize(sig
));
370 int nid2
= next_nid
++;
371 btorf("%d uext %d %d %d\n", nid2
, sid
, nid
, GetSize(sig
) - 1);
375 add_nid_sig(nid
, sig
);
379 if (cell
->type
.in("$not", "$neg", "$_NOT_"))
382 if (cell
->type
.in("$not", "$_NOT_")) btor_op
= "not";
383 if (cell
->type
== "$neg") btor_op
= "neg";
384 log_assert(!btor_op
.empty());
386 int width
= GetSize(cell
->getPort("\\Y"));
387 width
= std::max(width
, GetSize(cell
->getPort("\\A")));
389 bool a_signed
= cell
->hasParam("\\A_SIGNED") ? cell
->getParam("\\A_SIGNED").as_bool() : false;
391 int sid
= get_bv_sid(width
);
392 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, a_signed
);
394 int nid
= next_nid
++;
395 btorf("%d %s %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
);
397 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
399 if (GetSize(sig
) < width
) {
400 int sid
= get_bv_sid(GetSize(sig
));
401 int nid2
= next_nid
++;
402 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, GetSize(sig
)-1);
406 add_nid_sig(nid
, sig
);
410 if (cell
->type
.in("$logic_and", "$logic_or", "$logic_not"))
413 if (cell
->type
== "$logic_and") btor_op
= "and";
414 if (cell
->type
== "$logic_or") btor_op
= "or";
415 if (cell
->type
== "$logic_not") btor_op
= "not";
416 log_assert(!btor_op
.empty());
418 int sid
= get_bv_sid(1);
419 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
420 int nid_b
= btor_op
!= "not" ? get_sig_nid(cell
->getPort("\\B")) : 0;
422 if (GetSize(cell
->getPort("\\A")) > 1) {
423 int nid_red_a
= next_nid
++;
424 btorf("%d redor %d %d\n", nid_red_a
, sid
, nid_a
);
428 if (btor_op
!= "not" && GetSize(cell
->getPort("\\B")) > 1) {
429 int nid_red_b
= next_nid
++;
430 btorf("%d redor %d %d\n", nid_red_b
, sid
, nid_b
);
434 int nid
= next_nid
++;
435 if (btor_op
!= "not")
436 btorf("%d %s %d %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
, nid_b
);
438 btorf("%d %s %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
);
440 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
442 if (GetSize(sig
) > 1) {
443 int sid
= get_bv_sid(GetSize(sig
));
444 int zeros_nid
= get_sig_nid(Const(0, GetSize(sig
)-1));
445 int nid2
= next_nid
++;
446 btorf("%d concat %d %d %d\n", nid2
, sid
, zeros_nid
, nid
);
450 add_nid_sig(nid
, sig
);
454 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor"))
457 if (cell
->type
== "$reduce_and") btor_op
= "redand";
458 if (cell
->type
.in("$reduce_or", "$reduce_bool")) btor_op
= "redor";
459 if (cell
->type
.in("$reduce_xor", "$reduce_xnor")) btor_op
= "redxor";
460 log_assert(!btor_op
.empty());
462 int sid
= get_bv_sid(1);
463 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
465 int nid
= next_nid
++;
466 btorf("%d %s %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
);
468 if (cell
->type
== "$reduce_xnor") {
469 int nid2
= next_nid
++;
470 btorf("%d not %d %d %d\n", nid2
, sid
, nid
);
474 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
476 if (GetSize(sig
) > 1) {
477 int sid
= get_bv_sid(GetSize(sig
));
478 int zeros_nid
= get_sig_nid(Const(0, GetSize(sig
)-1));
479 int nid2
= next_nid
++;
480 btorf("%d concat %d %d %d\n", nid2
, sid
, zeros_nid
, nid
);
484 add_nid_sig(nid
, sig
);
488 if (cell
->type
.in("$mux", "$_MUX_"))
490 SigSpec sig_a
= sigmap(cell
->getPort("\\A"));
491 SigSpec sig_b
= sigmap(cell
->getPort("\\B"));
492 SigSpec sig_s
= sigmap(cell
->getPort("\\S"));
493 SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
495 int nid_a
= get_sig_nid(sig_a
);
496 int nid_b
= get_sig_nid(sig_b
);
497 int nid_s
= get_sig_nid(sig_s
);
499 int sid
= get_bv_sid(GetSize(sig_y
));
500 int nid
= next_nid
++;
501 btorf("%d ite %d %d %d %d\n", nid
, sid
, nid_s
, nid_b
, nid_a
);
503 add_nid_sig(nid
, sig_y
);
507 if (cell
->type
== "$pmux")
509 SigSpec sig_a
= sigmap(cell
->getPort("\\A"));
510 SigSpec sig_b
= sigmap(cell
->getPort("\\B"));
511 SigSpec sig_s
= sigmap(cell
->getPort("\\S"));
512 SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
514 int width
= GetSize(sig_a
);
515 int sid
= get_bv_sid(width
);
516 int nid
= get_sig_nid(sig_a
);
518 for (int i
= 0; i
< GetSize(sig_s
); i
++) {
519 int nid_b
= get_sig_nid(sig_b
.extract(i
*width
, width
));
520 int nid_s
= get_sig_nid(sig_s
.extract(i
));
521 int nid2
= next_nid
++;
522 btorf("%d ite %d %d %d %d\n", nid2
, sid
, nid_s
, nid_b
, nid
);
526 add_nid_sig(nid
, sig_y
);
530 if (cell
->type
.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N", "$_FF_"))
532 SigSpec sig_d
= sigmap(cell
->getPort("\\D"));
533 SigSpec sig_q
= sigmap(cell
->getPort("\\Q"));
537 if (sig_q
.is_wire()) {
538 Wire
*w
= sig_q
.as_wire();
539 if (w
->port_id
== 0) {
540 statewires
.insert(w
);
546 for (int i
= 0; i
< GetSize(sig_q
); i
++)
547 if (initbits
.count(sig_q
[i
]))
548 initval
.bits
.push_back(initbits
.at(sig_q
[i
]) ? State::S1
: State::S0
);
550 initval
.bits
.push_back(State::Sx
);
552 int nid_init_val
= -1;
554 if (!initval
.is_fully_undef())
555 nid_init_val
= get_sig_nid(initval
);
557 int sid
= get_bv_sid(GetSize(sig_q
));
558 int nid
= next_nid
++;
561 btorf("%d state %d\n", nid
, sid
);
563 btorf("%d state %d %s\n", nid
, sid
, log_id(symbol
));
565 if (nid_init_val
>= 0) {
566 int nid_init
= next_nid
++;
568 btorf("; initval = %s\n", log_signal(initval
));
569 btorf("%d init %d %d %d\n", nid_init
, sid
, nid
, nid_init_val
);
572 ff_todo
.push_back(make_pair(nid
, cell
));
573 add_nid_sig(nid
, sig_q
);
577 if (cell
->type
.in("$anyconst", "$anyseq"))
579 SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
581 int sid
= get_bv_sid(GetSize(sig_y
));
582 int nid
= next_nid
++;
584 btorf("%d state %d\n", nid
, sid
);
586 if (cell
->type
== "$anyconst") {
587 int nid2
= next_nid
++;
588 btorf("%d next %d %d %d\n", nid2
, sid
, nid
, nid
);
591 add_nid_sig(nid
, sig_y
);
595 if (cell
->type
== "$initstate")
597 SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
599 if (initstate_nid
< 0)
601 int sid
= get_bv_sid(1);
602 int one_nid
= get_sig_nid(Const(1, 1));
603 int zero_nid
= get_sig_nid(Const(0, 1));
604 initstate_nid
= next_nid
++;
605 btorf("%d state %d\n", initstate_nid
, sid
);
606 btorf("%d init %d %d %d\n", next_nid
++, sid
, initstate_nid
, one_nid
);
607 btorf("%d next %d %d %d\n", next_nid
++, sid
, initstate_nid
, zero_nid
);
610 add_nid_sig(initstate_nid
, sig_y
);
614 if (cell
->type
== "$mem")
616 int abits
= cell
->getParam("\\ABITS").as_int();
617 int width
= cell
->getParam("\\WIDTH").as_int();
618 int rdports
= cell
->getParam("\\RD_PORTS").as_int();
619 int wrports
= cell
->getParam("\\WR_PORTS").as_int();
621 Const wr_clk_en
= cell
->getParam("\\WR_CLK_ENABLE");
622 Const rd_clk_en
= cell
->getParam("\\RD_CLK_ENABLE");
624 bool asyncwr
= wr_clk_en
.is_fully_zero();
626 if (!asyncwr
&& !wr_clk_en
.is_fully_ones())
627 log_error("Memory %s.%s has mixed async/sync write ports.\n",
628 log_id(module
), log_id(cell
));
630 if (!rd_clk_en
.is_fully_zero())
631 log_error("Memory %s.%s has sync read ports.\n",
632 log_id(module
), log_id(cell
));
634 SigSpec sig_rd_addr
= sigmap(cell
->getPort("\\RD_ADDR"));
635 SigSpec sig_rd_data
= sigmap(cell
->getPort("\\RD_DATA"));
637 SigSpec sig_wr_addr
= sigmap(cell
->getPort("\\WR_ADDR"));
638 SigSpec sig_wr_data
= sigmap(cell
->getPort("\\WR_DATA"));
639 SigSpec sig_wr_en
= sigmap(cell
->getPort("\\WR_EN"));
641 int data_sid
= get_bv_sid(width
);
642 int bool_sid
= get_bv_sid(1);
643 int sid
= get_mem_sid(abits
, width
);
644 int nid
= next_nid
++;
647 if (cell
->name
[0] == '$')
648 btorf("%d state %d\n", nid
, sid
);
650 btorf("%d state %d %s\n", nid
, sid
, log_id(cell
));
654 for (int port
= 0; port
< wrports
; port
++)
656 SigSpec wa
= sig_wr_addr
.extract(port
*abits
, abits
);
657 SigSpec wd
= sig_wr_data
.extract(port
*width
, width
);
658 SigSpec we
= sig_wr_en
.extract(port
*width
, width
);
660 int wa_nid
= get_sig_nid(wa
);
661 int wd_nid
= get_sig_nid(wd
);
662 int we_nid
= get_sig_nid(we
);
664 int nid2
= next_nid
++;
665 btorf("%d read %d %d %d\n", nid2
, data_sid
, nid_head
, wa_nid
);
667 int nid3
= next_nid
++;
668 btorf("%d not %d %d\n", nid3
, data_sid
, we_nid
);
670 int nid4
= next_nid
++;
671 btorf("%d and %d %d %d\n", nid4
, data_sid
, nid2
, nid3
);
673 int nid5
= next_nid
++;
674 btorf("%d and %d %d %d\n", nid5
, data_sid
, wd_nid
, we_nid
);
676 int nid6
= next_nid
++;
677 btorf("%d or %d %d %d\n", nid6
, data_sid
, nid5
, nid4
);
679 int nid7
= next_nid
++;
680 btorf("%d write %d %d %d %d\n", nid7
, sid
, nid_head
, wa_nid
, nid6
);
682 int nid8
= next_nid
++;
683 btorf("%d redor %d %d\n", nid8
, bool_sid
, we_nid
);
685 int nid9
= next_nid
++;
686 btorf("%d ite %d %d %d %d\n", nid9
, sid
, nid8
, nid7
, nid_head
);
692 for (int port
= 0; port
< rdports
; port
++)
694 SigSpec ra
= sig_rd_addr
.extract(port
*abits
, abits
);
695 SigSpec rd
= sig_rd_data
.extract(port
*width
, width
);
697 int ra_nid
= get_sig_nid(ra
);
698 int rd_nid
= next_nid
++;
700 btorf("%d read %d %d %d\n", rd_nid
, data_sid
, nid_head
, ra_nid
);
702 add_nid_sig(rd_nid
, rd
);
707 ff_todo
.push_back(make_pair(nid
, cell
));
711 int nid2
= next_nid
++;
712 btorf("%d next %d %d %d\n", nid2
, sid
, nid
, nid_head
);
718 log_error("Unsupported cell type: %s (%s)\n", log_id(cell
->type
), log_id(cell
));
721 btorf_pop(log_id(cell
));
722 cell_recursion_guard
.erase(cell
);
725 int get_sig_nid(SigSpec sig
, int to_width
= -1, bool is_signed
= false)
731 if (bit
== State::Sx
)
737 SigSpec sig_mask_undef
, sig_noundef
;
738 int first_undef
= -1;
740 for (int i
= 0; i
< GetSize(sig
); i
++)
741 if (sig
[i
] == State::Sx
) {
744 sig_mask_undef
.append(State::S1
);
745 sig_noundef
.append(State::S0
);
747 sig_mask_undef
.append(State::S0
);
748 sig_noundef
.append(sig
[i
]);
751 if (to_width
< 0 || first_undef
< to_width
)
753 int sid
= get_bv_sid(GetSize(sig
));
755 int nid_input
= next_nid
++;
756 btorf("%d input %d\n", nid_input
, sid
);
758 int nid_masked_input
;
759 if (sig_mask_undef
.is_fully_ones()) {
760 nid_masked_input
= nid_input
;
762 int nid_mask_undef
= get_sig_nid(sig_mask_undef
);
763 nid_masked_input
= next_nid
++;
764 btorf("%d and %d %d %d\n", nid_masked_input
, sid
, nid_input
, nid_mask_undef
);
767 if (sig_noundef
.is_fully_zero()) {
768 nid
= nid_masked_input
;
770 int nid_noundef
= get_sig_nid(sig_noundef
);
772 btorf("%d or %d %d %d\n", nid
, sid
, nid_masked_input
, nid_noundef
);
781 if (sig_nid
.count(sig
) == 0)
784 vector
<pair
<int, int>> nidbits
;
787 for (int i
= 0; i
< GetSize(sig
); i
++)
791 if (bit_nid
.count(bit
) == 0)
793 if (bit
.wire
== nullptr)
797 while (i
+GetSize(c
) < GetSize(sig
) && sig
[i
+GetSize(c
)].wire
== nullptr)
798 c
.bits
.push_back(sig
[i
+GetSize(c
)].data
);
800 if (consts
.count(c
) == 0) {
801 int sid
= get_bv_sid(GetSize(c
));
802 int nid
= next_nid
++;
803 btorf("%d const %d %s\n", nid
, sid
, c
.as_string().c_str());
805 nid_width
[nid
] = GetSize(c
);
808 int nid
= consts
.at(c
);
810 for (int j
= 0; j
< GetSize(c
); j
++)
811 nidbits
.push_back(make_pair(nid
, j
));
818 if (bit_cell
.count(bit
) == 0)
819 log_error("No driver for signal bit %s.\n", log_signal(bit
));
820 export_cell(bit_cell
.at(bit
));
821 log_assert(bit_nid
.count(bit
));
825 nidbits
.push_back(bit_nid
.at(bit
));
831 // group bits and emit slice-concat chain
832 for (int i
= 0; i
< GetSize(nidbits
); i
++)
834 int nid2
= nidbits
[i
].first
;
835 int lower
= nidbits
[i
].second
;
838 while (i
+1 < GetSize(nidbits
) && nidbits
[i
+1].first
== nidbits
[i
].first
&&
839 nidbits
[i
+1].second
== nidbits
[i
].second
+1)
844 if (lower
!= 0 || upper
+1 != nid_width
.at(nid2
)) {
845 int sid
= get_bv_sid(upper
-lower
+1);
847 btorf("%d slice %d %d %d %d\n", nid3
, sid
, nid2
, upper
, lower
);
853 int sid
= get_bv_sid(width
+upper
-lower
+1);
855 btorf("%d concat %d %d %d\n", nid4
, sid
, nid3
, nid
);
858 width
+= upper
-lower
+1;
863 nid_width
[nid
] = width
;
866 nid
= sig_nid
.at(sig
);
869 if (to_width
>= 0 && to_width
!= GetSize(sig
))
871 if (to_width
< GetSize(sig
))
873 int sid
= get_bv_sid(to_width
);
874 int nid2
= next_nid
++;
875 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, to_width
-1);
880 int sid
= get_bv_sid(to_width
);
881 int nid2
= next_nid
++;
882 btorf("%d %s %d %d %d\n", nid2
, is_signed
? "sext" : "uext",
883 sid
, nid
, to_width
- GetSize(sig
));
891 BtorWorker(std::ostream
&f
, RTLIL::Module
*module
, bool verbose
, bool single_bad
) :
892 f(f
), sigmap(module
), module(module
), verbose(verbose
), single_bad(single_bad
)
894 btorf_push("inputs");
896 for (auto wire
: module
->wires())
898 if (wire
->attributes
.count("\\init")) {
899 Const attrval
= wire
->attributes
.at("\\init");
900 for (int i
= 0; i
< GetSize(wire
) && i
< GetSize(attrval
); i
++)
901 if (attrval
[i
] == State::S0
|| attrval
[i
] == State::S1
)
902 initbits
[sigmap(SigBit(wire
, i
))] = (attrval
[i
] == State::S1
);
905 if (!wire
->port_id
|| !wire
->port_input
)
908 SigSpec sig
= sigmap(wire
);
909 int sid
= get_bv_sid(GetSize(sig
));
910 int nid
= next_nid
++;
912 btorf("%d input %d %s\n", nid
, sid
, log_id(wire
));
913 add_nid_sig(nid
, sig
);
918 for (auto cell
: module
->cells())
919 for (auto &conn
: cell
->connections())
921 if (!cell
->output(conn
.first
))
924 for (auto bit
: sigmap(conn
.second
))
925 bit_cell
[bit
] = cell
;
928 for (auto wire
: module
->wires())
930 if (!wire
->port_id
|| !wire
->port_output
)
933 btorf_push(stringf("output %s", log_id(wire
)));
935 int sid
= get_bv_sid(GetSize(wire
));
936 int nid
= get_sig_nid(wire
);
937 btorf("%d output %d %d %s\n", next_nid
++, sid
, nid
, log_id(wire
));
939 btorf_pop(stringf("output %s", log_id(wire
)));
942 for (auto cell
: module
->cells())
944 if (cell
->type
== "$assume")
946 btorf_push(log_id(cell
));
948 int sid
= get_bv_sid(1);
949 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
950 int nid_en
= get_sig_nid(cell
->getPort("\\EN"));
951 int nid_not_en
= next_nid
++;
952 int nid_a_or_not_en
= next_nid
++;
953 int nid
= next_nid
++;
955 btorf("%d not %d %d\n", nid_not_en
, sid
, nid_en
);
956 btorf("%d or %d %d %d\n", nid_a_or_not_en
, sid
, nid_a
, nid_not_en
);
957 btorf("%d constraint %d\n", nid
, nid_a_or_not_en
);
959 btorf_pop(log_id(cell
));
962 if (cell
->type
== "$assert")
964 btorf_push(log_id(cell
));
966 int sid
= get_bv_sid(1);
967 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
968 int nid_en
= get_sig_nid(cell
->getPort("\\EN"));
969 int nid_not_a
= next_nid
++;
970 int nid_en_and_not_a
= next_nid
++;
972 btorf("%d not %d %d\n", nid_not_a
, sid
, nid_a
);
973 btorf("%d and %d %d %d\n", nid_en_and_not_a
, sid
, nid_en
, nid_not_a
);
976 bad_properties
.push_back(nid_en_and_not_a
);
978 int nid
= next_nid
++;
979 btorf("%d bad %d\n", nid
, nid_en_and_not_a
);
982 btorf_pop(log_id(cell
));
986 for (auto wire
: module
->wires())
988 if (wire
->port_id
|| wire
->name
[0] == '$')
991 btorf_push(stringf("wire %s", log_id(wire
)));
993 int sid
= get_bv_sid(GetSize(wire
));
994 int nid
= get_sig_nid(sigmap(wire
));
996 if (statewires
.count(wire
))
999 int this_nid
= next_nid
++;
1000 btorf("%d uext %d %d %d %s\n", this_nid
, sid
, nid
, 0, log_id(wire
));
1002 btorf_pop(stringf("wire %s", log_id(wire
)));
1006 while (!ff_todo
.empty())
1008 vector
<pair
<int, Cell
*>> todo
;
1011 for (auto &it
: todo
)
1014 Cell
*cell
= it
.second
;
1016 btorf_push(stringf("next %s", log_id(cell
)));
1018 if (cell
->type
== "$mem")
1020 int abits
= cell
->getParam("\\ABITS").as_int();
1021 int width
= cell
->getParam("\\WIDTH").as_int();
1022 int wrports
= cell
->getParam("\\WR_PORTS").as_int();
1024 SigSpec sig_wr_addr
= sigmap(cell
->getPort("\\WR_ADDR"));
1025 SigSpec sig_wr_data
= sigmap(cell
->getPort("\\WR_DATA"));
1026 SigSpec sig_wr_en
= sigmap(cell
->getPort("\\WR_EN"));
1028 int data_sid
= get_bv_sid(width
);
1029 int bool_sid
= get_bv_sid(1);
1030 int sid
= get_mem_sid(abits
, width
);
1033 for (int port
= 0; port
< wrports
; port
++)
1035 SigSpec wa
= sig_wr_addr
.extract(port
*abits
, abits
);
1036 SigSpec wd
= sig_wr_data
.extract(port
*width
, width
);
1037 SigSpec we
= sig_wr_en
.extract(port
*width
, width
);
1039 int wa_nid
= get_sig_nid(wa
);
1040 int wd_nid
= get_sig_nid(wd
);
1041 int we_nid
= get_sig_nid(we
);
1043 int nid2
= next_nid
++;
1044 btorf("%d read %d %d %d\n", nid2
, data_sid
, nid_head
, wa_nid
);
1046 int nid3
= next_nid
++;
1047 btorf("%d not %d %d\n", nid3
, data_sid
, we_nid
);
1049 int nid4
= next_nid
++;
1050 btorf("%d and %d %d %d\n", nid4
, data_sid
, nid2
, nid3
);
1052 int nid5
= next_nid
++;
1053 btorf("%d and %d %d %d\n", nid5
, data_sid
, wd_nid
, we_nid
);
1055 int nid6
= next_nid
++;
1056 btorf("%d or %d %d %d\n", nid6
, data_sid
, nid5
, nid4
);
1058 int nid7
= next_nid
++;
1059 btorf("%d write %d %d %d %d\n", nid7
, sid
, nid_head
, wa_nid
, nid6
);
1061 int nid8
= next_nid
++;
1062 btorf("%d redor %d %d\n", nid8
, bool_sid
, we_nid
);
1064 int nid9
= next_nid
++;
1065 btorf("%d ite %d %d %d %d\n", nid9
, sid
, nid8
, nid7
, nid_head
);
1070 int nid2
= next_nid
++;
1071 btorf("%d next %d %d %d\n", nid2
, sid
, nid
, nid_head
);
1075 SigSpec sig
= sigmap(cell
->getPort("\\D"));
1076 int nid_q
= get_sig_nid(sig
);
1077 int sid
= get_bv_sid(GetSize(sig
));
1078 btorf("%d next %d %d %d\n", next_nid
++, sid
, nid
, nid_q
);
1081 btorf_pop(stringf("next %s", log_id(cell
)));
1085 while (!bad_properties
.empty())
1088 bad_properties
.swap(todo
);
1090 int sid
= get_bv_sid(1);
1093 while (cursor
+1 < GetSize(todo
))
1095 int nid_a
= todo
[cursor
++];
1096 int nid_b
= todo
[cursor
++];
1097 int nid
= next_nid
++;
1099 bad_properties
.push_back(nid
);
1100 btorf("%d or %d %d %d\n", nid
, sid
, nid_a
, nid_b
);
1103 if (!bad_properties
.empty()) {
1104 if (cursor
< GetSize(todo
))
1105 bad_properties
.push_back(todo
[cursor
++]);
1106 log_assert(cursor
== GetSize(todo
));
1108 int nid
= next_nid
++;
1109 log_assert(cursor
== 0);
1110 log_assert(GetSize(todo
) == 1);
1111 btorf("%d bad %d\n", nid
, todo
[cursor
]);
1117 struct BtorBackend
: public Backend
{
1118 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1119 void help() YS_OVERRIDE
1121 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1123 log(" write_btor [options] [filename]\n");
1125 log("Write a BTOR description of the current design.\n");
1128 log(" Add comments and indentation to BTOR output file\n");
1131 log(" Output only a single bad property for all asserts\n");
1134 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1136 bool verbose
= false, single_bad
= false;
1138 log_header(design
, "Executing BTOR backend.\n");
1141 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1143 if (args
[argidx
] == "-v") {
1147 if (args
[argidx
] == "-s") {
1153 extra_args(f
, filename
, args
, argidx
);
1155 RTLIL::Module
*topmod
= design
->top_module();
1157 if (topmod
== nullptr)
1158 log_cmd_error("No top module found.\n");
1160 *f
<< stringf("; BTOR description generated by %s for module %s.\n",
1161 yosys_version_str
, log_id(topmod
));
1163 BtorWorker(*f
, topmod
, verbose
, single_bad
);
1165 *f
<< stringf("; end of yosys output\n");
1169 PRIVATE_NAMESPACE_END