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Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
[yosys.git] / backends / btor / btor.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] Btor2 , BtorMC and Boolector 3.0
21 // Aina Niemetz, Mathias Preiner, Clifford Wolf, Armin Biere
22 // Computer Aided Verification - 30th International Conference, CAV 2018
23 // https://cs.stanford.edu/people/niemetz/publication/2018/niemetzpreinerwolfbiere-cav18/
24
25 #include "kernel/rtlil.h"
26 #include "kernel/register.h"
27 #include "kernel/sigtools.h"
28 #include "kernel/celltypes.h"
29 #include "kernel/log.h"
30 #include <string>
31
32 USING_YOSYS_NAMESPACE
33 PRIVATE_NAMESPACE_BEGIN
34
35 struct BtorWorker
36 {
37 std::ostream &f;
38 SigMap sigmap;
39 RTLIL::Module *module;
40 bool verbose;
41 bool single_bad;
42 bool cover_mode;
43
44 int next_nid = 1;
45 int initstate_nid = -1;
46
47 // <width> => <sid>
48 dict<int, int> sorts_bv;
49
50 // (<address-width>, <data-width>) => <sid>
51 dict<pair<int, int>, int> sorts_mem;
52
53 // SigBit => (<nid>, <bitidx>)
54 dict<SigBit, pair<int, int>> bit_nid;
55
56 // <nid> => <bvwidth>
57 dict<int, int> nid_width;
58
59 // SigSpec => <nid>
60 dict<SigSpec, int> sig_nid;
61
62 // bit to driving cell
63 dict<SigBit, Cell*> bit_cell;
64
65 // nids for constants
66 dict<Const, int> consts;
67
68 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
69 vector<pair<int, Cell*>> ff_todo;
70
71 pool<Cell*> cell_recursion_guard;
72 vector<int> bad_properties;
73 dict<SigBit, bool> initbits;
74 pool<Wire*> statewires;
75 pool<string> srcsymbols;
76
77 string indent, info_filename;
78 vector<string> info_lines;
79 dict<int, int> info_clocks;
80
81 void btorf(const char *fmt, ...)
82 {
83 va_list ap;
84 va_start(ap, fmt);
85 f << indent << vstringf(fmt, ap);
86 va_end(ap);
87 }
88
89 void infof(const char *fmt, ...)
90 {
91 va_list ap;
92 va_start(ap, fmt);
93 info_lines.push_back(vstringf(fmt, ap));
94 va_end(ap);
95 }
96
97 template<typename T>
98 string getinfo(T *obj, bool srcsym = false)
99 {
100 string infostr = log_id(obj);
101 if (obj->attributes.count(ID::src)) {
102 string src = obj->attributes.at(ID::src).decode_string().c_str();
103 if (srcsym && infostr[0] == '$') {
104 std::replace(src.begin(), src.end(), ' ', '_');
105 if (srcsymbols.count(src) || module->count_id("\\" + src)) {
106 for (int i = 1;; i++) {
107 string s = stringf("%s-%d", src.c_str(), i);
108 if (!srcsymbols.count(s) && !module->count_id("\\" + s)) {
109 src = s;
110 break;
111 }
112 }
113 }
114 srcsymbols.insert(src);
115 infostr = src;
116 } else {
117 infostr += " ; " + src;
118 }
119 }
120 return infostr;
121 }
122
123 void btorf_push(const string &id)
124 {
125 if (verbose) {
126 f << indent << stringf(" ; begin %s\n", id.c_str());
127 indent += " ";
128 }
129 }
130
131 void btorf_pop(const string &id)
132 {
133 if (verbose) {
134 indent = indent.substr(4);
135 f << indent << stringf(" ; end %s\n", id.c_str());
136 }
137 }
138
139 int get_bv_sid(int width)
140 {
141 if (sorts_bv.count(width) == 0) {
142 int nid = next_nid++;
143 btorf("%d sort bitvec %d\n", nid, width);
144 sorts_bv[width] = nid;
145 }
146 return sorts_bv.at(width);
147 }
148
149 int get_mem_sid(int abits, int dbits)
150 {
151 pair<int, int> key(abits, dbits);
152 if (sorts_mem.count(key) == 0) {
153 int addr_sid = get_bv_sid(abits);
154 int data_sid = get_bv_sid(dbits);
155 int nid = next_nid++;
156 btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
157 sorts_mem[key] = nid;
158 }
159 return sorts_mem.at(key);
160 }
161
162 void add_nid_sig(int nid, const SigSpec &sig)
163 {
164 if (verbose)
165 f << indent << stringf("; %d %s\n", nid, log_signal(sig));
166
167 for (int i = 0; i < GetSize(sig); i++)
168 bit_nid[sig[i]] = make_pair(nid, i);
169
170 sig_nid[sig] = nid;
171 nid_width[nid] = GetSize(sig);
172 }
173
174 void export_cell(Cell *cell)
175 {
176 if (cell_recursion_guard.count(cell)) {
177 string cell_list;
178 for (auto c : cell_recursion_guard)
179 cell_list += stringf("\n %s", log_id(c));
180 log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
181 }
182
183 cell_recursion_guard.insert(cell);
184 btorf_push(log_id(cell));
185
186 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
187 ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
188 {
189 string btor_op;
190 if (cell->type == ID($add)) btor_op = "add";
191 if (cell->type == ID($sub)) btor_op = "sub";
192 if (cell->type == ID($mul)) btor_op = "mul";
193 if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
194 if (cell->type == ID($shr)) btor_op = "srl";
195 if (cell->type == ID($sshr)) btor_op = "sra";
196 if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
197 if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
198 if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
199 if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
200 if (cell->type == ID($concat)) btor_op = "concat";
201 if (cell->type == ID($_NAND_)) btor_op = "nand";
202 if (cell->type == ID($_NOR_)) btor_op = "nor";
203 if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
204 log_assert(!btor_op.empty());
205
206 int width = GetSize(cell->getPort(ID::Y));
207 width = std::max(width, GetSize(cell->getPort(ID::A)));
208 width = std::max(width, GetSize(cell->getPort(ID::B)));
209
210 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
211 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
212
213 if (btor_op == "shift" && !b_signed)
214 btor_op = "srl";
215
216 if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
217 b_signed = false;
218
219 if (cell->type == ID($sshr) && !a_signed)
220 btor_op = "srl";
221
222 int sid = get_bv_sid(width);
223 int nid;
224
225 if (btor_op == "shift")
226 {
227 int nid_a = get_sig_nid(cell->getPort(ID::A), width, false);
228 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
229
230 int nid_r = next_nid++;
231 btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);
232
233 int nid_b_neg = next_nid++;
234 btorf("%d neg %d %d\n", nid_b_neg, sid, nid_b);
235
236 int nid_l = next_nid++;
237 btorf("%d sll %d %d %d\n", nid_l, sid, nid_a, nid_b_neg);
238
239 int sid_bit = get_bv_sid(1);
240 int nid_zero = get_sig_nid(Const(0, width));
241 int nid_b_ltz = next_nid++;
242 btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
243
244 nid = next_nid++;
245 btorf("%d ite %d %d %d %d %s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell).c_str());
246 }
247 else
248 {
249 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
250 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
251
252 nid = next_nid++;
253 btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
254 }
255
256 SigSpec sig = sigmap(cell->getPort(ID::Y));
257
258 if (GetSize(sig) < width) {
259 int sid = get_bv_sid(GetSize(sig));
260 int nid2 = next_nid++;
261 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
262 nid = nid2;
263 }
264
265 add_nid_sig(nid, sig);
266 goto okay;
267 }
268
269 if (cell->type.in(ID($div), ID($mod), ID($modfloor)))
270 {
271 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
272 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
273
274 string btor_op;
275 if (cell->type == ID($div)) btor_op = "div";
276 // "rem" = truncating modulo
277 if (cell->type == ID($mod)) btor_op = "rem";
278 // "mod" = flooring modulo
279 if (cell->type == ID($modfloor)) {
280 // "umod" doesn't exist because it's the same as "urem"
281 btor_op = a_signed || b_signed ? "mod" : "rem";
282 }
283 log_assert(!btor_op.empty());
284
285 int width = GetSize(cell->getPort(ID::Y));
286 width = std::max(width, GetSize(cell->getPort(ID::A)));
287 width = std::max(width, GetSize(cell->getPort(ID::B)));
288
289 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
290 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
291
292 int sid = get_bv_sid(width);
293 int nid = next_nid++;
294 btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
295
296 SigSpec sig = sigmap(cell->getPort(ID::Y));
297
298 if (GetSize(sig) < width) {
299 int sid = get_bv_sid(GetSize(sig));
300 int nid2 = next_nid++;
301 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
302 nid = nid2;
303 }
304
305 add_nid_sig(nid, sig);
306 goto okay;
307 }
308
309 if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
310 {
311 int sid = get_bv_sid(1);
312 int nid_a = get_sig_nid(cell->getPort(ID::A));
313 int nid_b = get_sig_nid(cell->getPort(ID::B));
314
315 int nid1 = next_nid++;
316 int nid2 = next_nid++;
317
318 if (cell->type == ID($_ANDNOT_)) {
319 btorf("%d not %d %d\n", nid1, sid, nid_b);
320 btorf("%d and %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
321 }
322
323 if (cell->type == ID($_ORNOT_)) {
324 btorf("%d not %d %d\n", nid1, sid, nid_b);
325 btorf("%d or %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
326 }
327
328 SigSpec sig = sigmap(cell->getPort(ID::Y));
329 add_nid_sig(nid2, sig);
330 goto okay;
331 }
332
333 if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
334 {
335 int sid = get_bv_sid(1);
336 int nid_a = get_sig_nid(cell->getPort(ID::A));
337 int nid_b = get_sig_nid(cell->getPort(ID::B));
338 int nid_c = get_sig_nid(cell->getPort(ID::C));
339
340 int nid1 = next_nid++;
341 int nid2 = next_nid++;
342 int nid3 = next_nid++;
343
344 if (cell->type == ID($_OAI3_)) {
345 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
346 btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
347 btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
348 }
349
350 if (cell->type == ID($_AOI3_)) {
351 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
352 btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
353 btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
354 }
355
356 SigSpec sig = sigmap(cell->getPort(ID::Y));
357 add_nid_sig(nid3, sig);
358 goto okay;
359 }
360
361 if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
362 {
363 int sid = get_bv_sid(1);
364 int nid_a = get_sig_nid(cell->getPort(ID::A));
365 int nid_b = get_sig_nid(cell->getPort(ID::B));
366 int nid_c = get_sig_nid(cell->getPort(ID::C));
367 int nid_d = get_sig_nid(cell->getPort(ID::D));
368
369 int nid1 = next_nid++;
370 int nid2 = next_nid++;
371 int nid3 = next_nid++;
372 int nid4 = next_nid++;
373
374 if (cell->type == ID($_OAI4_)) {
375 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
376 btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
377 btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
378 btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str());
379 }
380
381 if (cell->type == ID($_AOI4_)) {
382 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
383 btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
384 btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
385 btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str());
386 }
387
388 SigSpec sig = sigmap(cell->getPort(ID::Y));
389 add_nid_sig(nid4, sig);
390 goto okay;
391 }
392
393 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
394 {
395 string btor_op;
396 if (cell->type == ID($lt)) btor_op = "lt";
397 if (cell->type == ID($le)) btor_op = "lte";
398 if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
399 if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
400 if (cell->type == ID($ge)) btor_op = "gte";
401 if (cell->type == ID($gt)) btor_op = "gt";
402 log_assert(!btor_op.empty());
403
404 int width = 1;
405 width = std::max(width, GetSize(cell->getPort(ID::A)));
406 width = std::max(width, GetSize(cell->getPort(ID::B)));
407
408 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
409 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
410
411 int sid = get_bv_sid(1);
412 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
413 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
414
415 int nid = next_nid++;
416 if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
417 btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
418 } else {
419 btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
420 }
421
422 SigSpec sig = sigmap(cell->getPort(ID::Y));
423
424 if (GetSize(sig) > 1) {
425 int sid = get_bv_sid(GetSize(sig));
426 int nid2 = next_nid++;
427 btorf("%d uext %d %d %d\n", nid2, sid, nid, GetSize(sig) - 1);
428 nid = nid2;
429 }
430
431 add_nid_sig(nid, sig);
432 goto okay;
433 }
434
435 if (cell->type.in(ID($not), ID($neg), ID($_NOT_)))
436 {
437 string btor_op;
438 if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
439 if (cell->type == ID($neg)) btor_op = "neg";
440 log_assert(!btor_op.empty());
441
442 int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
443
444 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
445
446 int sid = get_bv_sid(width);
447 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
448
449 int nid = next_nid++;
450 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
451
452 SigSpec sig = sigmap(cell->getPort(ID::Y));
453
454 if (GetSize(sig) < width) {
455 int sid = get_bv_sid(GetSize(sig));
456 int nid2 = next_nid++;
457 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
458 nid = nid2;
459 }
460
461 add_nid_sig(nid, sig);
462 goto okay;
463 }
464
465 if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
466 {
467 string btor_op;
468 if (cell->type == ID($logic_and)) btor_op = "and";
469 if (cell->type == ID($logic_or)) btor_op = "or";
470 if (cell->type == ID($logic_not)) btor_op = "not";
471 log_assert(!btor_op.empty());
472
473 int sid = get_bv_sid(1);
474 int nid_a = get_sig_nid(cell->getPort(ID::A));
475 int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0;
476
477 if (GetSize(cell->getPort(ID::A)) > 1) {
478 int nid_red_a = next_nid++;
479 btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
480 nid_a = nid_red_a;
481 }
482
483 if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) {
484 int nid_red_b = next_nid++;
485 btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
486 nid_b = nid_red_b;
487 }
488
489 int nid = next_nid++;
490 if (btor_op != "not")
491 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
492 else
493 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
494
495 SigSpec sig = sigmap(cell->getPort(ID::Y));
496
497 if (GetSize(sig) > 1) {
498 int sid = get_bv_sid(GetSize(sig));
499 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
500 int nid2 = next_nid++;
501 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
502 nid = nid2;
503 }
504
505 add_nid_sig(nid, sig);
506 goto okay;
507 }
508
509 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
510 {
511 string btor_op;
512 if (cell->type == ID($reduce_and)) btor_op = "redand";
513 if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
514 if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
515 log_assert(!btor_op.empty());
516
517 int sid = get_bv_sid(1);
518 int nid_a = get_sig_nid(cell->getPort(ID::A));
519
520 int nid = next_nid++;
521
522 if (cell->type == ID($reduce_xnor)) {
523 int nid2 = next_nid++;
524 btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
525 btorf("%d not %d %d %d\n", nid2, sid, nid);
526 nid = nid2;
527 } else {
528 btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
529 }
530
531 SigSpec sig = sigmap(cell->getPort(ID::Y));
532
533 if (GetSize(sig) > 1) {
534 int sid = get_bv_sid(GetSize(sig));
535 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
536 int nid2 = next_nid++;
537 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
538 nid = nid2;
539 }
540
541 add_nid_sig(nid, sig);
542 goto okay;
543 }
544
545 if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
546 {
547 SigSpec sig_a = sigmap(cell->getPort(ID::A));
548 SigSpec sig_b = sigmap(cell->getPort(ID::B));
549 SigSpec sig_s = sigmap(cell->getPort(ID::S));
550 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
551
552 int nid_a = get_sig_nid(sig_a);
553 int nid_b = get_sig_nid(sig_b);
554 int nid_s = get_sig_nid(sig_s);
555
556 int sid = get_bv_sid(GetSize(sig_y));
557 int nid = next_nid++;
558
559 if (cell->type == ID($_NMUX_)) {
560 int tmp = nid;
561 nid = next_nid++;
562 btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
563 btorf("%d not %d %d %s\n", nid, sid, tmp, getinfo(cell).c_str());
564 } else {
565 btorf("%d ite %d %d %d %d %s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell).c_str());
566 }
567
568 add_nid_sig(nid, sig_y);
569 goto okay;
570 }
571
572 if (cell->type == ID($pmux))
573 {
574 SigSpec sig_a = sigmap(cell->getPort(ID::A));
575 SigSpec sig_b = sigmap(cell->getPort(ID::B));
576 SigSpec sig_s = sigmap(cell->getPort(ID::S));
577 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
578
579 int width = GetSize(sig_a);
580 int sid = get_bv_sid(width);
581 int nid = get_sig_nid(sig_a);
582
583 for (int i = 0; i < GetSize(sig_s); i++) {
584 int nid_b = get_sig_nid(sig_b.extract(i*width, width));
585 int nid_s = get_sig_nid(sig_s.extract(i));
586 int nid2 = next_nid++;
587 if (i == GetSize(sig_s)-1)
588 btorf("%d ite %d %d %d %d %s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell).c_str());
589 else
590 btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
591 nid = nid2;
592 }
593
594 add_nid_sig(nid, sig_y);
595 goto okay;
596 }
597
598 if (cell->type.in(ID($dff), ID($ff), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
599 {
600 SigSpec sig_d = sigmap(cell->getPort(ID::D));
601 SigSpec sig_q = sigmap(cell->getPort(ID::Q));
602
603 if (!info_filename.empty() && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
604 {
605 SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C));
606 int nid = get_sig_nid(sig_c);
607 bool negedge = false;
608
609 if (cell->type == ID($_DFF_N_))
610 negedge = true;
611
612 if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
613 negedge = true;
614
615 info_clocks[nid] |= negedge ? 2 : 1;
616 }
617
618 IdString symbol;
619
620 if (sig_q.is_wire()) {
621 Wire *w = sig_q.as_wire();
622 if (w->port_id == 0) {
623 statewires.insert(w);
624 symbol = w->name;
625 }
626 }
627
628 Const initval;
629 for (int i = 0; i < GetSize(sig_q); i++)
630 if (initbits.count(sig_q[i]))
631 initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
632 else
633 initval.bits.push_back(State::Sx);
634
635 int nid_init_val = -1;
636
637 if (!initval.is_fully_undef())
638 nid_init_val = get_sig_nid(initval, -1, false, true);
639
640 int sid = get_bv_sid(GetSize(sig_q));
641 int nid = next_nid++;
642
643 if (symbol.empty())
644 btorf("%d state %d\n", nid, sid);
645 else
646 btorf("%d state %d %s\n", nid, sid, log_id(symbol));
647
648 if (nid_init_val >= 0) {
649 int nid_init = next_nid++;
650 if (verbose)
651 btorf("; initval = %s\n", log_signal(initval));
652 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
653 }
654
655 ff_todo.push_back(make_pair(nid, cell));
656 add_nid_sig(nid, sig_q);
657 goto okay;
658 }
659
660 if (cell->type.in(ID($anyconst), ID($anyseq)))
661 {
662 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
663
664 int sid = get_bv_sid(GetSize(sig_y));
665 int nid = next_nid++;
666
667 btorf("%d state %d\n", nid, sid);
668
669 if (cell->type == ID($anyconst)) {
670 int nid2 = next_nid++;
671 btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
672 }
673
674 add_nid_sig(nid, sig_y);
675 goto okay;
676 }
677
678 if (cell->type == ID($initstate))
679 {
680 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
681
682 if (initstate_nid < 0)
683 {
684 int sid = get_bv_sid(1);
685 int one_nid = get_sig_nid(State::S1);
686 int zero_nid = get_sig_nid(State::S0);
687 initstate_nid = next_nid++;
688 btorf("%d state %d\n", initstate_nid, sid);
689 btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
690 btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
691 }
692
693 add_nid_sig(initstate_nid, sig_y);
694 goto okay;
695 }
696
697 if (cell->type == ID($mem))
698 {
699 int abits = cell->getParam(ID::ABITS).as_int();
700 int width = cell->getParam(ID::WIDTH).as_int();
701 int nwords = cell->getParam(ID::SIZE).as_int();
702 int rdports = cell->getParam(ID::RD_PORTS).as_int();
703 int wrports = cell->getParam(ID::WR_PORTS).as_int();
704
705 Const wr_clk_en = cell->getParam(ID::WR_CLK_ENABLE);
706 Const rd_clk_en = cell->getParam(ID::RD_CLK_ENABLE);
707
708 bool asyncwr = wr_clk_en.is_fully_zero();
709
710 if (!asyncwr && !wr_clk_en.is_fully_ones())
711 log_error("Memory %s.%s has mixed async/sync write ports.\n",
712 log_id(module), log_id(cell));
713
714 if (!rd_clk_en.is_fully_zero())
715 log_error("Memory %s.%s has sync read ports.\n",
716 log_id(module), log_id(cell));
717
718 SigSpec sig_rd_addr = sigmap(cell->getPort(ID::RD_ADDR));
719 SigSpec sig_rd_data = sigmap(cell->getPort(ID::RD_DATA));
720
721 SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
722 SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
723 SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
724
725 int data_sid = get_bv_sid(width);
726 int bool_sid = get_bv_sid(1);
727 int sid = get_mem_sid(abits, width);
728
729 Const initdata = cell->getParam(ID::INIT);
730 initdata.exts(nwords*width);
731 int nid_init_val = -1;
732
733 if (!initdata.is_fully_undef())
734 {
735 bool constword = true;
736 Const firstword = initdata.extract(0, width);
737
738 for (int i = 1; i < nwords; i++) {
739 Const thisword = initdata.extract(i*width, width);
740 if (thisword != firstword) {
741 constword = false;
742 break;
743 }
744 }
745
746 if (constword)
747 {
748 if (verbose)
749 btorf("; initval = %s\n", log_signal(firstword));
750 nid_init_val = get_sig_nid(firstword, -1, false, true);
751 }
752 else
753 {
754 nid_init_val = next_nid++;
755 btorf("%d state %d\n", nid_init_val, sid);
756
757 for (int i = 0; i < nwords; i++) {
758 Const thisword = initdata.extract(i*width, width);
759 if (thisword.is_fully_undef())
760 continue;
761 Const thisaddr(i, abits);
762 int nid_thisword = get_sig_nid(thisword, -1, false, true);
763 int nid_thisaddr = get_sig_nid(thisaddr, -1, false, true);
764 int last_nid_init_val = nid_init_val;
765 nid_init_val = next_nid++;
766 if (verbose)
767 btorf("; initval[%d] = %s\n", i, log_signal(thisword));
768 btorf("%d write %d %d %d %d\n", nid_init_val, sid, last_nid_init_val, nid_thisaddr, nid_thisword);
769 }
770 }
771 }
772
773
774 int nid = next_nid++;
775 int nid_head = nid;
776
777 if (cell->name[0] == '$')
778 btorf("%d state %d\n", nid, sid);
779 else
780 btorf("%d state %d %s\n", nid, sid, log_id(cell));
781
782 if (nid_init_val >= 0)
783 {
784 int nid_init = next_nid++;
785 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
786 }
787
788 if (asyncwr)
789 {
790 for (int port = 0; port < wrports; port++)
791 {
792 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
793 SigSpec wd = sig_wr_data.extract(port*width, width);
794 SigSpec we = sig_wr_en.extract(port*width, width);
795
796 int wa_nid = get_sig_nid(wa);
797 int wd_nid = get_sig_nid(wd);
798 int we_nid = get_sig_nid(we);
799
800 int nid2 = next_nid++;
801 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
802
803 int nid3 = next_nid++;
804 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
805
806 int nid4 = next_nid++;
807 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
808
809 int nid5 = next_nid++;
810 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
811
812 int nid6 = next_nid++;
813 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
814
815 int nid7 = next_nid++;
816 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
817
818 int nid8 = next_nid++;
819 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
820
821 int nid9 = next_nid++;
822 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
823
824 nid_head = nid9;
825 }
826 }
827
828 for (int port = 0; port < rdports; port++)
829 {
830 SigSpec ra = sig_rd_addr.extract(port*abits, abits);
831 SigSpec rd = sig_rd_data.extract(port*width, width);
832
833 int ra_nid = get_sig_nid(ra);
834 int rd_nid = next_nid++;
835
836 btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);
837
838 add_nid_sig(rd_nid, rd);
839 }
840
841 if (!asyncwr)
842 {
843 ff_todo.push_back(make_pair(nid, cell));
844 }
845 else
846 {
847 int nid2 = next_nid++;
848 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
849 }
850
851 goto okay;
852 }
853
854 log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
855
856 okay:
857 btorf_pop(log_id(cell));
858 cell_recursion_guard.erase(cell);
859 }
860
861 int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false, bool is_init = false)
862 {
863 int nid = -1;
864 sigmap.apply(sig);
865
866 for (auto bit : sig)
867 if (bit == State::Sx)
868 goto has_undef_bits;
869
870 if (0)
871 {
872 has_undef_bits:
873 SigSpec sig_mask_undef, sig_noundef;
874 int first_undef = -1;
875
876 for (int i = 0; i < GetSize(sig); i++)
877 if (sig[i] == State::Sx) {
878 if (first_undef < 0)
879 first_undef = i;
880 sig_mask_undef.append(State::S1);
881 sig_noundef.append(State::S0);
882 } else {
883 sig_mask_undef.append(State::S0);
884 sig_noundef.append(sig[i]);
885 }
886
887 if (to_width < 0 || first_undef < to_width)
888 {
889 int sid = get_bv_sid(GetSize(sig));
890
891 int nid_input = next_nid++;
892 if (is_init)
893 btorf("%d state %d\n", nid_input, sid);
894 else
895 btorf("%d input %d\n", nid_input, sid);
896
897 int nid_masked_input;
898 if (sig_mask_undef.is_fully_ones()) {
899 nid_masked_input = nid_input;
900 } else {
901 int nid_mask_undef = get_sig_nid(sig_mask_undef);
902 nid_masked_input = next_nid++;
903 btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
904 }
905
906 if (sig_noundef.is_fully_zero()) {
907 nid = nid_masked_input;
908 } else {
909 int nid_noundef = get_sig_nid(sig_noundef);
910 nid = next_nid++;
911 btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
912 }
913
914 goto extend_or_trim;
915 }
916
917 sig = sig_noundef;
918 }
919
920 if (sig_nid.count(sig) == 0)
921 {
922 // <nid>, <bitidx>
923 vector<pair<int, int>> nidbits;
924
925 // collect all bits
926 for (int i = 0; i < GetSize(sig); i++)
927 {
928 SigBit bit = sig[i];
929
930 if (bit_nid.count(bit) == 0)
931 {
932 if (bit.wire == nullptr)
933 {
934 Const c(bit.data);
935
936 while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
937 c.bits.push_back(sig[i+GetSize(c)].data);
938
939 if (consts.count(c) == 0) {
940 int sid = get_bv_sid(GetSize(c));
941 int nid = next_nid++;
942 btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
943 consts[c] = nid;
944 nid_width[nid] = GetSize(c);
945 }
946
947 int nid = consts.at(c);
948
949 for (int j = 0; j < GetSize(c); j++)
950 nidbits.push_back(make_pair(nid, j));
951
952 i += GetSize(c)-1;
953 continue;
954 }
955 else
956 {
957 if (bit_cell.count(bit) == 0)
958 {
959 SigSpec s = bit;
960
961 while (i+GetSize(s) < GetSize(sig) && sig[i+GetSize(s)].wire != nullptr &&
962 bit_cell.count(sig[i+GetSize(s)]) == 0)
963 s.append(sig[i+GetSize(s)]);
964
965 log_warning("No driver for signal %s.\n", log_signal(s));
966
967 int sid = get_bv_sid(GetSize(s));
968 int nid = next_nid++;
969 btorf("%d input %d\n", nid, sid);
970 nid_width[nid] = GetSize(s);
971
972 for (int j = 0; j < GetSize(s); j++)
973 nidbits.push_back(make_pair(nid, j));
974
975 i += GetSize(s)-1;
976 continue;
977 }
978 else
979 {
980 export_cell(bit_cell.at(bit));
981 log_assert(bit_nid.count(bit));
982 }
983 }
984 }
985
986 nidbits.push_back(bit_nid.at(bit));
987 }
988
989 int width = 0;
990 int nid = -1;
991
992 // group bits and emit slice-concat chain
993 for (int i = 0; i < GetSize(nidbits); i++)
994 {
995 int nid2 = nidbits[i].first;
996 int lower = nidbits[i].second;
997 int upper = lower;
998
999 while (i+1 < GetSize(nidbits) && nidbits[i+1].first == nidbits[i].first &&
1000 nidbits[i+1].second == nidbits[i].second+1)
1001 upper++, i++;
1002
1003 int nid3 = nid2;
1004
1005 if (lower != 0 || upper+1 != nid_width.at(nid2)) {
1006 int sid = get_bv_sid(upper-lower+1);
1007 nid3 = next_nid++;
1008 btorf("%d slice %d %d %d %d\n", nid3, sid, nid2, upper, lower);
1009 }
1010
1011 int nid4 = nid3;
1012
1013 if (nid >= 0) {
1014 int sid = get_bv_sid(width+upper-lower+1);
1015 nid4 = next_nid++;
1016 btorf("%d concat %d %d %d\n", nid4, sid, nid3, nid);
1017 }
1018
1019 width += upper-lower+1;
1020 nid = nid4;
1021 }
1022
1023 sig_nid[sig] = nid;
1024 nid_width[nid] = width;
1025 }
1026
1027 nid = sig_nid.at(sig);
1028
1029 extend_or_trim:
1030 if (to_width >= 0 && to_width != GetSize(sig))
1031 {
1032 if (to_width < GetSize(sig))
1033 {
1034 int sid = get_bv_sid(to_width);
1035 int nid2 = next_nid++;
1036 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, to_width-1);
1037 nid = nid2;
1038 }
1039 else
1040 {
1041 int sid = get_bv_sid(to_width);
1042 int nid2 = next_nid++;
1043 btorf("%d %s %d %d %d\n", nid2, is_signed ? "sext" : "uext",
1044 sid, nid, to_width - GetSize(sig));
1045 nid = nid2;
1046 }
1047 }
1048
1049 return nid;
1050 }
1051
1052 BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad, bool cover_mode, string info_filename) :
1053 f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad), cover_mode(cover_mode), info_filename(info_filename)
1054 {
1055 if (!info_filename.empty())
1056 infof("name %s\n", log_id(module));
1057
1058 btorf_push("inputs");
1059
1060 for (auto wire : module->wires())
1061 {
1062 if (wire->attributes.count(ID::init)) {
1063 Const attrval = wire->attributes.at(ID::init);
1064 for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
1065 if (attrval[i] == State::S0 || attrval[i] == State::S1)
1066 initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
1067 }
1068
1069 if (!wire->port_id || !wire->port_input)
1070 continue;
1071
1072 SigSpec sig = sigmap(wire);
1073 int sid = get_bv_sid(GetSize(sig));
1074 int nid = next_nid++;
1075
1076 btorf("%d input %d %s\n", nid, sid, getinfo(wire).c_str());
1077 add_nid_sig(nid, sig);
1078 }
1079
1080 btorf_pop("inputs");
1081
1082 for (auto cell : module->cells())
1083 for (auto &conn : cell->connections())
1084 {
1085 if (!cell->output(conn.first))
1086 continue;
1087
1088 for (auto bit : sigmap(conn.second))
1089 bit_cell[bit] = cell;
1090 }
1091
1092 for (auto wire : module->wires())
1093 {
1094 if (!wire->port_id || !wire->port_output)
1095 continue;
1096
1097 btorf_push(stringf("output %s", log_id(wire)));
1098
1099 int nid = get_sig_nid(wire);
1100 btorf("%d output %d %s\n", next_nid++, nid, getinfo(wire).c_str());
1101
1102 btorf_pop(stringf("output %s", log_id(wire)));
1103 }
1104
1105 for (auto cell : module->cells())
1106 {
1107 if (cell->type == ID($assume))
1108 {
1109 btorf_push(log_id(cell));
1110
1111 int sid = get_bv_sid(1);
1112 int nid_a = get_sig_nid(cell->getPort(ID::A));
1113 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1114 int nid_not_en = next_nid++;
1115 int nid_a_or_not_en = next_nid++;
1116 int nid = next_nid++;
1117
1118 btorf("%d not %d %d\n", nid_not_en, sid, nid_en);
1119 btorf("%d or %d %d %d\n", nid_a_or_not_en, sid, nid_a, nid_not_en);
1120 btorf("%d constraint %d\n", nid, nid_a_or_not_en);
1121
1122 btorf_pop(log_id(cell));
1123 }
1124
1125 if (cell->type == ID($assert))
1126 {
1127 btorf_push(log_id(cell));
1128
1129 int sid = get_bv_sid(1);
1130 int nid_a = get_sig_nid(cell->getPort(ID::A));
1131 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1132 int nid_not_a = next_nid++;
1133 int nid_en_and_not_a = next_nid++;
1134
1135 btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
1136 btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);
1137
1138 if (single_bad && !cover_mode) {
1139 bad_properties.push_back(nid_en_and_not_a);
1140 } else {
1141 if (cover_mode) {
1142 infof("bad %d %s\n", nid_en_and_not_a, getinfo(cell, true).c_str());
1143 } else {
1144 int nid = next_nid++;
1145 btorf("%d bad %d %s\n", nid, nid_en_and_not_a, getinfo(cell, true).c_str());
1146 }
1147 }
1148
1149 btorf_pop(log_id(cell));
1150 }
1151
1152 if (cell->type == ID($cover) && cover_mode)
1153 {
1154 btorf_push(log_id(cell));
1155
1156 int sid = get_bv_sid(1);
1157 int nid_a = get_sig_nid(cell->getPort(ID::A));
1158 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1159 int nid_en_and_a = next_nid++;
1160
1161 btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a);
1162
1163 if (single_bad) {
1164 bad_properties.push_back(nid_en_and_a);
1165 } else {
1166 int nid = next_nid++;
1167 btorf("%d bad %d %s\n", nid, nid_en_and_a, getinfo(cell, true).c_str());
1168 }
1169
1170 btorf_pop(log_id(cell));
1171 }
1172 }
1173
1174 for (auto wire : module->wires())
1175 {
1176 if (wire->port_id || wire->name[0] == '$')
1177 continue;
1178
1179 btorf_push(stringf("wire %s", log_id(wire)));
1180
1181 int sid = get_bv_sid(GetSize(wire));
1182 int nid = get_sig_nid(sigmap(wire));
1183
1184 if (statewires.count(wire))
1185 continue;
1186
1187 int this_nid = next_nid++;
1188 btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, getinfo(wire).c_str());
1189
1190 btorf_pop(stringf("wire %s", log_id(wire)));
1191 continue;
1192 }
1193
1194 while (!ff_todo.empty())
1195 {
1196 vector<pair<int, Cell*>> todo;
1197 todo.swap(ff_todo);
1198
1199 for (auto &it : todo)
1200 {
1201 int nid = it.first;
1202 Cell *cell = it.second;
1203
1204 btorf_push(stringf("next %s", log_id(cell)));
1205
1206 if (cell->type == ID($mem))
1207 {
1208 int abits = cell->getParam(ID::ABITS).as_int();
1209 int width = cell->getParam(ID::WIDTH).as_int();
1210 int wrports = cell->getParam(ID::WR_PORTS).as_int();
1211
1212 SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
1213 SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
1214 SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
1215
1216 int data_sid = get_bv_sid(width);
1217 int bool_sid = get_bv_sid(1);
1218 int sid = get_mem_sid(abits, width);
1219 int nid_head = nid;
1220
1221 for (int port = 0; port < wrports; port++)
1222 {
1223 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
1224 SigSpec wd = sig_wr_data.extract(port*width, width);
1225 SigSpec we = sig_wr_en.extract(port*width, width);
1226
1227 int wa_nid = get_sig_nid(wa);
1228 int wd_nid = get_sig_nid(wd);
1229 int we_nid = get_sig_nid(we);
1230
1231 int nid2 = next_nid++;
1232 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
1233
1234 int nid3 = next_nid++;
1235 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
1236
1237 int nid4 = next_nid++;
1238 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
1239
1240 int nid5 = next_nid++;
1241 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
1242
1243 int nid6 = next_nid++;
1244 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
1245
1246 int nid7 = next_nid++;
1247 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
1248
1249 int nid8 = next_nid++;
1250 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
1251
1252 int nid9 = next_nid++;
1253 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
1254
1255 nid_head = nid9;
1256 }
1257
1258 int nid2 = next_nid++;
1259 btorf("%d next %d %d %d %s\n", nid2, sid, nid, nid_head, getinfo(cell).c_str());
1260 }
1261 else
1262 {
1263 SigSpec sig = sigmap(cell->getPort(ID::D));
1264 int nid_q = get_sig_nid(sig);
1265 int sid = get_bv_sid(GetSize(sig));
1266 btorf("%d next %d %d %d %s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());
1267 }
1268
1269 btorf_pop(stringf("next %s", log_id(cell)));
1270 }
1271 }
1272
1273 while (!bad_properties.empty())
1274 {
1275 vector<int> todo;
1276 bad_properties.swap(todo);
1277
1278 int sid = get_bv_sid(1);
1279 int cursor = 0;
1280
1281 while (cursor+1 < GetSize(todo))
1282 {
1283 int nid_a = todo[cursor++];
1284 int nid_b = todo[cursor++];
1285 int nid = next_nid++;
1286
1287 bad_properties.push_back(nid);
1288 btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
1289 }
1290
1291 if (!bad_properties.empty()) {
1292 if (cursor < GetSize(todo))
1293 bad_properties.push_back(todo[cursor++]);
1294 log_assert(cursor == GetSize(todo));
1295 } else {
1296 int nid = next_nid++;
1297 log_assert(cursor == 0);
1298 log_assert(GetSize(todo) == 1);
1299 btorf("%d bad %d\n", nid, todo[cursor]);
1300 }
1301 }
1302
1303 if (!info_filename.empty())
1304 {
1305 for (auto &it : info_clocks)
1306 {
1307 switch (it.second)
1308 {
1309 case 1:
1310 infof("posedge %d\n", it.first);
1311 break;
1312 case 2:
1313 infof("negedge %d\n", it.first);
1314 break;
1315 case 3:
1316 infof("event %d\n", it.first);
1317 break;
1318 default:
1319 log_abort();
1320 }
1321 }
1322
1323 std::ofstream f;
1324 f.open(info_filename.c_str(), std::ofstream::trunc);
1325 if (f.fail())
1326 log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno));
1327 for (auto &it : info_lines)
1328 f << it;
1329 f.close();
1330 }
1331 }
1332 };
1333
1334 struct BtorBackend : public Backend {
1335 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1336 void help() YS_OVERRIDE
1337 {
1338 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1339 log("\n");
1340 log(" write_btor [options] [filename]\n");
1341 log("\n");
1342 log("Write a BTOR description of the current design.\n");
1343 log("\n");
1344 log(" -v\n");
1345 log(" Add comments and indentation to BTOR output file\n");
1346 log("\n");
1347 log(" -s\n");
1348 log(" Output only a single bad property for all asserts\n");
1349 log("\n");
1350 log(" -c\n");
1351 log(" Output cover properties using 'bad' statements instead of asserts\n");
1352 log("\n");
1353 log(" -i <filename>\n");
1354 log(" Create additional info file with auxiliary information\n");
1355 log("\n");
1356 }
1357 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1358 {
1359 bool verbose = false, single_bad = false, cover_mode = false;
1360 string info_filename;
1361
1362 log_header(design, "Executing BTOR backend.\n");
1363
1364 size_t argidx;
1365 for (argidx = 1; argidx < args.size(); argidx++)
1366 {
1367 if (args[argidx] == "-v") {
1368 verbose = true;
1369 continue;
1370 }
1371 if (args[argidx] == "-s") {
1372 single_bad = true;
1373 continue;
1374 }
1375 if (args[argidx] == "-c") {
1376 cover_mode = true;
1377 continue;
1378 }
1379 if (args[argidx] == "-i" && argidx+1 < args.size()) {
1380 info_filename = args[++argidx];
1381 continue;
1382 }
1383 break;
1384 }
1385 extra_args(f, filename, args, argidx);
1386
1387 RTLIL::Module *topmod = design->top_module();
1388
1389 if (topmod == nullptr)
1390 log_cmd_error("No top module found.\n");
1391
1392 *f << stringf("; BTOR description generated by %s for module %s.\n",
1393 yosys_version_str, log_id(topmod));
1394
1395 BtorWorker(*f, topmod, verbose, single_bad, cover_mode, info_filename);
1396
1397 *f << stringf("; end of yosys output\n");
1398 }
1399 } BtorBackend;
1400
1401 PRIVATE_NAMESPACE_END