2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 // [[CITE]] Btor2 , BtorMC and Boolector 3.0
21 // Aina Niemetz, Mathias Preiner, Clifford Wolf, Armin Biere
22 // Computer Aided Verification - 30th International Conference, CAV 2018
23 // https://cs.stanford.edu/people/niemetz/publication/2018/niemetzpreinerwolfbiere-cav18/
25 #include "kernel/rtlil.h"
26 #include "kernel/register.h"
27 #include "kernel/sigtools.h"
28 #include "kernel/celltypes.h"
29 #include "kernel/log.h"
33 PRIVATE_NAMESPACE_BEGIN
39 RTLIL::Module
*module
;
43 bool print_internal_names
;
46 int initstate_nid
= -1;
49 dict
<int, int> sorts_bv
;
51 // (<address-width>, <data-width>) => <sid>
52 dict
<pair
<int, int>, int> sorts_mem
;
54 // SigBit => (<nid>, <bitidx>)
55 dict
<SigBit
, pair
<int, int>> bit_nid
;
58 dict
<int, int> nid_width
;
61 dict
<SigSpec
, int> sig_nid
;
63 // bit to driving cell
64 dict
<SigBit
, Cell
*> bit_cell
;
67 dict
<Const
, int> consts
;
69 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
70 vector
<pair
<int, Cell
*>> ff_todo
;
72 pool
<Cell
*> cell_recursion_guard
;
73 vector
<int> bad_properties
;
74 dict
<SigBit
, bool> initbits
;
75 pool
<Wire
*> statewires
;
76 pool
<string
> srcsymbols
;
78 string indent
, info_filename
;
79 vector
<string
> info_lines
;
80 dict
<int, int> info_clocks
;
82 void btorf(const char *fmt
, ...) YS_ATTRIBUTE(format(printf
, 2, 3))
86 f
<< indent
<< vstringf(fmt
, ap
);
90 void infof(const char *fmt
, ...) YS_ATTRIBUTE(format(printf
, 2, 3))
94 info_lines
.push_back(vstringf(fmt
, ap
));
99 string
getinfo(T
*obj
, bool srcsym
= false)
101 string infostr
= log_id(obj
);
102 if (!srcsym
&& !print_internal_names
&& infostr
[0] == '$') return "";
103 if (obj
->attributes
.count(ID::src
)) {
104 string src
= obj
->attributes
.at(ID::src
).decode_string().c_str();
105 if (srcsym
&& infostr
[0] == '$') {
106 std::replace(src
.begin(), src
.end(), ' ', '_');
107 if (srcsymbols
.count(src
) || module
->count_id("\\" + src
)) {
108 for (int i
= 1;; i
++) {
109 string s
= stringf("%s-%d", src
.c_str(), i
);
110 if (!srcsymbols
.count(s
) && !module
->count_id("\\" + s
)) {
116 srcsymbols
.insert(src
);
119 infostr
+= " ; " + src
;
122 return " " + infostr
;
125 void btorf_push(const string
&id
)
128 f
<< indent
<< stringf(" ; begin %s\n", id
.c_str());
133 void btorf_pop(const string
&id
)
136 indent
= indent
.substr(4);
137 f
<< indent
<< stringf(" ; end %s\n", id
.c_str());
141 int get_bv_sid(int width
)
143 if (sorts_bv
.count(width
) == 0) {
144 int nid
= next_nid
++;
145 btorf("%d sort bitvec %d\n", nid
, width
);
146 sorts_bv
[width
] = nid
;
148 return sorts_bv
.at(width
);
151 int get_mem_sid(int abits
, int dbits
)
153 pair
<int, int> key(abits
, dbits
);
154 if (sorts_mem
.count(key
) == 0) {
155 int addr_sid
= get_bv_sid(abits
);
156 int data_sid
= get_bv_sid(dbits
);
157 int nid
= next_nid
++;
158 btorf("%d sort array %d %d\n", nid
, addr_sid
, data_sid
);
159 sorts_mem
[key
] = nid
;
161 return sorts_mem
.at(key
);
164 void add_nid_sig(int nid
, const SigSpec
&sig
)
167 f
<< indent
<< stringf("; %d %s\n", nid
, log_signal(sig
));
169 for (int i
= 0; i
< GetSize(sig
); i
++)
170 bit_nid
[sig
[i
]] = make_pair(nid
, i
);
173 nid_width
[nid
] = GetSize(sig
);
176 void export_cell(Cell
*cell
)
178 if (cell_recursion_guard
.count(cell
)) {
180 for (auto c
: cell_recursion_guard
)
181 cell_list
+= stringf("\n %s", log_id(c
));
182 log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell
), cell_list
.c_str());
185 cell_recursion_guard
.insert(cell
);
186 btorf_push(log_id(cell
));
188 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($
and), ID($
or), ID($
xor), ID($xnor
), ID($shl
), ID($sshl
), ID($shr
), ID($sshr
), ID($shift
), ID($shiftx
),
189 ID($concat
), ID($_AND_
), ID($_NAND_
), ID($_OR_
), ID($_NOR_
), ID($_XOR_
), ID($_XNOR_
)))
192 if (cell
->type
== ID($add
)) btor_op
= "add";
193 if (cell
->type
== ID($sub
)) btor_op
= "sub";
194 if (cell
->type
== ID($mul
)) btor_op
= "mul";
195 if (cell
->type
.in(ID($shl
), ID($sshl
))) btor_op
= "sll";
196 if (cell
->type
== ID($shr
)) btor_op
= "srl";
197 if (cell
->type
== ID($sshr
)) btor_op
= "sra";
198 if (cell
->type
.in(ID($shift
), ID($shiftx
))) btor_op
= "shift";
199 if (cell
->type
.in(ID($
and), ID($_AND_
))) btor_op
= "and";
200 if (cell
->type
.in(ID($
or), ID($_OR_
))) btor_op
= "or";
201 if (cell
->type
.in(ID($
xor), ID($_XOR_
))) btor_op
= "xor";
202 if (cell
->type
== ID($concat
)) btor_op
= "concat";
203 if (cell
->type
== ID($_NAND_
)) btor_op
= "nand";
204 if (cell
->type
== ID($_NOR_
)) btor_op
= "nor";
205 if (cell
->type
.in(ID($xnor
), ID($_XNOR_
))) btor_op
= "xnor";
206 log_assert(!btor_op
.empty());
208 int width_ay
= std::max(GetSize(cell
->getPort(ID::A
)), GetSize(cell
->getPort(ID::Y
)));
209 int width
= std::max(width_ay
, GetSize(cell
->getPort(ID::B
)));
211 bool a_signed
= cell
->hasParam(ID::A_SIGNED
) ? cell
->getParam(ID::A_SIGNED
).as_bool() : false;
212 bool b_signed
= cell
->hasParam(ID::B_SIGNED
) ? cell
->getParam(ID::B_SIGNED
).as_bool() : false;
214 if (btor_op
== "shift" && !b_signed
)
217 if (cell
->type
.in(ID($shl
), ID($sshl
), ID($shr
), ID($sshr
)))
220 if (cell
->type
== ID($sshr
) && !a_signed
)
223 int sid
= get_bv_sid(width
);
227 if (cell
->type
.in(ID($shl
), ID($shr
), ID($shift
), ID($shiftx
)) && a_signed
&& width_ay
< width
) {
228 // sign-extend A up to the width of Y
229 int nid_a_padded
= get_sig_nid(cell
->getPort(ID::A
), width_ay
, a_signed
);
231 // zero-extend the rest
232 int zeroes
= get_sig_nid(Const(0, width
-width_ay
));
234 btorf("%d concat %d %d %d\n", nid_a
, sid
, zeroes
, nid_a_padded
);
236 nid_a
= get_sig_nid(cell
->getPort(ID::A
), width
, a_signed
);
239 int nid_b
= get_sig_nid(cell
->getPort(ID::B
), width
, b_signed
);
241 if (btor_op
== "shift")
243 int nid_r
= next_nid
++;
244 btorf("%d srl %d %d %d\n", nid_r
, sid
, nid_a
, nid_b
);
246 int nid_b_neg
= next_nid
++;
247 btorf("%d neg %d %d\n", nid_b_neg
, sid
, nid_b
);
249 int nid_l
= next_nid
++;
250 btorf("%d sll %d %d %d\n", nid_l
, sid
, nid_a
, nid_b_neg
);
252 int sid_bit
= get_bv_sid(1);
253 int nid_zero
= get_sig_nid(Const(0, width
));
254 int nid_b_ltz
= next_nid
++;
255 btorf("%d slt %d %d %d\n", nid_b_ltz
, sid_bit
, nid_b
, nid_zero
);
258 btorf("%d ite %d %d %d %d%s\n", nid
, sid
, nid_b_ltz
, nid_l
, nid_r
, getinfo(cell
).c_str());
263 btorf("%d %s %d %d %d%s\n", nid
, btor_op
.c_str(), sid
, nid_a
, nid_b
, getinfo(cell
).c_str());
266 SigSpec sig
= sigmap(cell
->getPort(ID::Y
));
268 if (GetSize(sig
) < width
) {
269 int sid
= get_bv_sid(GetSize(sig
));
270 int nid2
= next_nid
++;
271 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, GetSize(sig
)-1);
275 add_nid_sig(nid
, sig
);
279 if (cell
->type
.in(ID($div
), ID($mod
), ID($modfloor
)))
281 bool a_signed
= cell
->hasParam(ID::A_SIGNED
) ? cell
->getParam(ID::A_SIGNED
).as_bool() : false;
282 bool b_signed
= cell
->hasParam(ID::B_SIGNED
) ? cell
->getParam(ID::B_SIGNED
).as_bool() : false;
285 if (cell
->type
== ID($div
)) btor_op
= "div";
286 // "rem" = truncating modulo
287 if (cell
->type
== ID($mod
)) btor_op
= "rem";
288 // "mod" = flooring modulo
289 if (cell
->type
== ID($modfloor
)) {
290 // "umod" doesn't exist because it's the same as "urem"
291 btor_op
= a_signed
|| b_signed
? "mod" : "rem";
293 log_assert(!btor_op
.empty());
295 int width
= GetSize(cell
->getPort(ID::Y
));
296 width
= std::max(width
, GetSize(cell
->getPort(ID::A
)));
297 width
= std::max(width
, GetSize(cell
->getPort(ID::B
)));
299 int nid_a
= get_sig_nid(cell
->getPort(ID::A
), width
, a_signed
);
300 int nid_b
= get_sig_nid(cell
->getPort(ID::B
), width
, b_signed
);
302 int sid
= get_bv_sid(width
);
303 int nid
= next_nid
++;
304 btorf("%d %c%s %d %d %d%s\n", nid
, a_signed
|| b_signed
? 's' : 'u', btor_op
.c_str(), sid
, nid_a
, nid_b
, getinfo(cell
).c_str());
306 SigSpec sig
= sigmap(cell
->getPort(ID::Y
));
308 if (GetSize(sig
) < width
) {
309 int sid
= get_bv_sid(GetSize(sig
));
310 int nid2
= next_nid
++;
311 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, GetSize(sig
)-1);
315 add_nid_sig(nid
, sig
);
319 if (cell
->type
.in(ID($_ANDNOT_
), ID($_ORNOT_
)))
321 int sid
= get_bv_sid(1);
322 int nid_a
= get_sig_nid(cell
->getPort(ID::A
));
323 int nid_b
= get_sig_nid(cell
->getPort(ID::B
));
325 int nid1
= next_nid
++;
326 int nid2
= next_nid
++;
328 if (cell
->type
== ID($_ANDNOT_
)) {
329 btorf("%d not %d %d\n", nid1
, sid
, nid_b
);
330 btorf("%d and %d %d %d%s\n", nid2
, sid
, nid_a
, nid1
, getinfo(cell
).c_str());
333 if (cell
->type
== ID($_ORNOT_
)) {
334 btorf("%d not %d %d\n", nid1
, sid
, nid_b
);
335 btorf("%d or %d %d %d%s\n", nid2
, sid
, nid_a
, nid1
, getinfo(cell
).c_str());
338 SigSpec sig
= sigmap(cell
->getPort(ID::Y
));
339 add_nid_sig(nid2
, sig
);
343 if (cell
->type
.in(ID($_OAI3_
), ID($_AOI3_
)))
345 int sid
= get_bv_sid(1);
346 int nid_a
= get_sig_nid(cell
->getPort(ID::A
));
347 int nid_b
= get_sig_nid(cell
->getPort(ID::B
));
348 int nid_c
= get_sig_nid(cell
->getPort(ID::C
));
350 int nid1
= next_nid
++;
351 int nid2
= next_nid
++;
352 int nid3
= next_nid
++;
354 if (cell
->type
== ID($_OAI3_
)) {
355 btorf("%d or %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
356 btorf("%d and %d %d %d\n", nid2
, sid
, nid1
, nid_c
);
357 btorf("%d not %d %d%s\n", nid3
, sid
, nid2
, getinfo(cell
).c_str());
360 if (cell
->type
== ID($_AOI3_
)) {
361 btorf("%d and %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
362 btorf("%d or %d %d %d\n", nid2
, sid
, nid1
, nid_c
);
363 btorf("%d not %d %d%s\n", nid3
, sid
, nid2
, getinfo(cell
).c_str());
366 SigSpec sig
= sigmap(cell
->getPort(ID::Y
));
367 add_nid_sig(nid3
, sig
);
371 if (cell
->type
.in(ID($_OAI4_
), ID($_AOI4_
)))
373 int sid
= get_bv_sid(1);
374 int nid_a
= get_sig_nid(cell
->getPort(ID::A
));
375 int nid_b
= get_sig_nid(cell
->getPort(ID::B
));
376 int nid_c
= get_sig_nid(cell
->getPort(ID::C
));
377 int nid_d
= get_sig_nid(cell
->getPort(ID::D
));
379 int nid1
= next_nid
++;
380 int nid2
= next_nid
++;
381 int nid3
= next_nid
++;
382 int nid4
= next_nid
++;
384 if (cell
->type
== ID($_OAI4_
)) {
385 btorf("%d or %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
386 btorf("%d or %d %d %d\n", nid2
, sid
, nid_c
, nid_d
);
387 btorf("%d and %d %d %d\n", nid3
, sid
, nid1
, nid2
);
388 btorf("%d not %d %d%s\n", nid4
, sid
, nid3
, getinfo(cell
).c_str());
391 if (cell
->type
== ID($_AOI4_
)) {
392 btorf("%d and %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
393 btorf("%d and %d %d %d\n", nid2
, sid
, nid_c
, nid_d
);
394 btorf("%d or %d %d %d\n", nid3
, sid
, nid1
, nid2
);
395 btorf("%d not %d %d%s\n", nid4
, sid
, nid3
, getinfo(cell
).c_str());
398 SigSpec sig
= sigmap(cell
->getPort(ID::Y
));
399 add_nid_sig(nid4
, sig
);
403 if (cell
->type
.in(ID($lt
), ID($le
), ID($eq
), ID($eqx
), ID($ne
), ID($nex
), ID($ge
), ID($gt
)))
406 if (cell
->type
== ID($lt
)) btor_op
= "lt";
407 if (cell
->type
== ID($le
)) btor_op
= "lte";
408 if (cell
->type
.in(ID($eq
), ID($eqx
))) btor_op
= "eq";
409 if (cell
->type
.in(ID($ne
), ID($nex
))) btor_op
= "neq";
410 if (cell
->type
== ID($ge
)) btor_op
= "gte";
411 if (cell
->type
== ID($gt
)) btor_op
= "gt";
412 log_assert(!btor_op
.empty());
415 width
= std::max(width
, GetSize(cell
->getPort(ID::A
)));
416 width
= std::max(width
, GetSize(cell
->getPort(ID::B
)));
418 bool a_signed
= cell
->hasParam(ID::A_SIGNED
) ? cell
->getParam(ID::A_SIGNED
).as_bool() : false;
419 bool b_signed
= cell
->hasParam(ID::B_SIGNED
) ? cell
->getParam(ID::B_SIGNED
).as_bool() : false;
421 int sid
= get_bv_sid(1);
422 int nid_a
= get_sig_nid(cell
->getPort(ID::A
), width
, a_signed
);
423 int nid_b
= get_sig_nid(cell
->getPort(ID::B
), width
, b_signed
);
425 int nid
= next_nid
++;
426 if (cell
->type
.in(ID($lt
), ID($le
), ID($ge
), ID($gt
))) {
427 btorf("%d %c%s %d %d %d%s\n", nid
, a_signed
|| b_signed
? 's' : 'u', btor_op
.c_str(), sid
, nid_a
, nid_b
, getinfo(cell
).c_str());
429 btorf("%d %s %d %d %d%s\n", nid
, btor_op
.c_str(), sid
, nid_a
, nid_b
, getinfo(cell
).c_str());
432 SigSpec sig
= sigmap(cell
->getPort(ID::Y
));
434 if (GetSize(sig
) > 1) {
435 int sid
= get_bv_sid(GetSize(sig
));
436 int nid2
= next_nid
++;
437 btorf("%d uext %d %d %d\n", nid2
, sid
, nid
, GetSize(sig
) - 1);
441 add_nid_sig(nid
, sig
);
445 if (cell
->type
.in(ID($
not), ID($neg
), ID($_NOT_
)))
448 if (cell
->type
.in(ID($
not), ID($_NOT_
))) btor_op
= "not";
449 if (cell
->type
== ID($neg
)) btor_op
= "neg";
450 log_assert(!btor_op
.empty());
452 int width
= std::max(GetSize(cell
->getPort(ID::A
)), GetSize(cell
->getPort(ID::Y
)));
454 bool a_signed
= cell
->hasParam(ID::A_SIGNED
) ? cell
->getParam(ID::A_SIGNED
).as_bool() : false;
456 int sid
= get_bv_sid(width
);
457 int nid_a
= get_sig_nid(cell
->getPort(ID::A
), width
, a_signed
);
459 int nid
= next_nid
++;
460 btorf("%d %s %d %d%s\n", nid
, btor_op
.c_str(), sid
, nid_a
, getinfo(cell
).c_str());
462 SigSpec sig
= sigmap(cell
->getPort(ID::Y
));
464 if (GetSize(sig
) < width
) {
465 int sid
= get_bv_sid(GetSize(sig
));
466 int nid2
= next_nid
++;
467 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, GetSize(sig
)-1);
471 add_nid_sig(nid
, sig
);
475 if (cell
->type
.in(ID($logic_and
), ID($logic_or
), ID($logic_not
)))
478 if (cell
->type
== ID($logic_and
)) btor_op
= "and";
479 if (cell
->type
== ID($logic_or
)) btor_op
= "or";
480 if (cell
->type
== ID($logic_not
)) btor_op
= "not";
481 log_assert(!btor_op
.empty());
483 int sid
= get_bv_sid(1);
484 int nid_a
= get_sig_nid(cell
->getPort(ID::A
));
485 int nid_b
= btor_op
!= "not" ? get_sig_nid(cell
->getPort(ID::B
)) : 0;
487 if (GetSize(cell
->getPort(ID::A
)) > 1) {
488 int nid_red_a
= next_nid
++;
489 btorf("%d redor %d %d\n", nid_red_a
, sid
, nid_a
);
493 if (btor_op
!= "not" && GetSize(cell
->getPort(ID::B
)) > 1) {
494 int nid_red_b
= next_nid
++;
495 btorf("%d redor %d %d\n", nid_red_b
, sid
, nid_b
);
499 int nid
= next_nid
++;
500 if (btor_op
!= "not")
501 btorf("%d %s %d %d %d%s\n", nid
, btor_op
.c_str(), sid
, nid_a
, nid_b
, getinfo(cell
).c_str());
503 btorf("%d %s %d %d%s\n", nid
, btor_op
.c_str(), sid
, nid_a
, getinfo(cell
).c_str());
505 SigSpec sig
= sigmap(cell
->getPort(ID::Y
));
507 if (GetSize(sig
) > 1) {
508 int sid
= get_bv_sid(GetSize(sig
));
509 int zeros_nid
= get_sig_nid(Const(0, GetSize(sig
)-1));
510 int nid2
= next_nid
++;
511 btorf("%d concat %d %d %d\n", nid2
, sid
, zeros_nid
, nid
);
515 add_nid_sig(nid
, sig
);
519 if (cell
->type
.in(ID($reduce_and
), ID($reduce_or
), ID($reduce_bool
), ID($reduce_xor
), ID($reduce_xnor
)))
522 if (cell
->type
== ID($reduce_and
)) btor_op
= "redand";
523 if (cell
->type
.in(ID($reduce_or
), ID($reduce_bool
))) btor_op
= "redor";
524 if (cell
->type
.in(ID($reduce_xor
), ID($reduce_xnor
))) btor_op
= "redxor";
525 log_assert(!btor_op
.empty());
527 int sid
= get_bv_sid(1);
528 int nid_a
= get_sig_nid(cell
->getPort(ID::A
));
530 int nid
= next_nid
++;
532 if (cell
->type
== ID($reduce_xnor
)) {
533 int nid2
= next_nid
++;
534 btorf("%d %s %d %d%s\n", nid
, btor_op
.c_str(), sid
, nid_a
, getinfo(cell
).c_str());
535 btorf("%d not %d %d\n", nid2
, sid
, nid
);
538 btorf("%d %s %d %d%s\n", nid
, btor_op
.c_str(), sid
, nid_a
, getinfo(cell
).c_str());
541 SigSpec sig
= sigmap(cell
->getPort(ID::Y
));
543 if (GetSize(sig
) > 1) {
544 int sid
= get_bv_sid(GetSize(sig
));
545 int zeros_nid
= get_sig_nid(Const(0, GetSize(sig
)-1));
546 int nid2
= next_nid
++;
547 btorf("%d concat %d %d %d\n", nid2
, sid
, zeros_nid
, nid
);
551 add_nid_sig(nid
, sig
);
555 if (cell
->type
.in(ID($mux
), ID($_MUX_
), ID($_NMUX_
)))
557 SigSpec sig_a
= sigmap(cell
->getPort(ID::A
));
558 SigSpec sig_b
= sigmap(cell
->getPort(ID::B
));
559 SigSpec sig_s
= sigmap(cell
->getPort(ID::S
));
560 SigSpec sig_y
= sigmap(cell
->getPort(ID::Y
));
562 int nid_a
= get_sig_nid(sig_a
);
563 int nid_b
= get_sig_nid(sig_b
);
564 int nid_s
= get_sig_nid(sig_s
);
566 int sid
= get_bv_sid(GetSize(sig_y
));
567 int nid
= next_nid
++;
569 if (cell
->type
== ID($_NMUX_
)) {
572 btorf("%d ite %d %d %d %d\n", tmp
, sid
, nid_s
, nid_b
, nid_a
);
573 btorf("%d not %d %d%s\n", nid
, sid
, tmp
, getinfo(cell
).c_str());
575 btorf("%d ite %d %d %d %d%s\n", nid
, sid
, nid_s
, nid_b
, nid_a
, getinfo(cell
).c_str());
578 add_nid_sig(nid
, sig_y
);
582 if (cell
->type
== ID($pmux
))
584 SigSpec sig_a
= sigmap(cell
->getPort(ID::A
));
585 SigSpec sig_b
= sigmap(cell
->getPort(ID::B
));
586 SigSpec sig_s
= sigmap(cell
->getPort(ID::S
));
587 SigSpec sig_y
= sigmap(cell
->getPort(ID::Y
));
589 int width
= GetSize(sig_a
);
590 int sid
= get_bv_sid(width
);
591 int nid
= get_sig_nid(sig_a
);
593 for (int i
= 0; i
< GetSize(sig_s
); i
++) {
594 int nid_b
= get_sig_nid(sig_b
.extract(i
*width
, width
));
595 int nid_s
= get_sig_nid(sig_s
.extract(i
));
596 int nid2
= next_nid
++;
597 if (i
== GetSize(sig_s
)-1)
598 btorf("%d ite %d %d %d %d%s\n", nid2
, sid
, nid_s
, nid_b
, nid
, getinfo(cell
).c_str());
600 btorf("%d ite %d %d %d %d\n", nid2
, sid
, nid_s
, nid_b
, nid
);
604 add_nid_sig(nid
, sig_y
);
608 if (cell
->type
.in(ID($dff
), ID($ff
), ID($_DFF_P_
), ID($_DFF_N
), ID($_FF_
)))
610 SigSpec sig_d
= sigmap(cell
->getPort(ID::D
));
611 SigSpec sig_q
= sigmap(cell
->getPort(ID::Q
));
613 if (!info_filename
.empty() && cell
->type
.in(ID($dff
), ID($_DFF_P_
), ID($_DFF_N_
)))
615 SigSpec sig_c
= sigmap(cell
->getPort(cell
->type
== ID($dff
) ? ID::CLK
: ID::C
));
616 int nid
= get_sig_nid(sig_c
);
617 bool negedge
= false;
619 if (cell
->type
== ID($_DFF_N_
))
622 if (cell
->type
== ID($dff
) && !cell
->getParam(ID::CLK_POLARITY
).as_bool())
625 info_clocks
[nid
] |= negedge
? 2 : 1;
630 if (sig_q
.is_wire()) {
631 Wire
*w
= sig_q
.as_wire();
632 if (w
->port_id
== 0) {
633 statewires
.insert(w
);
639 for (int i
= 0; i
< GetSize(sig_q
); i
++)
640 if (initbits
.count(sig_q
[i
]))
641 initval
.bits
.push_back(initbits
.at(sig_q
[i
]) ? State::S1
: State::S0
);
643 initval
.bits
.push_back(State::Sx
);
645 int nid_init_val
= -1;
647 if (!initval
.is_fully_undef())
648 nid_init_val
= get_sig_nid(initval
, -1, false, true);
650 int sid
= get_bv_sid(GetSize(sig_q
));
651 int nid
= next_nid
++;
653 if (symbol
.empty() || (!print_internal_names
&& symbol
[0] == '$'))
654 btorf("%d state %d\n", nid
, sid
);
656 btorf("%d state %d %s\n", nid
, sid
, log_id(symbol
));
658 if (nid_init_val
>= 0) {
659 int nid_init
= next_nid
++;
661 btorf("; initval = %s\n", log_signal(initval
));
662 btorf("%d init %d %d %d\n", nid_init
, sid
, nid
, nid_init_val
);
665 ff_todo
.push_back(make_pair(nid
, cell
));
666 add_nid_sig(nid
, sig_q
);
670 if (cell
->type
.in(ID($anyconst
), ID($anyseq
)))
672 SigSpec sig_y
= sigmap(cell
->getPort(ID::Y
));
674 int sid
= get_bv_sid(GetSize(sig_y
));
675 int nid
= next_nid
++;
677 btorf("%d state %d\n", nid
, sid
);
679 if (cell
->type
== ID($anyconst
)) {
680 int nid2
= next_nid
++;
681 btorf("%d next %d %d %d\n", nid2
, sid
, nid
, nid
);
684 add_nid_sig(nid
, sig_y
);
688 if (cell
->type
== ID($initstate
))
690 SigSpec sig_y
= sigmap(cell
->getPort(ID::Y
));
692 if (initstate_nid
< 0)
694 int sid
= get_bv_sid(1);
695 int one_nid
= get_sig_nid(State::S1
);
696 int zero_nid
= get_sig_nid(State::S0
);
697 initstate_nid
= next_nid
++;
698 btorf("%d state %d\n", initstate_nid
, sid
);
699 btorf("%d init %d %d %d\n", next_nid
++, sid
, initstate_nid
, one_nid
);
700 btorf("%d next %d %d %d\n", next_nid
++, sid
, initstate_nid
, zero_nid
);
703 add_nid_sig(initstate_nid
, sig_y
);
707 if (cell
->type
== ID($mem
))
709 int abits
= cell
->getParam(ID::ABITS
).as_int();
710 int width
= cell
->getParam(ID::WIDTH
).as_int();
711 int nwords
= cell
->getParam(ID::SIZE
).as_int();
712 int rdports
= cell
->getParam(ID::RD_PORTS
).as_int();
713 int wrports
= cell
->getParam(ID::WR_PORTS
).as_int();
715 Const wr_clk_en
= cell
->getParam(ID::WR_CLK_ENABLE
);
716 Const rd_clk_en
= cell
->getParam(ID::RD_CLK_ENABLE
);
718 bool asyncwr
= wr_clk_en
.is_fully_zero();
720 if (!asyncwr
&& !wr_clk_en
.is_fully_ones())
721 log_error("Memory %s.%s has mixed async/sync write ports.\n",
722 log_id(module
), log_id(cell
));
724 if (!rd_clk_en
.is_fully_zero())
725 log_error("Memory %s.%s has sync read ports.\n",
726 log_id(module
), log_id(cell
));
728 SigSpec sig_rd_addr
= sigmap(cell
->getPort(ID::RD_ADDR
));
729 SigSpec sig_rd_data
= sigmap(cell
->getPort(ID::RD_DATA
));
731 SigSpec sig_wr_addr
= sigmap(cell
->getPort(ID::WR_ADDR
));
732 SigSpec sig_wr_data
= sigmap(cell
->getPort(ID::WR_DATA
));
733 SigSpec sig_wr_en
= sigmap(cell
->getPort(ID::WR_EN
));
735 int data_sid
= get_bv_sid(width
);
736 int bool_sid
= get_bv_sid(1);
737 int sid
= get_mem_sid(abits
, width
);
739 Const initdata
= cell
->getParam(ID::INIT
);
740 initdata
.exts(nwords
*width
);
741 int nid_init_val
= -1;
743 if (!initdata
.is_fully_undef())
745 bool constword
= true;
746 Const firstword
= initdata
.extract(0, width
);
748 for (int i
= 1; i
< nwords
; i
++) {
749 Const thisword
= initdata
.extract(i
*width
, width
);
750 if (thisword
!= firstword
) {
759 btorf("; initval = %s\n", log_signal(firstword
));
760 nid_init_val
= get_sig_nid(firstword
, -1, false, true);
764 nid_init_val
= next_nid
++;
765 btorf("%d state %d\n", nid_init_val
, sid
);
767 for (int i
= 0; i
< nwords
; i
++) {
768 Const thisword
= initdata
.extract(i
*width
, width
);
769 if (thisword
.is_fully_undef())
771 Const
thisaddr(i
, abits
);
772 int nid_thisword
= get_sig_nid(thisword
, -1, false, true);
773 int nid_thisaddr
= get_sig_nid(thisaddr
, -1, false, true);
774 int last_nid_init_val
= nid_init_val
;
775 nid_init_val
= next_nid
++;
777 btorf("; initval[%d] = %s\n", i
, log_signal(thisword
));
778 btorf("%d write %d %d %d %d\n", nid_init_val
, sid
, last_nid_init_val
, nid_thisaddr
, nid_thisword
);
784 int nid
= next_nid
++;
787 if (cell
->name
[0] == '$')
788 btorf("%d state %d\n", nid
, sid
);
790 btorf("%d state %d %s\n", nid
, sid
, log_id(cell
));
792 if (nid_init_val
>= 0)
794 int nid_init
= next_nid
++;
795 btorf("%d init %d %d %d\n", nid_init
, sid
, nid
, nid_init_val
);
800 for (int port
= 0; port
< wrports
; port
++)
802 SigSpec wa
= sig_wr_addr
.extract(port
*abits
, abits
);
803 SigSpec wd
= sig_wr_data
.extract(port
*width
, width
);
804 SigSpec we
= sig_wr_en
.extract(port
*width
, width
);
806 int wa_nid
= get_sig_nid(wa
);
807 int wd_nid
= get_sig_nid(wd
);
808 int we_nid
= get_sig_nid(we
);
810 int nid2
= next_nid
++;
811 btorf("%d read %d %d %d\n", nid2
, data_sid
, nid_head
, wa_nid
);
813 int nid3
= next_nid
++;
814 btorf("%d not %d %d\n", nid3
, data_sid
, we_nid
);
816 int nid4
= next_nid
++;
817 btorf("%d and %d %d %d\n", nid4
, data_sid
, nid2
, nid3
);
819 int nid5
= next_nid
++;
820 btorf("%d and %d %d %d\n", nid5
, data_sid
, wd_nid
, we_nid
);
822 int nid6
= next_nid
++;
823 btorf("%d or %d %d %d\n", nid6
, data_sid
, nid5
, nid4
);
825 int nid7
= next_nid
++;
826 btorf("%d write %d %d %d %d\n", nid7
, sid
, nid_head
, wa_nid
, nid6
);
828 int nid8
= next_nid
++;
829 btorf("%d redor %d %d\n", nid8
, bool_sid
, we_nid
);
831 int nid9
= next_nid
++;
832 btorf("%d ite %d %d %d %d\n", nid9
, sid
, nid8
, nid7
, nid_head
);
838 for (int port
= 0; port
< rdports
; port
++)
840 SigSpec ra
= sig_rd_addr
.extract(port
*abits
, abits
);
841 SigSpec rd
= sig_rd_data
.extract(port
*width
, width
);
843 int ra_nid
= get_sig_nid(ra
);
844 int rd_nid
= next_nid
++;
846 btorf("%d read %d %d %d\n", rd_nid
, data_sid
, nid_head
, ra_nid
);
848 add_nid_sig(rd_nid
, rd
);
853 ff_todo
.push_back(make_pair(nid
, cell
));
857 int nid2
= next_nid
++;
858 btorf("%d next %d %d %d\n", nid2
, sid
, nid
, nid_head
);
864 log_error("Unsupported cell type: %s (%s)\n", log_id(cell
->type
), log_id(cell
));
867 btorf_pop(log_id(cell
));
868 cell_recursion_guard
.erase(cell
);
871 int get_sig_nid(SigSpec sig
, int to_width
= -1, bool is_signed
= false, bool is_init
= false)
877 if (bit
== State::Sx
)
883 SigSpec sig_mask_undef
, sig_noundef
;
884 int first_undef
= -1;
886 for (int i
= 0; i
< GetSize(sig
); i
++)
887 if (sig
[i
] == State::Sx
) {
890 sig_mask_undef
.append(State::S1
);
891 sig_noundef
.append(State::S0
);
893 sig_mask_undef
.append(State::S0
);
894 sig_noundef
.append(sig
[i
]);
897 if (to_width
< 0 || first_undef
< to_width
)
899 int sid
= get_bv_sid(GetSize(sig
));
901 int nid_input
= next_nid
++;
903 btorf("%d state %d\n", nid_input
, sid
);
905 btorf("%d input %d\n", nid_input
, sid
);
907 int nid_masked_input
;
908 if (sig_mask_undef
.is_fully_ones()) {
909 nid_masked_input
= nid_input
;
911 int nid_mask_undef
= get_sig_nid(sig_mask_undef
);
912 nid_masked_input
= next_nid
++;
913 btorf("%d and %d %d %d\n", nid_masked_input
, sid
, nid_input
, nid_mask_undef
);
916 if (sig_noundef
.is_fully_zero()) {
917 nid
= nid_masked_input
;
919 int nid_noundef
= get_sig_nid(sig_noundef
);
921 btorf("%d or %d %d %d\n", nid
, sid
, nid_masked_input
, nid_noundef
);
930 if (sig_nid
.count(sig
) == 0)
933 vector
<pair
<int, int>> nidbits
;
936 for (int i
= 0; i
< GetSize(sig
); i
++)
940 if (bit_nid
.count(bit
) == 0)
942 if (bit
.wire
== nullptr)
946 while (i
+GetSize(c
) < GetSize(sig
) && sig
[i
+GetSize(c
)].wire
== nullptr)
947 c
.bits
.push_back(sig
[i
+GetSize(c
)].data
);
949 if (consts
.count(c
) == 0) {
950 int sid
= get_bv_sid(GetSize(c
));
951 int nid
= next_nid
++;
952 btorf("%d const %d %s\n", nid
, sid
, c
.as_string().c_str());
954 nid_width
[nid
] = GetSize(c
);
957 int nid
= consts
.at(c
);
959 for (int j
= 0; j
< GetSize(c
); j
++)
960 nidbits
.push_back(make_pair(nid
, j
));
967 if (bit_cell
.count(bit
) == 0)
971 while (i
+GetSize(s
) < GetSize(sig
) && sig
[i
+GetSize(s
)].wire
!= nullptr &&
972 bit_cell
.count(sig
[i
+GetSize(s
)]) == 0)
973 s
.append(sig
[i
+GetSize(s
)]);
975 log_warning("No driver for signal %s.\n", log_signal(s
));
977 int sid
= get_bv_sid(GetSize(s
));
978 int nid
= next_nid
++;
979 btorf("%d input %d\n", nid
, sid
);
980 nid_width
[nid
] = GetSize(s
);
982 for (int j
= 0; j
< GetSize(s
); j
++)
983 nidbits
.push_back(make_pair(nid
, j
));
990 export_cell(bit_cell
.at(bit
));
991 log_assert(bit_nid
.count(bit
));
996 nidbits
.push_back(bit_nid
.at(bit
));
1002 // group bits and emit slice-concat chain
1003 for (int i
= 0; i
< GetSize(nidbits
); i
++)
1005 int nid2
= nidbits
[i
].first
;
1006 int lower
= nidbits
[i
].second
;
1009 while (i
+1 < GetSize(nidbits
) && nidbits
[i
+1].first
== nidbits
[i
].first
&&
1010 nidbits
[i
+1].second
== nidbits
[i
].second
+1)
1015 if (lower
!= 0 || upper
+1 != nid_width
.at(nid2
)) {
1016 int sid
= get_bv_sid(upper
-lower
+1);
1018 btorf("%d slice %d %d %d %d\n", nid3
, sid
, nid2
, upper
, lower
);
1024 int sid
= get_bv_sid(width
+upper
-lower
+1);
1026 btorf("%d concat %d %d %d\n", nid4
, sid
, nid3
, nid
);
1029 width
+= upper
-lower
+1;
1034 nid_width
[nid
] = width
;
1037 nid
= sig_nid
.at(sig
);
1040 if (to_width
>= 0 && to_width
!= GetSize(sig
))
1042 if (to_width
< GetSize(sig
))
1044 int sid
= get_bv_sid(to_width
);
1045 int nid2
= next_nid
++;
1046 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, to_width
-1);
1051 int sid
= get_bv_sid(to_width
);
1052 int nid2
= next_nid
++;
1053 btorf("%d %s %d %d %d\n", nid2
, is_signed
? "sext" : "uext",
1054 sid
, nid
, to_width
- GetSize(sig
));
1062 BtorWorker(std::ostream
&f
, RTLIL::Module
*module
, bool verbose
, bool single_bad
, bool cover_mode
, bool print_internal_names
, string info_filename
) :
1063 f(f
), sigmap(module
), module(module
), verbose(verbose
), single_bad(single_bad
), cover_mode(cover_mode
), print_internal_names(print_internal_names
), info_filename(info_filename
)
1065 if (!info_filename
.empty())
1066 infof("name %s\n", log_id(module
));
1068 btorf_push("inputs");
1070 for (auto wire
: module
->wires())
1072 if (wire
->attributes
.count(ID::init
)) {
1073 Const attrval
= wire
->attributes
.at(ID::init
);
1074 for (int i
= 0; i
< GetSize(wire
) && i
< GetSize(attrval
); i
++)
1075 if (attrval
[i
] == State::S0
|| attrval
[i
] == State::S1
)
1076 initbits
[sigmap(SigBit(wire
, i
))] = (attrval
[i
] == State::S1
);
1079 if (!wire
->port_id
|| !wire
->port_input
)
1082 SigSpec sig
= sigmap(wire
);
1083 int sid
= get_bv_sid(GetSize(sig
));
1084 int nid
= next_nid
++;
1086 btorf("%d input %d%s\n", nid
, sid
, getinfo(wire
).c_str());
1087 add_nid_sig(nid
, sig
);
1090 btorf_pop("inputs");
1092 for (auto cell
: module
->cells())
1093 for (auto &conn
: cell
->connections())
1095 if (!cell
->output(conn
.first
))
1098 for (auto bit
: sigmap(conn
.second
))
1099 bit_cell
[bit
] = cell
;
1102 for (auto wire
: module
->wires())
1104 if (!wire
->port_id
|| !wire
->port_output
)
1107 btorf_push(stringf("output %s", log_id(wire
)));
1109 int nid
= get_sig_nid(wire
);
1110 btorf("%d output %d%s\n", next_nid
++, nid
, getinfo(wire
).c_str());
1112 btorf_pop(stringf("output %s", log_id(wire
)));
1115 for (auto cell
: module
->cells())
1117 if (cell
->type
== ID($assume
))
1119 btorf_push(log_id(cell
));
1121 int sid
= get_bv_sid(1);
1122 int nid_a
= get_sig_nid(cell
->getPort(ID::A
));
1123 int nid_en
= get_sig_nid(cell
->getPort(ID::EN
));
1124 int nid_not_en
= next_nid
++;
1125 int nid_a_or_not_en
= next_nid
++;
1126 int nid
= next_nid
++;
1128 btorf("%d not %d %d\n", nid_not_en
, sid
, nid_en
);
1129 btorf("%d or %d %d %d\n", nid_a_or_not_en
, sid
, nid_a
, nid_not_en
);
1130 btorf("%d constraint %d\n", nid
, nid_a_or_not_en
);
1132 btorf_pop(log_id(cell
));
1135 if (cell
->type
== ID($
assert))
1137 btorf_push(log_id(cell
));
1139 int sid
= get_bv_sid(1);
1140 int nid_a
= get_sig_nid(cell
->getPort(ID::A
));
1141 int nid_en
= get_sig_nid(cell
->getPort(ID::EN
));
1142 int nid_not_a
= next_nid
++;
1143 int nid_en_and_not_a
= next_nid
++;
1145 btorf("%d not %d %d\n", nid_not_a
, sid
, nid_a
);
1146 btorf("%d and %d %d %d\n", nid_en_and_not_a
, sid
, nid_en
, nid_not_a
);
1148 if (single_bad
&& !cover_mode
) {
1149 bad_properties
.push_back(nid_en_and_not_a
);
1152 infof("bad %d%s\n", nid_en_and_not_a
, getinfo(cell
, true).c_str());
1154 int nid
= next_nid
++;
1155 btorf("%d bad %d%s\n", nid
, nid_en_and_not_a
, getinfo(cell
, true).c_str());
1159 btorf_pop(log_id(cell
));
1162 if (cell
->type
== ID($cover
) && cover_mode
)
1164 btorf_push(log_id(cell
));
1166 int sid
= get_bv_sid(1);
1167 int nid_a
= get_sig_nid(cell
->getPort(ID::A
));
1168 int nid_en
= get_sig_nid(cell
->getPort(ID::EN
));
1169 int nid_en_and_a
= next_nid
++;
1171 btorf("%d and %d %d %d\n", nid_en_and_a
, sid
, nid_en
, nid_a
);
1174 bad_properties
.push_back(nid_en_and_a
);
1176 int nid
= next_nid
++;
1177 btorf("%d bad %d%s\n", nid
, nid_en_and_a
, getinfo(cell
, true).c_str());
1180 btorf_pop(log_id(cell
));
1184 for (auto wire
: module
->wires())
1186 if (wire
->port_id
|| wire
->name
[0] == '$')
1189 btorf_push(stringf("wire %s", log_id(wire
)));
1191 int sid
= get_bv_sid(GetSize(wire
));
1192 int nid
= get_sig_nid(sigmap(wire
));
1194 if (statewires
.count(wire
))
1197 int this_nid
= next_nid
++;
1198 btorf("%d uext %d %d %d%s\n", this_nid
, sid
, nid
, 0, getinfo(wire
).c_str());
1200 btorf_pop(stringf("wire %s", log_id(wire
)));
1204 while (!ff_todo
.empty())
1206 vector
<pair
<int, Cell
*>> todo
;
1209 for (auto &it
: todo
)
1212 Cell
*cell
= it
.second
;
1214 btorf_push(stringf("next %s", log_id(cell
)));
1216 if (cell
->type
== ID($mem
))
1218 int abits
= cell
->getParam(ID::ABITS
).as_int();
1219 int width
= cell
->getParam(ID::WIDTH
).as_int();
1220 int wrports
= cell
->getParam(ID::WR_PORTS
).as_int();
1222 SigSpec sig_wr_addr
= sigmap(cell
->getPort(ID::WR_ADDR
));
1223 SigSpec sig_wr_data
= sigmap(cell
->getPort(ID::WR_DATA
));
1224 SigSpec sig_wr_en
= sigmap(cell
->getPort(ID::WR_EN
));
1226 int data_sid
= get_bv_sid(width
);
1227 int bool_sid
= get_bv_sid(1);
1228 int sid
= get_mem_sid(abits
, width
);
1231 for (int port
= 0; port
< wrports
; port
++)
1233 SigSpec wa
= sig_wr_addr
.extract(port
*abits
, abits
);
1234 SigSpec wd
= sig_wr_data
.extract(port
*width
, width
);
1235 SigSpec we
= sig_wr_en
.extract(port
*width
, width
);
1237 int wa_nid
= get_sig_nid(wa
);
1238 int wd_nid
= get_sig_nid(wd
);
1239 int we_nid
= get_sig_nid(we
);
1241 int nid2
= next_nid
++;
1242 btorf("%d read %d %d %d\n", nid2
, data_sid
, nid_head
, wa_nid
);
1244 int nid3
= next_nid
++;
1245 btorf("%d not %d %d\n", nid3
, data_sid
, we_nid
);
1247 int nid4
= next_nid
++;
1248 btorf("%d and %d %d %d\n", nid4
, data_sid
, nid2
, nid3
);
1250 int nid5
= next_nid
++;
1251 btorf("%d and %d %d %d\n", nid5
, data_sid
, wd_nid
, we_nid
);
1253 int nid6
= next_nid
++;
1254 btorf("%d or %d %d %d\n", nid6
, data_sid
, nid5
, nid4
);
1256 int nid7
= next_nid
++;
1257 btorf("%d write %d %d %d %d\n", nid7
, sid
, nid_head
, wa_nid
, nid6
);
1259 int nid8
= next_nid
++;
1260 btorf("%d redor %d %d\n", nid8
, bool_sid
, we_nid
);
1262 int nid9
= next_nid
++;
1263 btorf("%d ite %d %d %d %d\n", nid9
, sid
, nid8
, nid7
, nid_head
);
1268 int nid2
= next_nid
++;
1269 btorf("%d next %d %d %d%s\n", nid2
, sid
, nid
, nid_head
, getinfo(cell
).c_str());
1273 SigSpec sig
= sigmap(cell
->getPort(ID::D
));
1274 int nid_q
= get_sig_nid(sig
);
1275 int sid
= get_bv_sid(GetSize(sig
));
1276 btorf("%d next %d %d %d%s\n", next_nid
++, sid
, nid
, nid_q
, getinfo(cell
).c_str());
1279 btorf_pop(stringf("next %s", log_id(cell
)));
1283 while (!bad_properties
.empty())
1286 bad_properties
.swap(todo
);
1288 int sid
= get_bv_sid(1);
1291 while (cursor
+1 < GetSize(todo
))
1293 int nid_a
= todo
[cursor
++];
1294 int nid_b
= todo
[cursor
++];
1295 int nid
= next_nid
++;
1297 bad_properties
.push_back(nid
);
1298 btorf("%d or %d %d %d\n", nid
, sid
, nid_a
, nid_b
);
1301 if (!bad_properties
.empty()) {
1302 if (cursor
< GetSize(todo
))
1303 bad_properties
.push_back(todo
[cursor
++]);
1304 log_assert(cursor
== GetSize(todo
));
1306 int nid
= next_nid
++;
1307 log_assert(cursor
== 0);
1308 log_assert(GetSize(todo
) == 1);
1309 btorf("%d bad %d\n", nid
, todo
[cursor
]);
1313 if (!info_filename
.empty())
1315 for (auto &it
: info_clocks
)
1320 infof("posedge %d\n", it
.first
);
1323 infof("negedge %d\n", it
.first
);
1326 infof("event %d\n", it
.first
);
1334 f
.open(info_filename
.c_str(), std::ofstream::trunc
);
1336 log_error("Can't open file `%s' for writing: %s\n", info_filename
.c_str(), strerror(errno
));
1337 for (auto &it
: info_lines
)
1344 struct BtorBackend
: public Backend
{
1345 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1346 void help() override
1348 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1350 log(" write_btor [options] [filename]\n");
1352 log("Write a BTOR description of the current design.\n");
1355 log(" Add comments and indentation to BTOR output file\n");
1358 log(" Output only a single bad property for all asserts\n");
1361 log(" Output cover properties using 'bad' statements instead of asserts\n");
1363 log(" -i <filename>\n");
1364 log(" Create additional info file with auxiliary information\n");
1367 log(" Output symbols for internal netnames (starting with '$')\n");
1370 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) override
1372 bool verbose
= false, single_bad
= false, cover_mode
= false, print_internal_names
= false;
1373 string info_filename
;
1375 log_header(design
, "Executing BTOR backend.\n");
1378 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1380 if (args
[argidx
] == "-v") {
1384 if (args
[argidx
] == "-s") {
1388 if (args
[argidx
] == "-c") {
1392 if (args
[argidx
] == "-i" && argidx
+1 < args
.size()) {
1393 info_filename
= args
[++argidx
];
1396 if (args
[argidx
] == "-x") {
1397 print_internal_names
= true;
1402 extra_args(f
, filename
, args
, argidx
);
1404 RTLIL::Module
*topmod
= design
->top_module();
1406 if (topmod
== nullptr)
1407 log_cmd_error("No top module found.\n");
1409 *f
<< stringf("; BTOR description generated by %s for module %s.\n",
1410 yosys_version_str
, log_id(topmod
));
1412 BtorWorker(*f
, topmod
, verbose
, single_bad
, cover_mode
, print_internal_names
, info_filename
);
1414 *f
<< stringf("; end of yosys output\n");
1418 PRIVATE_NAMESPACE_END