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Merge pull request #752 from Icenowy/anlogic-lut-cost
[yosys.git] / backends / btor / btor.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
25 #include <string>
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
30 struct BtorWorker
31 {
32 std::ostream &f;
33 SigMap sigmap;
34 RTLIL::Module *module;
35 bool verbose;
36 bool single_bad;
37
38 int next_nid = 1;
39 int initstate_nid = -1;
40
41 // <width> => <sid>
42 dict<int, int> sorts_bv;
43
44 // (<address-width>, <data-width>) => <sid>
45 dict<pair<int, int>, int> sorts_mem;
46
47 // SigBit => (<nid>, <bitidx>)
48 dict<SigBit, pair<int, int>> bit_nid;
49
50 // <nid> => <bvwidth>
51 dict<int, int> nid_width;
52
53 // SigSpec => <nid>
54 dict<SigSpec, int> sig_nid;
55
56 // bit to driving cell
57 dict<SigBit, Cell*> bit_cell;
58
59 // nids for constants
60 dict<Const, int> consts;
61
62 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
63 vector<pair<int, Cell*>> ff_todo;
64
65 pool<Cell*> cell_recursion_guard;
66 vector<int> bad_properties;
67 dict<SigBit, bool> initbits;
68 pool<Wire*> statewires;
69 string indent;
70
71 void btorf(const char *fmt, ...)
72 {
73 va_list ap;
74 va_start(ap, fmt);
75 f << indent << vstringf(fmt, ap);
76 va_end(ap);
77 }
78
79 void btorf_push(const string &id)
80 {
81 if (verbose) {
82 f << indent << stringf(" ; begin %s\n", id.c_str());
83 indent += " ";
84 }
85 }
86
87 void btorf_pop(const string &id)
88 {
89 if (verbose) {
90 indent = indent.substr(4);
91 f << indent << stringf(" ; end %s\n", id.c_str());
92 }
93 }
94
95 int get_bv_sid(int width)
96 {
97 if (sorts_bv.count(width) == 0) {
98 int nid = next_nid++;
99 btorf("%d sort bitvec %d\n", nid, width);
100 sorts_bv[width] = nid;
101 }
102 return sorts_bv.at(width);
103 }
104
105 int get_mem_sid(int abits, int dbits)
106 {
107 pair<int, int> key(abits, dbits);
108 if (sorts_mem.count(key) == 0) {
109 int addr_sid = get_bv_sid(abits);
110 int data_sid = get_bv_sid(dbits);
111 int nid = next_nid++;
112 btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
113 sorts_mem[key] = nid;
114 }
115 return sorts_mem.at(key);
116 }
117
118 void add_nid_sig(int nid, const SigSpec &sig)
119 {
120 if (verbose)
121 f << indent << stringf("; %d %s\n", nid, log_signal(sig));
122
123 for (int i = 0; i < GetSize(sig); i++)
124 bit_nid[sig[i]] = make_pair(nid, i);
125
126 sig_nid[sig] = nid;
127 nid_width[nid] = GetSize(sig);
128 }
129
130 void export_cell(Cell *cell)
131 {
132 log_assert(cell_recursion_guard.count(cell) == 0);
133 cell_recursion_guard.insert(cell);
134 btorf_push(log_id(cell));
135
136 if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
137 "$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
138 {
139 string btor_op;
140 if (cell->type == "$add") btor_op = "add";
141 if (cell->type == "$sub") btor_op = "sub";
142 if (cell->type == "$mul") btor_op = "mul";
143 if (cell->type.in("$shl", "$sshl")) btor_op = "sll";
144 if (cell->type == "$shr") btor_op = "srl";
145 if (cell->type == "$sshr") btor_op = "sra";
146 if (cell->type.in("$shift", "$shiftx")) btor_op = "shift";
147 if (cell->type.in("$and", "$_AND_")) btor_op = "and";
148 if (cell->type.in("$or", "$_OR_")) btor_op = "or";
149 if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor";
150 if (cell->type == "$concat") btor_op = "concat";
151 if (cell->type == "$_NAND_") btor_op = "nand";
152 if (cell->type == "$_NOR_") btor_op = "nor";
153 if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
154 log_assert(!btor_op.empty());
155
156 int width = GetSize(cell->getPort("\\Y"));
157 width = std::max(width, GetSize(cell->getPort("\\A")));
158 width = std::max(width, GetSize(cell->getPort("\\B")));
159
160 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
161 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
162
163 if (btor_op == "shift" && !b_signed)
164 btor_op = "srl";
165
166 if (cell->type.in("$shl", "$sshl", "$shr", "$sshr"))
167 b_signed = false;
168
169 if (cell->type == "$sshr" && !a_signed)
170 btor_op = "srl";
171
172 int sid = get_bv_sid(width);
173 int nid;
174
175 if (btor_op == "shift")
176 {
177 int nid_a = get_sig_nid(cell->getPort("\\A"), width, false);
178 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
179
180 int nid_r = next_nid++;
181 btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);
182
183 int nid_b_neg = next_nid++;
184 btorf("%d neg %d %d\n", nid_b_neg, sid, nid_b);
185
186 int nid_l = next_nid++;
187 btorf("%d sll %d %d %d\n", nid_l, sid, nid_a, nid_b_neg);
188
189 int sid_bit = get_bv_sid(1);
190 int nid_zero = get_sig_nid(Const(0, width));
191 int nid_b_ltz = next_nid++;
192 btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
193
194 nid = next_nid++;
195 btorf("%d ite %d %d %d %d\n", nid, sid, nid_b_ltz, nid_l, nid_r);
196 }
197 else
198 {
199 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
200 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
201
202 nid = next_nid++;
203 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
204 }
205
206 SigSpec sig = sigmap(cell->getPort("\\Y"));
207
208 if (GetSize(sig) < width) {
209 int sid = get_bv_sid(GetSize(sig));
210 int nid2 = next_nid++;
211 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
212 nid = nid2;
213 }
214
215 add_nid_sig(nid, sig);
216 goto okay;
217 }
218
219 if (cell->type.in("$div", "$mod"))
220 {
221 string btor_op;
222 if (cell->type == "$div") btor_op = "div";
223 if (cell->type == "$mod") btor_op = "rem";
224 log_assert(!btor_op.empty());
225
226 int width = GetSize(cell->getPort("\\Y"));
227 width = std::max(width, GetSize(cell->getPort("\\A")));
228 width = std::max(width, GetSize(cell->getPort("\\B")));
229
230 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
231 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
232
233 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
234 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
235
236 int sid = get_bv_sid(width);
237 int nid = next_nid++;
238 btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);
239
240 SigSpec sig = sigmap(cell->getPort("\\Y"));
241
242 if (GetSize(sig) < width) {
243 int sid = get_bv_sid(GetSize(sig));
244 int nid2 = next_nid++;
245 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
246 nid = nid2;
247 }
248
249 add_nid_sig(nid, sig);
250 goto okay;
251 }
252
253 if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
254 {
255 int sid = get_bv_sid(1);
256 int nid_a = get_sig_nid(cell->getPort("\\A"));
257 int nid_b = get_sig_nid(cell->getPort("\\B"));
258
259 int nid1 = next_nid++;
260 int nid2 = next_nid++;
261
262 if (cell->type == "$_ANDNOT_") {
263 btorf("%d not %d %d\n", nid1, sid, nid_b);
264 btorf("%d and %d %d %d\n", nid2, sid, nid_a, nid1);
265 }
266
267 if (cell->type == "$_ORNOT_") {
268 btorf("%d not %d %d\n", nid1, sid, nid_b);
269 btorf("%d or %d %d %d\n", nid2, sid, nid_a, nid1);
270 }
271
272 SigSpec sig = sigmap(cell->getPort("\\Y"));
273 add_nid_sig(nid2, sig);
274 goto okay;
275 }
276
277 if (cell->type.in("$_OAI3_", "$_AOI3_"))
278 {
279 int sid = get_bv_sid(1);
280 int nid_a = get_sig_nid(cell->getPort("\\A"));
281 int nid_b = get_sig_nid(cell->getPort("\\B"));
282 int nid_c = get_sig_nid(cell->getPort("\\C"));
283
284 int nid1 = next_nid++;
285 int nid2 = next_nid++;
286 int nid3 = next_nid++;
287
288 if (cell->type == "$_OAI3_") {
289 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
290 btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
291 btorf("%d not %d %d\n", nid3, sid, nid2);
292 }
293
294 if (cell->type == "$_AOI3_") {
295 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
296 btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
297 btorf("%d not %d %d\n", nid3, sid, nid2);
298 }
299
300 SigSpec sig = sigmap(cell->getPort("\\Y"));
301 add_nid_sig(nid3, sig);
302 goto okay;
303 }
304
305 if (cell->type.in("$_OAI4_", "$_AOI4_"))
306 {
307 int sid = get_bv_sid(1);
308 int nid_a = get_sig_nid(cell->getPort("\\A"));
309 int nid_b = get_sig_nid(cell->getPort("\\B"));
310 int nid_c = get_sig_nid(cell->getPort("\\C"));
311 int nid_d = get_sig_nid(cell->getPort("\\D"));
312
313 int nid1 = next_nid++;
314 int nid2 = next_nid++;
315 int nid3 = next_nid++;
316 int nid4 = next_nid++;
317
318 if (cell->type == "$_OAI4_") {
319 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
320 btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
321 btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
322 btorf("%d not %d %d\n", nid4, sid, nid3);
323 }
324
325 if (cell->type == "$_AOI4_") {
326 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
327 btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
328 btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
329 btorf("%d not %d %d\n", nid4, sid, nid3);
330 }
331
332 SigSpec sig = sigmap(cell->getPort("\\Y"));
333 add_nid_sig(nid4, sig);
334 goto okay;
335 }
336
337 if (cell->type.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt"))
338 {
339 string btor_op;
340 if (cell->type == "$lt") btor_op = "lt";
341 if (cell->type == "$le") btor_op = "lte";
342 if (cell->type.in("$eq", "$eqx")) btor_op = "eq";
343 if (cell->type.in("$ne", "$nex")) btor_op = "ne";
344 if (cell->type == "$ge") btor_op = "gte";
345 if (cell->type == "$gt") btor_op = "gt";
346 log_assert(!btor_op.empty());
347
348 int width = 1;
349 width = std::max(width, GetSize(cell->getPort("\\A")));
350 width = std::max(width, GetSize(cell->getPort("\\B")));
351
352 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
353 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
354
355 int sid = get_bv_sid(1);
356 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
357 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
358
359 int nid = next_nid++;
360 if (cell->type.in("$lt", "$le", "$ge", "$gt")) {
361 btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);
362 } else {
363 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
364 }
365
366 SigSpec sig = sigmap(cell->getPort("\\Y"));
367
368 if (GetSize(sig) > 1) {
369 int sid = get_bv_sid(GetSize(sig));
370 int nid2 = next_nid++;
371 btorf("%d uext %d %d %d\n", nid2, sid, nid, GetSize(sig) - 1);
372 nid = nid2;
373 }
374
375 add_nid_sig(nid, sig);
376 goto okay;
377 }
378
379 if (cell->type.in("$not", "$neg", "$_NOT_"))
380 {
381 string btor_op;
382 if (cell->type.in("$not", "$_NOT_")) btor_op = "not";
383 if (cell->type == "$neg") btor_op = "neg";
384 log_assert(!btor_op.empty());
385
386 int width = GetSize(cell->getPort("\\Y"));
387 width = std::max(width, GetSize(cell->getPort("\\A")));
388
389 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
390
391 int sid = get_bv_sid(width);
392 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
393
394 int nid = next_nid++;
395 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
396
397 SigSpec sig = sigmap(cell->getPort("\\Y"));
398
399 if (GetSize(sig) < width) {
400 int sid = get_bv_sid(GetSize(sig));
401 int nid2 = next_nid++;
402 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
403 nid = nid2;
404 }
405
406 add_nid_sig(nid, sig);
407 goto okay;
408 }
409
410 if (cell->type.in("$logic_and", "$logic_or", "$logic_not"))
411 {
412 string btor_op;
413 if (cell->type == "$logic_and") btor_op = "and";
414 if (cell->type == "$logic_or") btor_op = "or";
415 if (cell->type == "$logic_not") btor_op = "not";
416 log_assert(!btor_op.empty());
417
418 int sid = get_bv_sid(1);
419 int nid_a = get_sig_nid(cell->getPort("\\A"));
420 int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort("\\B")) : 0;
421
422 if (GetSize(cell->getPort("\\A")) > 1) {
423 int nid_red_a = next_nid++;
424 btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
425 nid_a = nid_red_a;
426 }
427
428 if (btor_op != "not" && GetSize(cell->getPort("\\B")) > 1) {
429 int nid_red_b = next_nid++;
430 btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
431 nid_b = nid_red_b;
432 }
433
434 int nid = next_nid++;
435 if (btor_op != "not")
436 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
437 else
438 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
439
440 SigSpec sig = sigmap(cell->getPort("\\Y"));
441
442 if (GetSize(sig) > 1) {
443 int sid = get_bv_sid(GetSize(sig));
444 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
445 int nid2 = next_nid++;
446 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
447 nid = nid2;
448 }
449
450 add_nid_sig(nid, sig);
451 goto okay;
452 }
453
454 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor"))
455 {
456 string btor_op;
457 if (cell->type == "$reduce_and") btor_op = "redand";
458 if (cell->type.in("$reduce_or", "$reduce_bool")) btor_op = "redor";
459 if (cell->type.in("$reduce_xor", "$reduce_xnor")) btor_op = "redxor";
460 log_assert(!btor_op.empty());
461
462 int sid = get_bv_sid(1);
463 int nid_a = get_sig_nid(cell->getPort("\\A"));
464
465 int nid = next_nid++;
466 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
467
468 if (cell->type == "$reduce_xnor") {
469 int nid2 = next_nid++;
470 btorf("%d not %d %d %d\n", nid2, sid, nid);
471 nid = nid2;
472 }
473
474 SigSpec sig = sigmap(cell->getPort("\\Y"));
475
476 if (GetSize(sig) > 1) {
477 int sid = get_bv_sid(GetSize(sig));
478 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
479 int nid2 = next_nid++;
480 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
481 nid = nid2;
482 }
483
484 add_nid_sig(nid, sig);
485 goto okay;
486 }
487
488 if (cell->type.in("$mux", "$_MUX_"))
489 {
490 SigSpec sig_a = sigmap(cell->getPort("\\A"));
491 SigSpec sig_b = sigmap(cell->getPort("\\B"));
492 SigSpec sig_s = sigmap(cell->getPort("\\S"));
493 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
494
495 int nid_a = get_sig_nid(sig_a);
496 int nid_b = get_sig_nid(sig_b);
497 int nid_s = get_sig_nid(sig_s);
498
499 int sid = get_bv_sid(GetSize(sig_y));
500 int nid = next_nid++;
501 btorf("%d ite %d %d %d %d\n", nid, sid, nid_s, nid_b, nid_a);
502
503 add_nid_sig(nid, sig_y);
504 goto okay;
505 }
506
507 if (cell->type == "$pmux")
508 {
509 SigSpec sig_a = sigmap(cell->getPort("\\A"));
510 SigSpec sig_b = sigmap(cell->getPort("\\B"));
511 SigSpec sig_s = sigmap(cell->getPort("\\S"));
512 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
513
514 int width = GetSize(sig_a);
515 int sid = get_bv_sid(width);
516 int nid = get_sig_nid(sig_a);
517
518 for (int i = 0; i < GetSize(sig_s); i++) {
519 int nid_b = get_sig_nid(sig_b.extract(i*width, width));
520 int nid_s = get_sig_nid(sig_s.extract(i));
521 int nid2 = next_nid++;
522 btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
523 nid = nid2;
524 }
525
526 add_nid_sig(nid, sig_y);
527 goto okay;
528 }
529
530 if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N", "$_FF_"))
531 {
532 SigSpec sig_d = sigmap(cell->getPort("\\D"));
533 SigSpec sig_q = sigmap(cell->getPort("\\Q"));
534
535 IdString symbol;
536
537 if (sig_q.is_wire()) {
538 Wire *w = sig_q.as_wire();
539 if (w->port_id == 0) {
540 statewires.insert(w);
541 symbol = w->name;
542 }
543 }
544
545 Const initval;
546 for (int i = 0; i < GetSize(sig_q); i++)
547 if (initbits.count(sig_q[i]))
548 initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
549 else
550 initval.bits.push_back(State::Sx);
551
552 int nid_init_val = -1;
553
554 if (!initval.is_fully_undef())
555 nid_init_val = get_sig_nid(initval);
556
557 int sid = get_bv_sid(GetSize(sig_q));
558 int nid = next_nid++;
559
560 if (symbol.empty())
561 btorf("%d state %d\n", nid, sid);
562 else
563 btorf("%d state %d %s\n", nid, sid, log_id(symbol));
564
565 if (nid_init_val >= 0) {
566 int nid_init = next_nid++;
567 if (verbose)
568 btorf("; initval = %s\n", log_signal(initval));
569 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
570 }
571
572 ff_todo.push_back(make_pair(nid, cell));
573 add_nid_sig(nid, sig_q);
574 goto okay;
575 }
576
577 if (cell->type.in("$anyconst", "$anyseq"))
578 {
579 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
580
581 int sid = get_bv_sid(GetSize(sig_y));
582 int nid = next_nid++;
583
584 btorf("%d state %d\n", nid, sid);
585
586 if (cell->type == "$anyconst") {
587 int nid2 = next_nid++;
588 btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
589 }
590
591 add_nid_sig(nid, sig_y);
592 goto okay;
593 }
594
595 if (cell->type == "$initstate")
596 {
597 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
598
599 if (initstate_nid < 0)
600 {
601 int sid = get_bv_sid(1);
602 int one_nid = get_sig_nid(Const(1, 1));
603 int zero_nid = get_sig_nid(Const(0, 1));
604 initstate_nid = next_nid++;
605 btorf("%d state %d\n", initstate_nid, sid);
606 btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
607 btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
608 }
609
610 add_nid_sig(initstate_nid, sig_y);
611 goto okay;
612 }
613
614 if (cell->type == "$mem")
615 {
616 int abits = cell->getParam("\\ABITS").as_int();
617 int width = cell->getParam("\\WIDTH").as_int();
618 int rdports = cell->getParam("\\RD_PORTS").as_int();
619 int wrports = cell->getParam("\\WR_PORTS").as_int();
620
621 Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE");
622 Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE");
623
624 bool asyncwr = wr_clk_en.is_fully_zero();
625
626 if (!asyncwr && !wr_clk_en.is_fully_ones())
627 log_error("Memory %s.%s has mixed async/sync write ports.\n",
628 log_id(module), log_id(cell));
629
630 if (!rd_clk_en.is_fully_zero())
631 log_error("Memory %s.%s has sync read ports.\n",
632 log_id(module), log_id(cell));
633
634 SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR"));
635 SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA"));
636
637 SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
638 SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
639 SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
640
641 int data_sid = get_bv_sid(width);
642 int bool_sid = get_bv_sid(1);
643 int sid = get_mem_sid(abits, width);
644 int nid = next_nid++;
645 int nid_head = nid;
646
647 if (cell->name[0] == '$')
648 btorf("%d state %d\n", nid, sid);
649 else
650 btorf("%d state %d %s\n", nid, sid, log_id(cell));
651
652 if (asyncwr)
653 {
654 for (int port = 0; port < wrports; port++)
655 {
656 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
657 SigSpec wd = sig_wr_data.extract(port*width, width);
658 SigSpec we = sig_wr_en.extract(port*width, width);
659
660 int wa_nid = get_sig_nid(wa);
661 int wd_nid = get_sig_nid(wd);
662 int we_nid = get_sig_nid(we);
663
664 int nid2 = next_nid++;
665 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
666
667 int nid3 = next_nid++;
668 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
669
670 int nid4 = next_nid++;
671 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
672
673 int nid5 = next_nid++;
674 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
675
676 int nid6 = next_nid++;
677 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
678
679 int nid7 = next_nid++;
680 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
681
682 int nid8 = next_nid++;
683 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
684
685 int nid9 = next_nid++;
686 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
687
688 nid_head = nid9;
689 }
690 }
691
692 for (int port = 0; port < rdports; port++)
693 {
694 SigSpec ra = sig_rd_addr.extract(port*abits, abits);
695 SigSpec rd = sig_rd_data.extract(port*width, width);
696
697 int ra_nid = get_sig_nid(ra);
698 int rd_nid = next_nid++;
699
700 btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);
701
702 add_nid_sig(rd_nid, rd);
703 }
704
705 if (!asyncwr)
706 {
707 ff_todo.push_back(make_pair(nid, cell));
708 }
709 else
710 {
711 int nid2 = next_nid++;
712 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
713 }
714
715 goto okay;
716 }
717
718 log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
719
720 okay:
721 btorf_pop(log_id(cell));
722 cell_recursion_guard.erase(cell);
723 }
724
725 int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false)
726 {
727 int nid = -1;
728 sigmap.apply(sig);
729
730 for (auto bit : sig)
731 if (bit == State::Sx)
732 goto has_undef_bits;
733
734 if (0)
735 {
736 has_undef_bits:
737 SigSpec sig_mask_undef, sig_noundef;
738 int first_undef = -1;
739
740 for (int i = 0; i < GetSize(sig); i++)
741 if (sig[i] == State::Sx) {
742 if (first_undef < 0)
743 first_undef = i;
744 sig_mask_undef.append(State::S1);
745 sig_noundef.append(State::S0);
746 } else {
747 sig_mask_undef.append(State::S0);
748 sig_noundef.append(sig[i]);
749 }
750
751 if (to_width < 0 || first_undef < to_width)
752 {
753 int sid = get_bv_sid(GetSize(sig));
754
755 int nid_input = next_nid++;
756 btorf("%d input %d\n", nid_input, sid);
757
758 int nid_masked_input;
759 if (sig_mask_undef.is_fully_ones()) {
760 nid_masked_input = nid_input;
761 } else {
762 int nid_mask_undef = get_sig_nid(sig_mask_undef);
763 nid_masked_input = next_nid++;
764 btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
765 }
766
767 if (sig_noundef.is_fully_zero()) {
768 nid = nid_masked_input;
769 } else {
770 int nid_noundef = get_sig_nid(sig_noundef);
771 nid = next_nid++;
772 btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
773 }
774
775 goto extend_or_trim;
776 }
777
778 sig = sig_noundef;
779 }
780
781 if (sig_nid.count(sig) == 0)
782 {
783 // <nid>, <bitidx>
784 vector<pair<int, int>> nidbits;
785
786 // collect all bits
787 for (int i = 0; i < GetSize(sig); i++)
788 {
789 SigBit bit = sig[i];
790
791 if (bit_nid.count(bit) == 0)
792 {
793 if (bit.wire == nullptr)
794 {
795 Const c(bit.data);
796
797 while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
798 c.bits.push_back(sig[i+GetSize(c)].data);
799
800 if (consts.count(c) == 0) {
801 int sid = get_bv_sid(GetSize(c));
802 int nid = next_nid++;
803 btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
804 consts[c] = nid;
805 nid_width[nid] = GetSize(c);
806 }
807
808 int nid = consts.at(c);
809
810 for (int j = 0; j < GetSize(c); j++)
811 nidbits.push_back(make_pair(nid, j));
812
813 i += GetSize(c)-1;
814 continue;
815 }
816 else
817 {
818 if (bit_cell.count(bit) == 0)
819 log_error("No driver for signal bit %s.\n", log_signal(bit));
820 export_cell(bit_cell.at(bit));
821 log_assert(bit_nid.count(bit));
822 }
823 }
824
825 nidbits.push_back(bit_nid.at(bit));
826 }
827
828 int width = 0;
829 int nid = -1;
830
831 // group bits and emit slice-concat chain
832 for (int i = 0; i < GetSize(nidbits); i++)
833 {
834 int nid2 = nidbits[i].first;
835 int lower = nidbits[i].second;
836 int upper = lower;
837
838 while (i+1 < GetSize(nidbits) && nidbits[i+1].first == nidbits[i].first &&
839 nidbits[i+1].second == nidbits[i].second+1)
840 upper++, i++;
841
842 int nid3 = nid2;
843
844 if (lower != 0 || upper+1 != nid_width.at(nid2)) {
845 int sid = get_bv_sid(upper-lower+1);
846 nid3 = next_nid++;
847 btorf("%d slice %d %d %d %d\n", nid3, sid, nid2, upper, lower);
848 }
849
850 int nid4 = nid3;
851
852 if (nid >= 0) {
853 int sid = get_bv_sid(width+upper-lower+1);
854 nid4 = next_nid++;
855 btorf("%d concat %d %d %d\n", nid4, sid, nid3, nid);
856 }
857
858 width += upper-lower+1;
859 nid = nid4;
860 }
861
862 sig_nid[sig] = nid;
863 nid_width[nid] = width;
864 }
865
866 nid = sig_nid.at(sig);
867
868 extend_or_trim:
869 if (to_width >= 0 && to_width != GetSize(sig))
870 {
871 if (to_width < GetSize(sig))
872 {
873 int sid = get_bv_sid(to_width);
874 int nid2 = next_nid++;
875 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, to_width-1);
876 nid = nid2;
877 }
878 else
879 {
880 int sid = get_bv_sid(to_width);
881 int nid2 = next_nid++;
882 btorf("%d %s %d %d %d\n", nid2, is_signed ? "sext" : "uext",
883 sid, nid, to_width - GetSize(sig));
884 nid = nid2;
885 }
886 }
887
888 return nid;
889 }
890
891 BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad) :
892 f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad)
893 {
894 btorf_push("inputs");
895
896 for (auto wire : module->wires())
897 {
898 if (wire->attributes.count("\\init")) {
899 Const attrval = wire->attributes.at("\\init");
900 for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
901 if (attrval[i] == State::S0 || attrval[i] == State::S1)
902 initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
903 }
904
905 if (!wire->port_id || !wire->port_input)
906 continue;
907
908 SigSpec sig = sigmap(wire);
909 int sid = get_bv_sid(GetSize(sig));
910 int nid = next_nid++;
911
912 btorf("%d input %d %s\n", nid, sid, log_id(wire));
913 add_nid_sig(nid, sig);
914 }
915
916 btorf_pop("inputs");
917
918 for (auto cell : module->cells())
919 for (auto &conn : cell->connections())
920 {
921 if (!cell->output(conn.first))
922 continue;
923
924 for (auto bit : sigmap(conn.second))
925 bit_cell[bit] = cell;
926 }
927
928 for (auto wire : module->wires())
929 {
930 if (!wire->port_id || !wire->port_output)
931 continue;
932
933 btorf_push(stringf("output %s", log_id(wire)));
934
935 int sid = get_bv_sid(GetSize(wire));
936 int nid = get_sig_nid(wire);
937 btorf("%d output %d %d %s\n", next_nid++, sid, nid, log_id(wire));
938
939 btorf_pop(stringf("output %s", log_id(wire)));
940 }
941
942 for (auto cell : module->cells())
943 {
944 if (cell->type == "$assume")
945 {
946 btorf_push(log_id(cell));
947
948 int sid = get_bv_sid(1);
949 int nid_a = get_sig_nid(cell->getPort("\\A"));
950 int nid_en = get_sig_nid(cell->getPort("\\EN"));
951 int nid_not_en = next_nid++;
952 int nid_a_or_not_en = next_nid++;
953 int nid = next_nid++;
954
955 btorf("%d not %d %d\n", nid_not_en, sid, nid_en);
956 btorf("%d or %d %d %d\n", nid_a_or_not_en, sid, nid_a, nid_not_en);
957 btorf("%d constraint %d\n", nid, nid_a_or_not_en);
958
959 btorf_pop(log_id(cell));
960 }
961
962 if (cell->type == "$assert")
963 {
964 btorf_push(log_id(cell));
965
966 int sid = get_bv_sid(1);
967 int nid_a = get_sig_nid(cell->getPort("\\A"));
968 int nid_en = get_sig_nid(cell->getPort("\\EN"));
969 int nid_not_a = next_nid++;
970 int nid_en_and_not_a = next_nid++;
971
972 btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
973 btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);
974
975 if (single_bad) {
976 bad_properties.push_back(nid_en_and_not_a);
977 } else {
978 int nid = next_nid++;
979 btorf("%d bad %d\n", nid, nid_en_and_not_a);
980 }
981
982 btorf_pop(log_id(cell));
983 }
984 }
985
986 for (auto wire : module->wires())
987 {
988 if (wire->port_id || wire->name[0] == '$')
989 continue;
990
991 btorf_push(stringf("wire %s", log_id(wire)));
992
993 int sid = get_bv_sid(GetSize(wire));
994 int nid = get_sig_nid(sigmap(wire));
995
996 if (statewires.count(wire))
997 continue;
998
999 int this_nid = next_nid++;
1000 btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, log_id(wire));
1001
1002 btorf_pop(stringf("wire %s", log_id(wire)));
1003 continue;
1004 }
1005
1006 while (!ff_todo.empty())
1007 {
1008 vector<pair<int, Cell*>> todo;
1009 todo.swap(ff_todo);
1010
1011 for (auto &it : todo)
1012 {
1013 int nid = it.first;
1014 Cell *cell = it.second;
1015
1016 btorf_push(stringf("next %s", log_id(cell)));
1017
1018 if (cell->type == "$mem")
1019 {
1020 int abits = cell->getParam("\\ABITS").as_int();
1021 int width = cell->getParam("\\WIDTH").as_int();
1022 int wrports = cell->getParam("\\WR_PORTS").as_int();
1023
1024 SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
1025 SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
1026 SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
1027
1028 int data_sid = get_bv_sid(width);
1029 int bool_sid = get_bv_sid(1);
1030 int sid = get_mem_sid(abits, width);
1031 int nid_head = nid;
1032
1033 for (int port = 0; port < wrports; port++)
1034 {
1035 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
1036 SigSpec wd = sig_wr_data.extract(port*width, width);
1037 SigSpec we = sig_wr_en.extract(port*width, width);
1038
1039 int wa_nid = get_sig_nid(wa);
1040 int wd_nid = get_sig_nid(wd);
1041 int we_nid = get_sig_nid(we);
1042
1043 int nid2 = next_nid++;
1044 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
1045
1046 int nid3 = next_nid++;
1047 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
1048
1049 int nid4 = next_nid++;
1050 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
1051
1052 int nid5 = next_nid++;
1053 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
1054
1055 int nid6 = next_nid++;
1056 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
1057
1058 int nid7 = next_nid++;
1059 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
1060
1061 int nid8 = next_nid++;
1062 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
1063
1064 int nid9 = next_nid++;
1065 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
1066
1067 nid_head = nid9;
1068 }
1069
1070 int nid2 = next_nid++;
1071 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
1072 }
1073 else
1074 {
1075 SigSpec sig = sigmap(cell->getPort("\\D"));
1076 int nid_q = get_sig_nid(sig);
1077 int sid = get_bv_sid(GetSize(sig));
1078 btorf("%d next %d %d %d\n", next_nid++, sid, nid, nid_q);
1079 }
1080
1081 btorf_pop(stringf("next %s", log_id(cell)));
1082 }
1083 }
1084
1085 while (!bad_properties.empty())
1086 {
1087 vector<int> todo;
1088 bad_properties.swap(todo);
1089
1090 int sid = get_bv_sid(1);
1091 int cursor = 0;
1092
1093 while (cursor+1 < GetSize(todo))
1094 {
1095 int nid_a = todo[cursor++];
1096 int nid_b = todo[cursor++];
1097 int nid = next_nid++;
1098
1099 bad_properties.push_back(nid);
1100 btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
1101 }
1102
1103 if (!bad_properties.empty()) {
1104 if (cursor < GetSize(todo))
1105 bad_properties.push_back(todo[cursor++]);
1106 log_assert(cursor == GetSize(todo));
1107 } else {
1108 int nid = next_nid++;
1109 log_assert(cursor == 0);
1110 log_assert(GetSize(todo) == 1);
1111 btorf("%d bad %d\n", nid, todo[cursor]);
1112 }
1113 }
1114 }
1115 };
1116
1117 struct BtorBackend : public Backend {
1118 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1119 void help() YS_OVERRIDE
1120 {
1121 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1122 log("\n");
1123 log(" write_btor [options] [filename]\n");
1124 log("\n");
1125 log("Write a BTOR description of the current design.\n");
1126 log("\n");
1127 log(" -v\n");
1128 log(" Add comments and indentation to BTOR output file\n");
1129 log("\n");
1130 log(" -s\n");
1131 log(" Output only a single bad property for all asserts\n");
1132 log("\n");
1133 }
1134 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1135 {
1136 bool verbose = false, single_bad = false;
1137
1138 log_header(design, "Executing BTOR backend.\n");
1139
1140 size_t argidx;
1141 for (argidx = 1; argidx < args.size(); argidx++)
1142 {
1143 if (args[argidx] == "-v") {
1144 verbose = true;
1145 continue;
1146 }
1147 if (args[argidx] == "-s") {
1148 single_bad = true;
1149 continue;
1150 }
1151 break;
1152 }
1153 extra_args(f, filename, args, argidx);
1154
1155 RTLIL::Module *topmod = design->top_module();
1156
1157 if (topmod == nullptr)
1158 log_cmd_error("No top module found.\n");
1159
1160 *f << stringf("; BTOR description generated by %s for module %s.\n",
1161 yosys_version_str, log_id(topmod));
1162
1163 BtorWorker(*f, topmod, verbose, single_bad);
1164
1165 *f << stringf("; end of yosys output\n");
1166 }
1167 } BtorBackend;
1168
1169 PRIVATE_NAMESPACE_END