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Add $anyconst/$anyseq support to btor back-end
[yosys.git] / backends / btor / btor.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
25 #include <string>
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
30 struct BtorWorker
31 {
32 std::ostream &f;
33 SigMap sigmap;
34 RTLIL::Module *module;
35 bool verbose;
36 bool single_bad;
37
38 int next_nid = 1;
39 int initstate_nid = -1;
40
41 // <width> => <sid>
42 dict<int, int> sorts_bv;
43
44 // (<address-width>, <data-width>) => <sid>
45 dict<pair<int, int>, int> sorts_mem;
46
47 // SigBit => (<nid>, <bitidx>)
48 dict<SigBit, pair<int, int>> bit_nid;
49
50 // <nid> => <bvwidth>
51 dict<int, int> nid_width;
52
53 // SigSpec => <nid>
54 dict<SigSpec, int> sig_nid;
55
56 // bit to driving cell
57 dict<SigBit, Cell*> bit_cell;
58
59 // nids for constants
60 dict<Const, int> consts;
61
62 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
63 vector<pair<int, Cell*>> ff_todo;
64
65 pool<Cell*> cell_recursion_guard;
66 vector<int> bad_properties;
67 dict<SigBit, bool> initbits;
68 pool<Wire*> statewires;
69 string indent;
70
71 void btorf(const char *fmt, ...)
72 {
73 va_list ap;
74 va_start(ap, fmt);
75 f << indent << vstringf(fmt, ap);
76 va_end(ap);
77 }
78
79 void btorf_push(const string &id)
80 {
81 if (verbose) {
82 f << indent << stringf(" ; begin %s\n", id.c_str());
83 indent += " ";
84 }
85 }
86
87 void btorf_pop(const string &id)
88 {
89 if (verbose) {
90 indent = indent.substr(4);
91 f << indent << stringf(" ; end %s\n", id.c_str());
92 }
93 }
94
95 int get_bv_sid(int width)
96 {
97 if (sorts_bv.count(width) == 0) {
98 int nid = next_nid++;
99 btorf("%d sort bitvec %d\n", nid, width);
100 sorts_bv[width] = nid;
101 }
102 return sorts_bv.at(width);
103 }
104
105 void add_nid_sig(int nid, const SigSpec &sig)
106 {
107 if (verbose)
108 f << indent << stringf("; %d %s\n", nid, log_signal(sig));
109
110 for (int i = 0; i < GetSize(sig); i++)
111 bit_nid[sig[i]] = make_pair(nid, i);
112
113 sig_nid[sig] = nid;
114 nid_width[nid] = GetSize(sig);
115 }
116
117 void export_cell(Cell *cell)
118 {
119 log_assert(cell_recursion_guard.count(cell) == 0);
120 cell_recursion_guard.insert(cell);
121 btorf_push(log_id(cell));
122
123 if (cell->type.in("$add", "$sub", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
124 "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
125 {
126 string btor_op;
127 if (cell->type == "$add") btor_op = "add";
128 if (cell->type == "$sub") btor_op = "sub";
129 if (cell->type.in("$shl", "$sshl")) btor_op = "sll";
130 if (cell->type == "$shr") btor_op = "srl";
131 if (cell->type == "$sshr") btor_op = "sra";
132 if (cell->type.in("$shift", "$shiftx")) btor_op = "shift";
133 if (cell->type.in("$and", "$_AND_")) btor_op = "and";
134 if (cell->type.in("$or", "$_OR_")) btor_op = "or";
135 if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor";
136 if (cell->type == "$_NAND_") btor_op = "nand";
137 if (cell->type == "$_NOR_") btor_op = "nor";
138 if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
139 log_assert(!btor_op.empty());
140
141 int width = GetSize(cell->getPort("\\Y"));
142 width = std::max(width, GetSize(cell->getPort("\\A")));
143 width = std::max(width, GetSize(cell->getPort("\\B")));
144
145 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
146 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
147
148 if (btor_op == "shift" && !b_signed)
149 btor_op = "srl";
150
151 if (cell->type.in("$shl", "$sshl", "$shr", "$sshr"))
152 b_signed = false;
153
154 if (cell->type == "$sshr" && !a_signed)
155 btor_op = "srl";
156
157 int sid = get_bv_sid(width);
158 int nid;
159
160 if (btor_op == "shift")
161 {
162 int nid_a = get_sig_nid(cell->getPort("\\A"), width, false);
163 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
164
165 int nid_r = next_nid++;
166 btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);
167
168 int nid_b_neg = next_nid++;
169 btorf("%d neg %d %d\n", nid_b_neg, sid, nid_b);
170
171 int nid_l = next_nid++;
172 btorf("%d sll %d %d %d\n", nid_l, sid, nid_a, nid_b_neg);
173
174 int sid_bit = get_bv_sid(1);
175 int nid_zero = get_sig_nid(Const(0, width));
176 int nid_b_ltz = next_nid++;
177 btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
178
179 nid = next_nid++;
180 btorf("%d ite %d %d %d %d\n", nid, sid, nid_b_ltz, nid_l, nid_r);
181 }
182 else
183 {
184 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
185 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
186
187 nid = next_nid++;
188 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
189 }
190
191 SigSpec sig = sigmap(cell->getPort("\\Y"));
192
193 if (GetSize(sig) < width) {
194 int sid = get_bv_sid(GetSize(sig));
195 int nid2 = next_nid++;
196 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
197 nid = nid2;
198 }
199
200 add_nid_sig(nid, sig);
201 goto okay;
202 }
203
204 if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
205 {
206 int sid = get_bv_sid(1);
207 int nid_a = get_sig_nid(cell->getPort("\\A"));
208 int nid_b = get_sig_nid(cell->getPort("\\B"));
209
210 int nid1 = next_nid++;
211 int nid2 = next_nid++;
212
213 if (cell->type == "$_ANDNOT_") {
214 btorf("%d not %d %d\n", nid1, sid, nid_b);
215 btorf("%d and %d %d %d\n", nid2, sid, nid_a, nid1);
216 }
217
218 if (cell->type == "$_ORNOT_") {
219 btorf("%d not %d %d\n", nid1, sid, nid_b);
220 btorf("%d or %d %d %d\n", nid2, sid, nid_a, nid1);
221 }
222
223 SigSpec sig = sigmap(cell->getPort("\\Y"));
224 add_nid_sig(nid2, sig);
225 goto okay;
226 }
227
228 if (cell->type.in("$_OAI3_", "$_AOI3_"))
229 {
230 int sid = get_bv_sid(1);
231 int nid_a = get_sig_nid(cell->getPort("\\A"));
232 int nid_b = get_sig_nid(cell->getPort("\\B"));
233 int nid_c = get_sig_nid(cell->getPort("\\C"));
234
235 int nid1 = next_nid++;
236 int nid2 = next_nid++;
237 int nid3 = next_nid++;
238
239 if (cell->type == "$_OAI3_") {
240 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
241 btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
242 btorf("%d not %d %d\n", nid3, sid, nid2);
243 }
244
245 if (cell->type == "$_AOI3_") {
246 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
247 btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
248 btorf("%d not %d %d\n", nid3, sid, nid2);
249 }
250
251 SigSpec sig = sigmap(cell->getPort("\\Y"));
252 add_nid_sig(nid3, sig);
253 goto okay;
254 }
255
256 if (cell->type.in("$_OAI4_", "$_AOI4_"))
257 {
258 int sid = get_bv_sid(1);
259 int nid_a = get_sig_nid(cell->getPort("\\A"));
260 int nid_b = get_sig_nid(cell->getPort("\\B"));
261 int nid_c = get_sig_nid(cell->getPort("\\C"));
262 int nid_d = get_sig_nid(cell->getPort("\\D"));
263
264 int nid1 = next_nid++;
265 int nid2 = next_nid++;
266 int nid3 = next_nid++;
267 int nid4 = next_nid++;
268
269 if (cell->type == "$_OAI4_") {
270 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
271 btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
272 btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
273 btorf("%d not %d %d\n", nid4, sid, nid3);
274 }
275
276 if (cell->type == "$_AOI4_") {
277 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
278 btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
279 btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
280 btorf("%d not %d %d\n", nid4, sid, nid3);
281 }
282
283 SigSpec sig = sigmap(cell->getPort("\\Y"));
284 add_nid_sig(nid4, sig);
285 goto okay;
286 }
287
288 if (cell->type.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt"))
289 {
290 string btor_op;
291 if (cell->type == "$lt") btor_op = "lt";
292 if (cell->type == "$le") btor_op = "lte";
293 if (cell->type.in("$eq", "$eqx")) btor_op = "eq";
294 if (cell->type.in("$ne", "$nex")) btor_op = "ne";
295 if (cell->type == "$ge") btor_op = "gte";
296 if (cell->type == "$gt") btor_op = "gt";
297 log_assert(!btor_op.empty());
298
299 int width = 1;
300 width = std::max(width, GetSize(cell->getPort("\\A")));
301 width = std::max(width, GetSize(cell->getPort("\\B")));
302
303 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
304 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
305
306 int sid = get_bv_sid(1);
307 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
308 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
309
310 int nid = next_nid++;
311 if (cell->type.in("$lt", "$le", "$ge", "$gt")) {
312 btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);
313 } else {
314 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
315 }
316
317 SigSpec sig = sigmap(cell->getPort("\\Y"));
318
319 if (GetSize(sig) > 1) {
320 int sid = get_bv_sid(GetSize(sig));
321 int nid2 = next_nid++;
322 btorf("%d uext %d %d %d\n", nid2, sid, nid, GetSize(sig) - 1);
323 nid = nid2;
324 }
325
326 add_nid_sig(nid, sig);
327 goto okay;
328 }
329
330 if (cell->type.in("$not", "$neg", "$_NOT_"))
331 {
332 string btor_op;
333 if (cell->type.in("$not", "$_NOT_")) btor_op = "not";
334 if (cell->type == "$neg") btor_op = "neg";
335 log_assert(!btor_op.empty());
336
337 int width = GetSize(cell->getPort("\\Y"));
338 width = std::max(width, GetSize(cell->getPort("\\A")));
339
340 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
341
342 int sid = get_bv_sid(width);
343 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
344
345 int nid = next_nid++;
346 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
347
348 SigSpec sig = sigmap(cell->getPort("\\Y"));
349
350 if (GetSize(sig) < width) {
351 int sid = get_bv_sid(GetSize(sig));
352 int nid2 = next_nid++;
353 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
354 nid = nid2;
355 }
356
357 add_nid_sig(nid, sig);
358 goto okay;
359 }
360
361 if (cell->type.in("$logic_and", "$logic_or", "$logic_not"))
362 {
363 string btor_op;
364 if (cell->type == "$logic_and") btor_op = "and";
365 if (cell->type == "$logic_or") btor_op = "or";
366 if (cell->type == "$logic_not") btor_op = "not";
367 log_assert(!btor_op.empty());
368
369 int sid = get_bv_sid(1);
370 int nid_a = get_sig_nid(cell->getPort("\\A"));
371 int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort("\\B")) : 0;
372
373 if (GetSize(cell->getPort("\\A")) > 1) {
374 int nid_red_a = next_nid++;
375 btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
376 nid_a = nid_red_a;
377 }
378
379 if (btor_op != "not" && GetSize(cell->getPort("\\B")) > 1) {
380 int nid_red_b = next_nid++;
381 btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
382 nid_b = nid_red_b;
383 }
384
385 int nid = next_nid++;
386 if (btor_op != "not")
387 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
388 else
389 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
390
391 SigSpec sig = sigmap(cell->getPort("\\Y"));
392
393 if (GetSize(sig) > 1) {
394 int sid = get_bv_sid(GetSize(sig));
395 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
396 int nid2 = next_nid++;
397 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
398 nid = nid2;
399 }
400
401 add_nid_sig(nid, sig);
402 goto okay;
403 }
404
405 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor"))
406 {
407 string btor_op;
408 if (cell->type == "$reduce_and") btor_op = "redand";
409 if (cell->type.in("$reduce_or", "$reduce_bool")) btor_op = "redor";
410 if (cell->type.in("$reduce_xor", "$reduce_xnor")) btor_op = "redxor";
411 log_assert(!btor_op.empty());
412
413 int sid = get_bv_sid(1);
414 int nid_a = get_sig_nid(cell->getPort("\\A"));
415
416 int nid = next_nid++;
417 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
418
419 if (cell->type == "$reduce_xnor") {
420 int nid2 = next_nid++;
421 btorf("%d not %d %d %d\n", nid2, sid, nid);
422 nid = nid2;
423 }
424
425 SigSpec sig = sigmap(cell->getPort("\\Y"));
426
427 if (GetSize(sig) > 1) {
428 int sid = get_bv_sid(GetSize(sig));
429 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
430 int nid2 = next_nid++;
431 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
432 nid = nid2;
433 }
434
435 add_nid_sig(nid, sig);
436 goto okay;
437 }
438
439 if (cell->type.in("$mux", "$_MUX_"))
440 {
441 SigSpec sig_a = sigmap(cell->getPort("\\A"));
442 SigSpec sig_b = sigmap(cell->getPort("\\B"));
443 SigSpec sig_s = sigmap(cell->getPort("\\S"));
444 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
445
446 int nid_a = get_sig_nid(sig_a);
447 int nid_b = get_sig_nid(sig_b);
448 int nid_s = get_sig_nid(sig_s);
449
450 int sid = get_bv_sid(GetSize(sig_y));
451 int nid = next_nid++;
452 btorf("%d ite %d %d %d %d\n", nid, sid, nid_s, nid_b, nid_a);
453
454 add_nid_sig(nid, sig_y);
455 goto okay;
456 }
457
458 if (cell->type == "$pmux")
459 {
460 SigSpec sig_a = sigmap(cell->getPort("\\A"));
461 SigSpec sig_b = sigmap(cell->getPort("\\B"));
462 SigSpec sig_s = sigmap(cell->getPort("\\S"));
463 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
464
465 int width = GetSize(sig_a);
466 int sid = get_bv_sid(width);
467 int nid = get_sig_nid(sig_a);
468
469 for (int i = 0; i < GetSize(sig_s); i++) {
470 int nid_b = get_sig_nid(sig_b.extract(i*width, width));
471 int nid_s = get_sig_nid(sig_s.extract(i));
472 int nid2 = next_nid++;
473 btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
474 nid = nid2;
475 }
476
477 add_nid_sig(nid, sig_y);
478 goto okay;
479 }
480
481 if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N", "$_FF_"))
482 {
483 SigSpec sig_d = sigmap(cell->getPort("\\D"));
484 SigSpec sig_q = sigmap(cell->getPort("\\Q"));
485
486 IdString symbol;
487
488 if (sig_q.is_wire()) {
489 Wire *w = sig_q.as_wire();
490 if (w->port_id == 0) {
491 statewires.insert(w);
492 symbol = w->name;
493 }
494 }
495
496 int sid = get_bv_sid(GetSize(sig_q));
497 int nid = next_nid++;
498
499 if (symbol.empty())
500 btorf("%d state %d\n", nid, sid);
501 else
502 btorf("%d state %d %s\n", nid, sid, log_id(symbol));
503
504 Const initval;
505 for (int i = 0; i < GetSize(sig_q); i++)
506 if (initbits.count(sig_q[i]))
507 initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
508 else
509 initval.bits.push_back(State::Sx);
510
511 if (!initval.is_fully_undef()) {
512 int nid_init_val = get_sig_nid(initval);
513 int nid_init = next_nid++;
514 if (verbose)
515 btorf("; initval = %s\n", log_signal(initval));
516 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
517 }
518
519 ff_todo.push_back(make_pair(nid, cell));
520 add_nid_sig(nid, sig_q);
521 goto okay;
522 }
523
524 if (cell->type.in("$anyconst", "$anyseq"))
525 {
526 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
527
528 int sid = get_bv_sid(GetSize(sig_y));
529 int nid = next_nid++;
530
531 btorf("%d state %d\n", nid, sid);
532
533 if (cell->type == "$anyconst") {
534 int nid2 = next_nid++;
535 btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
536 }
537
538 add_nid_sig(nid, sig_y);
539 goto okay;
540 }
541
542 if (cell->type == "$initstate")
543 {
544 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
545
546 if (initstate_nid < 0)
547 {
548 int sid = get_bv_sid(1);
549 int one_nid = get_sig_nid(Const(1, 1));
550 int zero_nid = get_sig_nid(Const(0, 1));
551 initstate_nid = next_nid++;
552 btorf("%d state %d\n", initstate_nid, sid);
553 btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
554 btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
555 }
556
557 add_nid_sig(initstate_nid, sig_y);
558 goto okay;
559 }
560
561 log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
562
563 okay:
564 btorf_pop(log_id(cell));
565 cell_recursion_guard.erase(cell);
566 }
567
568 int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false)
569 {
570 int nid = -1;
571 sigmap.apply(sig);
572
573 for (auto bit : sig)
574 if (bit == State::Sx)
575 goto has_undef_bits;
576
577 if (0)
578 {
579 has_undef_bits:
580 SigSpec sig_mask_undef, sig_noundef;
581 int first_undef = -1;
582
583 for (int i = 0; i < GetSize(sig); i++)
584 if (sig[i] == State::Sx) {
585 if (first_undef < 0)
586 first_undef = i;
587 sig_mask_undef.append(State::S1);
588 sig_noundef.append(State::S0);
589 } else {
590 sig_mask_undef.append(State::S0);
591 sig_noundef.append(sig[i]);
592 }
593
594 if (to_width < 0 || first_undef < to_width)
595 {
596 int sid = get_bv_sid(GetSize(sig));
597
598 int nid_input = next_nid++;
599 btorf("%d input %d\n", nid_input, sid);
600
601 int nid_masked_input;
602 if (sig_mask_undef.is_fully_ones()) {
603 nid_masked_input = nid_input;
604 } else {
605 int nid_mask_undef = get_sig_nid(sig_mask_undef);
606 nid_masked_input = next_nid++;
607 btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
608 }
609
610 if (sig_noundef.is_fully_zero()) {
611 nid = nid_masked_input;
612 } else {
613 int nid_noundef = get_sig_nid(sig_noundef);
614 nid = next_nid++;
615 btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
616 }
617
618 goto extend_or_trim;
619 }
620
621 sig = sig_noundef;
622 }
623
624 if (sig_nid.count(sig) == 0)
625 {
626 // <nid>, <bitidx>
627 vector<pair<int, int>> nidbits;
628
629 // collect all bits
630 for (int i = 0; i < GetSize(sig); i++)
631 {
632 SigBit bit = sig[i];
633
634 if (bit_nid.count(bit) == 0)
635 {
636 if (bit.wire == nullptr)
637 {
638 Const c(bit.data);
639
640 while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
641 c.bits.push_back(sig[i+GetSize(c)].data);
642
643 if (consts.count(c) == 0) {
644 int sid = get_bv_sid(GetSize(c));
645 int nid = next_nid++;
646 btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
647 consts[c] = nid;
648 nid_width[nid] = GetSize(c);
649 }
650
651 int nid = consts.at(c);
652
653 for (int j = 0; j < GetSize(c); j++)
654 nidbits.push_back(make_pair(nid, j));
655
656 i += GetSize(c)-1;
657 continue;
658 }
659 else
660 {
661 export_cell(bit_cell.at(bit));
662 log_assert(bit_nid.count(bit));
663 }
664 }
665
666 nidbits.push_back(bit_nid.at(bit));
667 }
668
669 int width = 0;
670 int nid = -1;
671
672 // group bits and emit slice-concat chain
673 for (int i = 0; i < GetSize(nidbits); i++)
674 {
675 int nid2 = nidbits[i].first;
676 int lower = nidbits[i].second;
677 int upper = lower;
678
679 while (i+1 < GetSize(nidbits) && nidbits[i+1].first == nidbits[i].first &&
680 nidbits[i+1].second == nidbits[i].second+1)
681 upper++, i++;
682
683 int nid3 = nid2;
684
685 if (lower != 0 || upper+1 != nid_width.at(nid2)) {
686 int sid = get_bv_sid(upper-lower+1);
687 nid3 = next_nid++;
688 btorf("%d slice %d %d %d %d\n", nid3, sid, nid2, upper, lower);
689 }
690
691 int nid4 = nid3;
692
693 if (nid >= 0) {
694 int sid = get_bv_sid(width+upper-lower+1);
695 nid4 = next_nid++;
696 btorf("%d concat %d %d %d\n", nid4, sid, nid3, nid);
697 }
698
699 width += upper-lower+1;
700 nid = nid4;
701 }
702
703 sig_nid[sig] = nid;
704 nid_width[nid] = width;
705 }
706
707 nid = sig_nid.at(sig);
708
709 extend_or_trim:
710 if (to_width >= 0 && to_width != GetSize(sig))
711 {
712 if (to_width < GetSize(sig))
713 {
714 int sid = get_bv_sid(to_width);
715 int nid2 = next_nid++;
716 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, to_width-1);
717 nid = nid2;
718 }
719 else
720 {
721 int sid = get_bv_sid(to_width);
722 int nid2 = next_nid++;
723 btorf("%d %s %d %d %d\n", nid2, is_signed ? "sext" : "uext",
724 sid, nid, to_width - GetSize(sig));
725 nid = nid2;
726 }
727 }
728
729 return nid;
730 }
731
732 BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad) :
733 f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad)
734 {
735 btorf_push("inputs");
736
737 for (auto wire : module->wires())
738 {
739 if (wire->attributes.count("\\init")) {
740 Const attrval = wire->attributes.at("\\init");
741 for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
742 if (attrval[i] == State::S0 || attrval[i] == State::S1)
743 initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
744 }
745
746 if (!wire->port_id || !wire->port_input)
747 continue;
748
749 SigSpec sig = sigmap(wire);
750 int sid = get_bv_sid(GetSize(sig));
751 int nid = next_nid++;
752
753 btorf("%d input %d %s\n", nid, sid, log_id(wire));
754 add_nid_sig(nid, sig);
755 }
756
757 btorf_pop("inputs");
758
759 for (auto cell : module->cells())
760 for (auto &conn : cell->connections())
761 {
762 if (!cell->output(conn.first))
763 continue;
764
765 for (auto bit : sigmap(conn.second))
766 bit_cell[bit] = cell;
767 }
768
769 for (auto wire : module->wires())
770 {
771 if (!wire->port_id || !wire->port_output)
772 continue;
773
774 btorf_push(stringf("output %s", log_id(wire)));
775
776 int sid = get_bv_sid(GetSize(wire));
777 int nid = get_sig_nid(wire);
778 btorf("%d output %d %d %s\n", next_nid++, sid, nid, log_id(wire));
779
780 btorf_pop(stringf("output %s", log_id(wire)));
781 }
782
783 for (auto cell : module->cells())
784 {
785 if (cell->type == "$assume")
786 {
787 btorf_push(log_id(cell));
788
789 int sid = get_bv_sid(1);
790 int nid_a = get_sig_nid(cell->getPort("\\A"));
791 int nid_en = get_sig_nid(cell->getPort("\\EN"));
792 int nid_not_en = next_nid++;
793 int nid_a_or_not_en = next_nid++;
794 int nid = next_nid++;
795
796 btorf("%d not %d %d\n", nid_not_en, sid, nid_en);
797 btorf("%d or %d %d %d\n", nid_a_or_not_en, sid, nid_a, nid_not_en);
798 btorf("%d constraint %d\n", nid, nid_a_or_not_en);
799
800 btorf_pop(log_id(cell));
801 }
802
803 if (cell->type == "$assert")
804 {
805 btorf_push(log_id(cell));
806
807 int sid = get_bv_sid(1);
808 int nid_a = get_sig_nid(cell->getPort("\\A"));
809 int nid_en = get_sig_nid(cell->getPort("\\EN"));
810 int nid_not_a = next_nid++;
811 int nid_en_and_not_a = next_nid++;
812
813 btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
814 btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);
815
816 if (single_bad) {
817 bad_properties.push_back(nid_en_and_not_a);
818 } else {
819 int nid = next_nid++;
820 btorf("%d bad %d\n", nid, nid_en_and_not_a);
821 }
822
823 btorf_pop(log_id(cell));
824 }
825 }
826
827 for (auto wire : module->wires())
828 {
829 if (wire->port_id || wire->name[0] == '$')
830 continue;
831
832 btorf_push(stringf("wire %s", log_id(wire)));
833
834 int sid = get_bv_sid(GetSize(wire));
835 int nid = get_sig_nid(sigmap(wire));
836
837 if (statewires.count(wire))
838 continue;
839
840 int this_nid = next_nid++;
841 btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, log_id(wire));
842
843 btorf_pop(stringf("wire %s", log_id(wire)));
844 continue;
845 }
846
847 while (!ff_todo.empty())
848 {
849 vector<pair<int, Cell*>> todo;
850 todo.swap(ff_todo);
851
852 for (auto &it : todo)
853 {
854 btorf_push(stringf("next %s", log_id(it.second)));
855
856 SigSpec sig = sigmap(it.second->getPort("\\D"));
857
858 int nid = get_sig_nid(sig);
859 int sid = get_bv_sid(GetSize(sig));
860 btorf("%d next %d %d %d\n", next_nid++, sid, it.first, nid);
861
862 btorf_pop(stringf("next %s", log_id(it.second)));
863 }
864 }
865
866 while (!bad_properties.empty())
867 {
868 vector<int> todo;
869 bad_properties.swap(todo);
870
871 int sid = get_bv_sid(1);
872 int cursor = 0;
873
874 while (cursor+1 < GetSize(todo))
875 {
876 int nid_a = todo[cursor++];
877 int nid_b = todo[cursor++];
878 int nid = next_nid++;
879
880 bad_properties.push_back(nid);
881 btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
882 }
883
884 if (!bad_properties.empty()) {
885 if (cursor < GetSize(todo))
886 bad_properties.push_back(todo[cursor++]);
887 log_assert(cursor == GetSize(todo));
888 } else {
889 int nid = next_nid++;
890 log_assert(cursor == 0);
891 log_assert(GetSize(todo) == 1);
892 btorf("%d bad %d\n", nid, todo[cursor]);
893 }
894 }
895 }
896 };
897
898 struct BtorBackend : public Backend {
899 BtorBackend() : Backend("btor", "write design to BTOR file") { }
900 virtual void help()
901 {
902 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
903 log("\n");
904 log(" write_btor [options] [filename]\n");
905 log("\n");
906 log("Write a BTOR description of the current design.\n");
907 log("\n");
908 log(" -v\n");
909 log(" Add comments and indentation to BTOR output file\n");
910 log("\n");
911 log(" -s\n");
912 log(" Output only a single bad property for all asserts\n");
913 log("\n");
914 }
915 virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
916 {
917 bool verbose = false, single_bad = false;
918
919 log_header(design, "Executing BTOR backend.\n");
920
921 size_t argidx;
922 for (argidx = 1; argidx < args.size(); argidx++)
923 {
924 if (args[argidx] == "-v") {
925 verbose = true;
926 continue;
927 }
928 if (args[argidx] == "-s") {
929 single_bad = true;
930 continue;
931 }
932 break;
933 }
934 extra_args(f, filename, args, argidx);
935
936 RTLIL::Module *topmod = design->top_module();
937
938 if (topmod == nullptr)
939 log_cmd_error("No top module found.\n");
940
941 *f << stringf("; BTOR description generated by %s for module %s.\n",
942 yosys_version_str, log_id(topmod));
943
944 BtorWorker(*f, topmod, verbose, single_bad);
945
946 *f << stringf("; end of yosys output\n");
947 }
948 } BtorBackend;
949
950 PRIVATE_NAMESPACE_END