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kernel/rtlil: Extract some helpers for checking memory cell types.
[yosys.git] / backends / btor / btor.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] Btor2 , BtorMC and Boolector 3.0
21 // Aina Niemetz, Mathias Preiner, Clifford Wolf, Armin Biere
22 // Computer Aided Verification - 30th International Conference, CAV 2018
23 // https://cs.stanford.edu/people/niemetz/publication/2018/niemetzpreinerwolfbiere-cav18/
24
25 #include "kernel/rtlil.h"
26 #include "kernel/register.h"
27 #include "kernel/sigtools.h"
28 #include "kernel/celltypes.h"
29 #include "kernel/log.h"
30 #include "kernel/mem.h"
31 #include <string>
32
33 USING_YOSYS_NAMESPACE
34 PRIVATE_NAMESPACE_BEGIN
35
36 struct BtorWorker
37 {
38 std::ostream &f;
39 SigMap sigmap;
40 RTLIL::Module *module;
41 bool verbose;
42 bool single_bad;
43 bool cover_mode;
44 bool print_internal_names;
45
46 int next_nid = 1;
47 int initstate_nid = -1;
48
49 // <width> => <sid>
50 dict<int, int> sorts_bv;
51
52 // (<address-width>, <data-width>) => <sid>
53 dict<pair<int, int>, int> sorts_mem;
54
55 // SigBit => (<nid>, <bitidx>)
56 dict<SigBit, pair<int, int>> bit_nid;
57
58 // <nid> => <bvwidth>
59 dict<int, int> nid_width;
60
61 // SigSpec => <nid>
62 dict<SigSpec, int> sig_nid;
63
64 // bit to driving cell
65 dict<SigBit, Cell*> bit_cell;
66
67 // nids for constants
68 dict<Const, int> consts;
69
70 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
71 vector<pair<int, Cell*>> ff_todo;
72 vector<pair<int, Mem*>> mem_todo;
73
74 pool<Cell*> cell_recursion_guard;
75 vector<int> bad_properties;
76 dict<SigBit, bool> initbits;
77 pool<Wire*> statewires;
78 pool<string> srcsymbols;
79 vector<Mem> memories;
80 dict<Cell*, Mem*> mem_cells;
81
82 string indent, info_filename;
83 vector<string> info_lines;
84 dict<int, int> info_clocks;
85
86 void btorf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
87 {
88 va_list ap;
89 va_start(ap, fmt);
90 f << indent << vstringf(fmt, ap);
91 va_end(ap);
92 }
93
94 void infof(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
95 {
96 va_list ap;
97 va_start(ap, fmt);
98 info_lines.push_back(vstringf(fmt, ap));
99 va_end(ap);
100 }
101
102 template<typename T>
103 string getinfo(T *obj, bool srcsym = false)
104 {
105 string infostr = log_id(obj);
106 if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
107 if (obj->attributes.count(ID::src)) {
108 string src = obj->attributes.at(ID::src).decode_string().c_str();
109 if (srcsym && infostr[0] == '$') {
110 std::replace(src.begin(), src.end(), ' ', '_');
111 if (srcsymbols.count(src) || module->count_id("\\" + src)) {
112 for (int i = 1;; i++) {
113 string s = stringf("%s-%d", src.c_str(), i);
114 if (!srcsymbols.count(s) && !module->count_id("\\" + s)) {
115 src = s;
116 break;
117 }
118 }
119 }
120 srcsymbols.insert(src);
121 infostr = src;
122 } else {
123 infostr += " ; " + src;
124 }
125 }
126 return " " + infostr;
127 }
128
129 void btorf_push(const string &id)
130 {
131 if (verbose) {
132 f << indent << stringf(" ; begin %s\n", id.c_str());
133 indent += " ";
134 }
135 }
136
137 void btorf_pop(const string &id)
138 {
139 if (verbose) {
140 indent = indent.substr(4);
141 f << indent << stringf(" ; end %s\n", id.c_str());
142 }
143 }
144
145 int get_bv_sid(int width)
146 {
147 if (sorts_bv.count(width) == 0) {
148 int nid = next_nid++;
149 btorf("%d sort bitvec %d\n", nid, width);
150 sorts_bv[width] = nid;
151 }
152 return sorts_bv.at(width);
153 }
154
155 int get_mem_sid(int abits, int dbits)
156 {
157 pair<int, int> key(abits, dbits);
158 if (sorts_mem.count(key) == 0) {
159 int addr_sid = get_bv_sid(abits);
160 int data_sid = get_bv_sid(dbits);
161 int nid = next_nid++;
162 btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
163 sorts_mem[key] = nid;
164 }
165 return sorts_mem.at(key);
166 }
167
168 void add_nid_sig(int nid, const SigSpec &sig)
169 {
170 if (verbose)
171 f << indent << stringf("; %d %s\n", nid, log_signal(sig));
172
173 for (int i = 0; i < GetSize(sig); i++)
174 bit_nid[sig[i]] = make_pair(nid, i);
175
176 sig_nid[sig] = nid;
177 nid_width[nid] = GetSize(sig);
178 }
179
180 void export_cell(Cell *cell)
181 {
182 if (cell_recursion_guard.count(cell)) {
183 string cell_list;
184 for (auto c : cell_recursion_guard)
185 cell_list += stringf("\n %s", log_id(c));
186 log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
187 }
188
189 cell_recursion_guard.insert(cell);
190 btorf_push(log_id(cell));
191
192 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
193 ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
194 {
195 string btor_op;
196 if (cell->type == ID($add)) btor_op = "add";
197 if (cell->type == ID($sub)) btor_op = "sub";
198 if (cell->type == ID($mul)) btor_op = "mul";
199 if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
200 if (cell->type == ID($shr)) btor_op = "srl";
201 if (cell->type == ID($sshr)) btor_op = "sra";
202 if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
203 if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
204 if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
205 if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
206 if (cell->type == ID($concat)) btor_op = "concat";
207 if (cell->type == ID($_NAND_)) btor_op = "nand";
208 if (cell->type == ID($_NOR_)) btor_op = "nor";
209 if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
210 log_assert(!btor_op.empty());
211
212 int width_ay = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
213 int width = std::max(width_ay, GetSize(cell->getPort(ID::B)));
214
215 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
216 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
217
218 if (btor_op == "shift" && !b_signed)
219 btor_op = "srl";
220
221 if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
222 b_signed = false;
223
224 if (cell->type == ID($sshr) && !a_signed)
225 btor_op = "srl";
226
227 int sid = get_bv_sid(width);
228 int nid;
229
230 int nid_a;
231 if (cell->type.in(ID($shl), ID($shr), ID($shift), ID($shiftx)) && a_signed && width_ay < width) {
232 // sign-extend A up to the width of Y
233 int nid_a_padded = get_sig_nid(cell->getPort(ID::A), width_ay, a_signed);
234
235 // zero-extend the rest
236 int zeroes = get_sig_nid(Const(0, width-width_ay));
237 nid_a = next_nid++;
238 btorf("%d concat %d %d %d\n", nid_a, sid, zeroes, nid_a_padded);
239 } else {
240 nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
241 }
242
243 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
244
245 if (btor_op == "shift")
246 {
247 int nid_r = next_nid++;
248 btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);
249
250 int nid_b_neg = next_nid++;
251 btorf("%d neg %d %d\n", nid_b_neg, sid, nid_b);
252
253 int nid_l = next_nid++;
254 btorf("%d sll %d %d %d\n", nid_l, sid, nid_a, nid_b_neg);
255
256 int sid_bit = get_bv_sid(1);
257 int nid_zero = get_sig_nid(Const(0, width));
258 int nid_b_ltz = next_nid++;
259 btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
260
261 nid = next_nid++;
262 btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell).c_str());
263 }
264 else
265 {
266 nid = next_nid++;
267 btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
268 }
269
270 SigSpec sig = sigmap(cell->getPort(ID::Y));
271
272 if (GetSize(sig) < width) {
273 int sid = get_bv_sid(GetSize(sig));
274 int nid2 = next_nid++;
275 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
276 nid = nid2;
277 }
278
279 add_nid_sig(nid, sig);
280 goto okay;
281 }
282
283 if (cell->type.in(ID($div), ID($mod), ID($modfloor)))
284 {
285 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
286 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
287
288 string btor_op;
289 if (cell->type == ID($div)) btor_op = "div";
290 // "rem" = truncating modulo
291 if (cell->type == ID($mod)) btor_op = "rem";
292 // "mod" = flooring modulo
293 if (cell->type == ID($modfloor)) {
294 // "umod" doesn't exist because it's the same as "urem"
295 btor_op = a_signed || b_signed ? "mod" : "rem";
296 }
297 log_assert(!btor_op.empty());
298
299 int width = GetSize(cell->getPort(ID::Y));
300 width = std::max(width, GetSize(cell->getPort(ID::A)));
301 width = std::max(width, GetSize(cell->getPort(ID::B)));
302
303 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
304 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
305
306 int sid = get_bv_sid(width);
307 int nid = next_nid++;
308 btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
309
310 SigSpec sig = sigmap(cell->getPort(ID::Y));
311
312 if (GetSize(sig) < width) {
313 int sid = get_bv_sid(GetSize(sig));
314 int nid2 = next_nid++;
315 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
316 nid = nid2;
317 }
318
319 add_nid_sig(nid, sig);
320 goto okay;
321 }
322
323 if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
324 {
325 int sid = get_bv_sid(1);
326 int nid_a = get_sig_nid(cell->getPort(ID::A));
327 int nid_b = get_sig_nid(cell->getPort(ID::B));
328
329 int nid1 = next_nid++;
330 int nid2 = next_nid++;
331
332 if (cell->type == ID($_ANDNOT_)) {
333 btorf("%d not %d %d\n", nid1, sid, nid_b);
334 btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
335 }
336
337 if (cell->type == ID($_ORNOT_)) {
338 btorf("%d not %d %d\n", nid1, sid, nid_b);
339 btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
340 }
341
342 SigSpec sig = sigmap(cell->getPort(ID::Y));
343 add_nid_sig(nid2, sig);
344 goto okay;
345 }
346
347 if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
348 {
349 int sid = get_bv_sid(1);
350 int nid_a = get_sig_nid(cell->getPort(ID::A));
351 int nid_b = get_sig_nid(cell->getPort(ID::B));
352 int nid_c = get_sig_nid(cell->getPort(ID::C));
353
354 int nid1 = next_nid++;
355 int nid2 = next_nid++;
356 int nid3 = next_nid++;
357
358 if (cell->type == ID($_OAI3_)) {
359 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
360 btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
361 btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
362 }
363
364 if (cell->type == ID($_AOI3_)) {
365 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
366 btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
367 btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
368 }
369
370 SigSpec sig = sigmap(cell->getPort(ID::Y));
371 add_nid_sig(nid3, sig);
372 goto okay;
373 }
374
375 if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
376 {
377 int sid = get_bv_sid(1);
378 int nid_a = get_sig_nid(cell->getPort(ID::A));
379 int nid_b = get_sig_nid(cell->getPort(ID::B));
380 int nid_c = get_sig_nid(cell->getPort(ID::C));
381 int nid_d = get_sig_nid(cell->getPort(ID::D));
382
383 int nid1 = next_nid++;
384 int nid2 = next_nid++;
385 int nid3 = next_nid++;
386 int nid4 = next_nid++;
387
388 if (cell->type == ID($_OAI4_)) {
389 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
390 btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
391 btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
392 btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
393 }
394
395 if (cell->type == ID($_AOI4_)) {
396 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
397 btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
398 btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
399 btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
400 }
401
402 SigSpec sig = sigmap(cell->getPort(ID::Y));
403 add_nid_sig(nid4, sig);
404 goto okay;
405 }
406
407 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
408 {
409 string btor_op;
410 if (cell->type == ID($lt)) btor_op = "lt";
411 if (cell->type == ID($le)) btor_op = "lte";
412 if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
413 if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
414 if (cell->type == ID($ge)) btor_op = "gte";
415 if (cell->type == ID($gt)) btor_op = "gt";
416 log_assert(!btor_op.empty());
417
418 int width = 1;
419 width = std::max(width, GetSize(cell->getPort(ID::A)));
420 width = std::max(width, GetSize(cell->getPort(ID::B)));
421
422 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
423 bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
424
425 int sid = get_bv_sid(1);
426 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
427 int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
428
429 int nid = next_nid++;
430 if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
431 btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
432 } else {
433 btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
434 }
435
436 SigSpec sig = sigmap(cell->getPort(ID::Y));
437
438 if (GetSize(sig) > 1) {
439 int sid = get_bv_sid(GetSize(sig));
440 int nid2 = next_nid++;
441 btorf("%d uext %d %d %d\n", nid2, sid, nid, GetSize(sig) - 1);
442 nid = nid2;
443 }
444
445 add_nid_sig(nid, sig);
446 goto okay;
447 }
448
449 if (cell->type.in(ID($not), ID($neg), ID($_NOT_)))
450 {
451 string btor_op;
452 if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
453 if (cell->type == ID($neg)) btor_op = "neg";
454 log_assert(!btor_op.empty());
455
456 int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
457
458 bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
459
460 int sid = get_bv_sid(width);
461 int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
462
463 int nid = next_nid++;
464 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
465
466 SigSpec sig = sigmap(cell->getPort(ID::Y));
467
468 if (GetSize(sig) < width) {
469 int sid = get_bv_sid(GetSize(sig));
470 int nid2 = next_nid++;
471 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
472 nid = nid2;
473 }
474
475 add_nid_sig(nid, sig);
476 goto okay;
477 }
478
479 if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
480 {
481 string btor_op;
482 if (cell->type == ID($logic_and)) btor_op = "and";
483 if (cell->type == ID($logic_or)) btor_op = "or";
484 if (cell->type == ID($logic_not)) btor_op = "not";
485 log_assert(!btor_op.empty());
486
487 int sid = get_bv_sid(1);
488 int nid_a = get_sig_nid(cell->getPort(ID::A));
489 int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0;
490
491 if (GetSize(cell->getPort(ID::A)) > 1) {
492 int nid_red_a = next_nid++;
493 btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
494 nid_a = nid_red_a;
495 }
496
497 if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) {
498 int nid_red_b = next_nid++;
499 btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
500 nid_b = nid_red_b;
501 }
502
503 int nid = next_nid++;
504 if (btor_op != "not")
505 btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
506 else
507 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
508
509 SigSpec sig = sigmap(cell->getPort(ID::Y));
510
511 if (GetSize(sig) > 1) {
512 int sid = get_bv_sid(GetSize(sig));
513 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
514 int nid2 = next_nid++;
515 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
516 nid = nid2;
517 }
518
519 add_nid_sig(nid, sig);
520 goto okay;
521 }
522
523 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
524 {
525 string btor_op;
526 if (cell->type == ID($reduce_and)) btor_op = "redand";
527 if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
528 if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
529 log_assert(!btor_op.empty());
530
531 int sid = get_bv_sid(1);
532 int nid_a = get_sig_nid(cell->getPort(ID::A));
533
534 int nid = next_nid++;
535
536 if (cell->type == ID($reduce_xnor)) {
537 int nid2 = next_nid++;
538 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
539 btorf("%d not %d %d\n", nid2, sid, nid);
540 nid = nid2;
541 } else {
542 btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
543 }
544
545 SigSpec sig = sigmap(cell->getPort(ID::Y));
546
547 if (GetSize(sig) > 1) {
548 int sid = get_bv_sid(GetSize(sig));
549 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
550 int nid2 = next_nid++;
551 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
552 nid = nid2;
553 }
554
555 add_nid_sig(nid, sig);
556 goto okay;
557 }
558
559 if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
560 {
561 SigSpec sig_a = sigmap(cell->getPort(ID::A));
562 SigSpec sig_b = sigmap(cell->getPort(ID::B));
563 SigSpec sig_s = sigmap(cell->getPort(ID::S));
564 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
565
566 int nid_a = get_sig_nid(sig_a);
567 int nid_b = get_sig_nid(sig_b);
568 int nid_s = get_sig_nid(sig_s);
569
570 int sid = get_bv_sid(GetSize(sig_y));
571 int nid = next_nid++;
572
573 if (cell->type == ID($_NMUX_)) {
574 int tmp = nid;
575 nid = next_nid++;
576 btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
577 btorf("%d not %d %d%s\n", nid, sid, tmp, getinfo(cell).c_str());
578 } else {
579 btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell).c_str());
580 }
581
582 add_nid_sig(nid, sig_y);
583 goto okay;
584 }
585
586 if (cell->type == ID($pmux))
587 {
588 SigSpec sig_a = sigmap(cell->getPort(ID::A));
589 SigSpec sig_b = sigmap(cell->getPort(ID::B));
590 SigSpec sig_s = sigmap(cell->getPort(ID::S));
591 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
592
593 int width = GetSize(sig_a);
594 int sid = get_bv_sid(width);
595 int nid = get_sig_nid(sig_a);
596
597 for (int i = 0; i < GetSize(sig_s); i++) {
598 int nid_b = get_sig_nid(sig_b.extract(i*width, width));
599 int nid_s = get_sig_nid(sig_s.extract(i));
600 int nid2 = next_nid++;
601 if (i == GetSize(sig_s)-1)
602 btorf("%d ite %d %d %d %d%s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell).c_str());
603 else
604 btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
605 nid = nid2;
606 }
607
608 add_nid_sig(nid, sig_y);
609 goto okay;
610 }
611
612 if (cell->type.in(ID($dff), ID($ff), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
613 {
614 SigSpec sig_d = sigmap(cell->getPort(ID::D));
615 SigSpec sig_q = sigmap(cell->getPort(ID::Q));
616
617 if (!info_filename.empty() && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
618 {
619 SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C));
620 int nid = get_sig_nid(sig_c);
621 bool negedge = false;
622
623 if (cell->type == ID($_DFF_N_))
624 negedge = true;
625
626 if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
627 negedge = true;
628
629 info_clocks[nid] |= negedge ? 2 : 1;
630 }
631
632 IdString symbol;
633
634 if (sig_q.is_wire()) {
635 Wire *w = sig_q.as_wire();
636 if (w->port_id == 0) {
637 statewires.insert(w);
638 symbol = w->name;
639 }
640 }
641
642 Const initval;
643 for (int i = 0; i < GetSize(sig_q); i++)
644 if (initbits.count(sig_q[i]))
645 initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
646 else
647 initval.bits.push_back(State::Sx);
648
649 int nid_init_val = -1;
650
651 if (!initval.is_fully_undef())
652 nid_init_val = get_sig_nid(initval, -1, false, true);
653
654 int sid = get_bv_sid(GetSize(sig_q));
655 int nid = next_nid++;
656
657 if (symbol.empty() || (!print_internal_names && symbol[0] == '$'))
658 btorf("%d state %d\n", nid, sid);
659 else
660 btorf("%d state %d %s\n", nid, sid, log_id(symbol));
661
662 if (nid_init_val >= 0) {
663 int nid_init = next_nid++;
664 if (verbose)
665 btorf("; initval = %s\n", log_signal(initval));
666 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
667 }
668
669 ff_todo.push_back(make_pair(nid, cell));
670 add_nid_sig(nid, sig_q);
671 goto okay;
672 }
673
674 if (cell->type.in(ID($anyconst), ID($anyseq)))
675 {
676 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
677
678 int sid = get_bv_sid(GetSize(sig_y));
679 int nid = next_nid++;
680
681 btorf("%d state %d\n", nid, sid);
682
683 if (cell->type == ID($anyconst)) {
684 int nid2 = next_nid++;
685 btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
686 }
687
688 add_nid_sig(nid, sig_y);
689 goto okay;
690 }
691
692 if (cell->type == ID($initstate))
693 {
694 SigSpec sig_y = sigmap(cell->getPort(ID::Y));
695
696 if (initstate_nid < 0)
697 {
698 int sid = get_bv_sid(1);
699 int one_nid = get_sig_nid(State::S1);
700 int zero_nid = get_sig_nid(State::S0);
701 initstate_nid = next_nid++;
702 btorf("%d state %d\n", initstate_nid, sid);
703 btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
704 btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
705 }
706
707 add_nid_sig(initstate_nid, sig_y);
708 goto okay;
709 }
710
711 if (cell->is_mem_cell())
712 {
713 Mem *mem = mem_cells[cell];
714
715 int abits = ceil_log2(mem->size);
716
717 bool asyncwr = false;
718 bool syncwr = false;
719
720 for (auto &port : mem->wr_ports) {
721 if (port.clk_enable)
722 syncwr = true;
723 else
724 asyncwr = true;
725 }
726
727 if (asyncwr && syncwr)
728 log_error("Memory %s.%s has mixed async/sync write ports.\n",
729 log_id(module), log_id(mem->memid));
730
731 for (auto &port : mem->rd_ports)
732 if (port.clk_enable)
733 log_error("Memory %s.%s has sync read ports.\n",
734 log_id(module), log_id(mem->memid));
735
736 int data_sid = get_bv_sid(mem->width);
737 int bool_sid = get_bv_sid(1);
738 int sid = get_mem_sid(abits, mem->width);
739
740 int nid_init_val = -1;
741
742 if (!mem->inits.empty())
743 {
744 Const initdata = mem->get_init_data();
745 bool constword = true;
746 Const firstword = initdata.extract(0, mem->width);
747
748 for (int i = 1; i < mem->size; i++) {
749 Const thisword = initdata.extract(i*mem->width, mem->width);
750 if (thisword != firstword) {
751 constword = false;
752 break;
753 }
754 }
755
756 if (constword)
757 {
758 if (verbose)
759 btorf("; initval = %s\n", log_signal(firstword));
760 nid_init_val = get_sig_nid(firstword, -1, false, true);
761 }
762 else
763 {
764 nid_init_val = next_nid++;
765 btorf("%d state %d\n", nid_init_val, sid);
766
767 for (int i = 0; i < mem->size; i++) {
768 Const thisword = initdata.extract(i*mem->width, mem->width);
769 if (thisword.is_fully_undef())
770 continue;
771 Const thisaddr(i, abits);
772 int nid_thisword = get_sig_nid(thisword, -1, false, true);
773 int nid_thisaddr = get_sig_nid(thisaddr, -1, false, true);
774 int last_nid_init_val = nid_init_val;
775 nid_init_val = next_nid++;
776 if (verbose)
777 btorf("; initval[%d] = %s\n", i, log_signal(thisword));
778 btorf("%d write %d %d %d %d\n", nid_init_val, sid, last_nid_init_val, nid_thisaddr, nid_thisword);
779 }
780 }
781 }
782
783
784 int nid = next_nid++;
785 int nid_head = nid;
786
787 if (mem->memid[0] == '$')
788 btorf("%d state %d\n", nid, sid);
789 else
790 btorf("%d state %d %s\n", nid, sid, log_id(mem->memid));
791
792 if (nid_init_val >= 0)
793 {
794 int nid_init = next_nid++;
795 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
796 }
797
798 if (asyncwr)
799 {
800 for (auto &port : mem->wr_ports)
801 {
802 SigSpec wa = port.addr;
803 wa.extend_u0(abits);
804
805 int wa_nid = get_sig_nid(wa);
806 int wd_nid = get_sig_nid(port.data);
807 int we_nid = get_sig_nid(port.en);
808
809 int nid2 = next_nid++;
810 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
811
812 int nid3 = next_nid++;
813 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
814
815 int nid4 = next_nid++;
816 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
817
818 int nid5 = next_nid++;
819 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
820
821 int nid6 = next_nid++;
822 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
823
824 int nid7 = next_nid++;
825 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
826
827 int nid8 = next_nid++;
828 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
829
830 int nid9 = next_nid++;
831 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
832
833 nid_head = nid9;
834 }
835 }
836
837 for (auto &port : mem->rd_ports)
838 {
839 SigSpec ra = port.addr;
840 ra.extend_u0(abits);
841
842 int ra_nid = get_sig_nid(ra);
843 int rd_nid = next_nid++;
844
845 btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);
846
847 add_nid_sig(rd_nid, port.data);
848 }
849
850 if (!asyncwr)
851 {
852 mem_todo.push_back(make_pair(nid, mem));
853 }
854 else
855 {
856 int nid2 = next_nid++;
857 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
858 }
859
860 goto okay;
861 }
862
863 if (cell->type.in(ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
864 log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_btor`.\n",
865 log_id(cell->type), log_id(module), log_id(cell));
866 }
867 if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
868 log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_btor`.\n",
869 log_id(cell->type), log_id(module), log_id(cell));
870 }
871 if (cell->type.in(ID($sr), ID($dlatch), ID($adlatch), ID($dlatchsr)) || cell->type.str().substr(0, 8) == "$_DLATCH" || cell->type.str().substr(0, 5) == "$_SR_") {
872 log_error("Unsupported cell type %s for cell %s.%s -- please run `clk2fflogic` before `write_btor`.\n",
873 log_id(cell->type), log_id(module), log_id(cell));
874 }
875 log_error("Unsupported cell type %s for cell %s.%s.\n",
876 log_id(cell->type), log_id(module), log_id(cell));
877
878 okay:
879 btorf_pop(log_id(cell));
880 cell_recursion_guard.erase(cell);
881 }
882
883 int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false, bool is_init = false)
884 {
885 int nid = -1;
886 sigmap.apply(sig);
887
888 for (auto bit : sig)
889 if (bit == State::Sx)
890 goto has_undef_bits;
891
892 if (0)
893 {
894 has_undef_bits:
895 SigSpec sig_mask_undef, sig_noundef;
896 int first_undef = -1;
897
898 for (int i = 0; i < GetSize(sig); i++)
899 if (sig[i] == State::Sx) {
900 if (first_undef < 0)
901 first_undef = i;
902 sig_mask_undef.append(State::S1);
903 sig_noundef.append(State::S0);
904 } else {
905 sig_mask_undef.append(State::S0);
906 sig_noundef.append(sig[i]);
907 }
908
909 if (to_width < 0 || first_undef < to_width)
910 {
911 int sid = get_bv_sid(GetSize(sig));
912
913 int nid_input = next_nid++;
914 if (is_init)
915 btorf("%d state %d\n", nid_input, sid);
916 else
917 btorf("%d input %d\n", nid_input, sid);
918
919 int nid_masked_input;
920 if (sig_mask_undef.is_fully_ones()) {
921 nid_masked_input = nid_input;
922 } else {
923 int nid_mask_undef = get_sig_nid(sig_mask_undef);
924 nid_masked_input = next_nid++;
925 btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
926 }
927
928 if (sig_noundef.is_fully_zero()) {
929 nid = nid_masked_input;
930 } else {
931 int nid_noundef = get_sig_nid(sig_noundef);
932 nid = next_nid++;
933 btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
934 }
935
936 goto extend_or_trim;
937 }
938
939 sig = sig_noundef;
940 }
941
942 if (sig_nid.count(sig) == 0)
943 {
944 // <nid>, <bitidx>
945 vector<pair<int, int>> nidbits;
946
947 // collect all bits
948 for (int i = 0; i < GetSize(sig); i++)
949 {
950 SigBit bit = sig[i];
951
952 if (bit_nid.count(bit) == 0)
953 {
954 if (bit.wire == nullptr)
955 {
956 Const c(bit.data);
957
958 while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
959 c.bits.push_back(sig[i+GetSize(c)].data);
960
961 if (consts.count(c) == 0) {
962 int sid = get_bv_sid(GetSize(c));
963 int nid = next_nid++;
964 btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
965 consts[c] = nid;
966 nid_width[nid] = GetSize(c);
967 }
968
969 int nid = consts.at(c);
970
971 for (int j = 0; j < GetSize(c); j++)
972 nidbits.push_back(make_pair(nid, j));
973
974 i += GetSize(c)-1;
975 continue;
976 }
977 else
978 {
979 if (bit_cell.count(bit) == 0)
980 {
981 SigSpec s = bit;
982
983 while (i+GetSize(s) < GetSize(sig) && sig[i+GetSize(s)].wire != nullptr &&
984 bit_cell.count(sig[i+GetSize(s)]) == 0)
985 s.append(sig[i+GetSize(s)]);
986
987 log_warning("No driver for signal %s.\n", log_signal(s));
988
989 int sid = get_bv_sid(GetSize(s));
990 int nid = next_nid++;
991 btorf("%d input %d\n", nid, sid);
992 nid_width[nid] = GetSize(s);
993
994 for (int j = 0; j < GetSize(s); j++)
995 nidbits.push_back(make_pair(nid, j));
996
997 i += GetSize(s)-1;
998 continue;
999 }
1000 else
1001 {
1002 export_cell(bit_cell.at(bit));
1003 log_assert(bit_nid.count(bit));
1004 }
1005 }
1006 }
1007
1008 nidbits.push_back(bit_nid.at(bit));
1009 }
1010
1011 int width = 0;
1012 int nid = -1;
1013
1014 // group bits and emit slice-concat chain
1015 for (int i = 0; i < GetSize(nidbits); i++)
1016 {
1017 int nid2 = nidbits[i].first;
1018 int lower = nidbits[i].second;
1019 int upper = lower;
1020
1021 while (i+1 < GetSize(nidbits) && nidbits[i+1].first == nidbits[i].first &&
1022 nidbits[i+1].second == nidbits[i].second+1)
1023 upper++, i++;
1024
1025 int nid3 = nid2;
1026
1027 if (lower != 0 || upper+1 != nid_width.at(nid2)) {
1028 int sid = get_bv_sid(upper-lower+1);
1029 nid3 = next_nid++;
1030 btorf("%d slice %d %d %d %d\n", nid3, sid, nid2, upper, lower);
1031 }
1032
1033 int nid4 = nid3;
1034
1035 if (nid >= 0) {
1036 int sid = get_bv_sid(width+upper-lower+1);
1037 nid4 = next_nid++;
1038 btorf("%d concat %d %d %d\n", nid4, sid, nid3, nid);
1039 }
1040
1041 width += upper-lower+1;
1042 nid = nid4;
1043 }
1044
1045 sig_nid[sig] = nid;
1046 nid_width[nid] = width;
1047 }
1048
1049 nid = sig_nid.at(sig);
1050
1051 extend_or_trim:
1052 if (to_width >= 0 && to_width != GetSize(sig))
1053 {
1054 if (to_width < GetSize(sig))
1055 {
1056 int sid = get_bv_sid(to_width);
1057 int nid2 = next_nid++;
1058 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, to_width-1);
1059 nid = nid2;
1060 }
1061 else
1062 {
1063 int sid = get_bv_sid(to_width);
1064 int nid2 = next_nid++;
1065 btorf("%d %s %d %d %d\n", nid2, is_signed ? "sext" : "uext",
1066 sid, nid, to_width - GetSize(sig));
1067 nid = nid2;
1068 }
1069 }
1070
1071 return nid;
1072 }
1073
1074 BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad, bool cover_mode, bool print_internal_names, string info_filename) :
1075 f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad), cover_mode(cover_mode), print_internal_names(print_internal_names), info_filename(info_filename)
1076 {
1077 if (!info_filename.empty())
1078 infof("name %s\n", log_id(module));
1079
1080 memories = Mem::get_all_memories(module);
1081
1082 dict<IdString, Mem*> mem_dict;
1083 for (auto &mem : memories)
1084 mem_dict[mem.memid] = &mem;
1085 for (auto cell : module->cells())
1086 if (cell->type.in(ID($mem), ID($memwr), ID($memrd), ID($meminit)))
1087 mem_cells[cell] = mem_dict[cell->parameters.at(ID::MEMID).decode_string()];
1088
1089 btorf_push("inputs");
1090
1091 for (auto wire : module->wires())
1092 {
1093 if (wire->attributes.count(ID::init)) {
1094 Const attrval = wire->attributes.at(ID::init);
1095 for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
1096 if (attrval[i] == State::S0 || attrval[i] == State::S1)
1097 initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
1098 }
1099
1100 if (!wire->port_id || !wire->port_input)
1101 continue;
1102
1103 SigSpec sig = sigmap(wire);
1104 int sid = get_bv_sid(GetSize(sig));
1105 int nid = next_nid++;
1106
1107 btorf("%d input %d%s\n", nid, sid, getinfo(wire).c_str());
1108 add_nid_sig(nid, sig);
1109 }
1110
1111 btorf_pop("inputs");
1112
1113 for (auto cell : module->cells())
1114 for (auto &conn : cell->connections())
1115 {
1116 if (!cell->output(conn.first))
1117 continue;
1118
1119 for (auto bit : sigmap(conn.second))
1120 bit_cell[bit] = cell;
1121 }
1122
1123 for (auto wire : module->wires())
1124 {
1125 if (!wire->port_id || !wire->port_output)
1126 continue;
1127
1128 btorf_push(stringf("output %s", log_id(wire)));
1129
1130 int nid = get_sig_nid(wire);
1131 btorf("%d output %d%s\n", next_nid++, nid, getinfo(wire).c_str());
1132
1133 btorf_pop(stringf("output %s", log_id(wire)));
1134 }
1135
1136 for (auto cell : module->cells())
1137 {
1138 if (cell->type == ID($assume))
1139 {
1140 btorf_push(log_id(cell));
1141
1142 int sid = get_bv_sid(1);
1143 int nid_a = get_sig_nid(cell->getPort(ID::A));
1144 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1145 int nid_not_en = next_nid++;
1146 int nid_a_or_not_en = next_nid++;
1147 int nid = next_nid++;
1148
1149 btorf("%d not %d %d\n", nid_not_en, sid, nid_en);
1150 btorf("%d or %d %d %d\n", nid_a_or_not_en, sid, nid_a, nid_not_en);
1151 btorf("%d constraint %d\n", nid, nid_a_or_not_en);
1152
1153 btorf_pop(log_id(cell));
1154 }
1155
1156 if (cell->type == ID($assert))
1157 {
1158 btorf_push(log_id(cell));
1159
1160 int sid = get_bv_sid(1);
1161 int nid_a = get_sig_nid(cell->getPort(ID::A));
1162 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1163 int nid_not_a = next_nid++;
1164 int nid_en_and_not_a = next_nid++;
1165
1166 btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
1167 btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);
1168
1169 if (single_bad && !cover_mode) {
1170 bad_properties.push_back(nid_en_and_not_a);
1171 } else {
1172 if (cover_mode) {
1173 infof("bad %d%s\n", nid_en_and_not_a, getinfo(cell, true).c_str());
1174 } else {
1175 int nid = next_nid++;
1176 btorf("%d bad %d%s\n", nid, nid_en_and_not_a, getinfo(cell, true).c_str());
1177 }
1178 }
1179
1180 btorf_pop(log_id(cell));
1181 }
1182
1183 if (cell->type == ID($cover) && cover_mode)
1184 {
1185 btorf_push(log_id(cell));
1186
1187 int sid = get_bv_sid(1);
1188 int nid_a = get_sig_nid(cell->getPort(ID::A));
1189 int nid_en = get_sig_nid(cell->getPort(ID::EN));
1190 int nid_en_and_a = next_nid++;
1191
1192 btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a);
1193
1194 if (single_bad) {
1195 bad_properties.push_back(nid_en_and_a);
1196 } else {
1197 int nid = next_nid++;
1198 btorf("%d bad %d%s\n", nid, nid_en_and_a, getinfo(cell, true).c_str());
1199 }
1200
1201 btorf_pop(log_id(cell));
1202 }
1203 }
1204
1205 for (auto wire : module->wires())
1206 {
1207 if (wire->port_id || wire->name[0] == '$')
1208 continue;
1209
1210 btorf_push(stringf("wire %s", log_id(wire)));
1211
1212 int sid = get_bv_sid(GetSize(wire));
1213 int nid = get_sig_nid(sigmap(wire));
1214
1215 if (statewires.count(wire))
1216 continue;
1217
1218 int this_nid = next_nid++;
1219 btorf("%d uext %d %d %d%s\n", this_nid, sid, nid, 0, getinfo(wire).c_str());
1220
1221 btorf_pop(stringf("wire %s", log_id(wire)));
1222 continue;
1223 }
1224
1225 while (!ff_todo.empty() || !mem_todo.empty())
1226 {
1227 vector<pair<int, Cell*>> todo;
1228 todo.swap(ff_todo);
1229
1230 for (auto &it : todo)
1231 {
1232 int nid = it.first;
1233 Cell *cell = it.second;
1234
1235 btorf_push(stringf("next %s", log_id(cell)));
1236
1237 SigSpec sig = sigmap(cell->getPort(ID::D));
1238 int nid_q = get_sig_nid(sig);
1239 int sid = get_bv_sid(GetSize(sig));
1240 btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());
1241
1242 btorf_pop(stringf("next %s", log_id(cell)));
1243 }
1244
1245 vector<pair<int, Mem*>> mtodo;
1246 mtodo.swap(mem_todo);
1247
1248 for (auto &it : mtodo)
1249 {
1250 int nid = it.first;
1251 Mem *mem = it.second;
1252
1253 btorf_push(stringf("next %s", log_id(mem->memid)));
1254
1255 int abits = ceil_log2(mem->size);
1256
1257 int data_sid = get_bv_sid(mem->width);
1258 int bool_sid = get_bv_sid(1);
1259 int sid = get_mem_sid(abits, mem->width);
1260 int nid_head = nid;
1261
1262 for (auto &port : mem->wr_ports)
1263 {
1264 SigSpec wa = port.addr;
1265 wa.extend_u0(abits);
1266
1267 int wa_nid = get_sig_nid(wa);
1268 int wd_nid = get_sig_nid(port.data);
1269 int we_nid = get_sig_nid(port.en);
1270
1271 int nid2 = next_nid++;
1272 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
1273
1274 int nid3 = next_nid++;
1275 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
1276
1277 int nid4 = next_nid++;
1278 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
1279
1280 int nid5 = next_nid++;
1281 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
1282
1283 int nid6 = next_nid++;
1284 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
1285
1286 int nid7 = next_nid++;
1287 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
1288
1289 int nid8 = next_nid++;
1290 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
1291
1292 int nid9 = next_nid++;
1293 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
1294
1295 nid_head = nid9;
1296 }
1297
1298 int nid2 = next_nid++;
1299 btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, (mem->cell ? getinfo(mem->cell) : getinfo(mem->mem)).c_str());
1300
1301 btorf_pop(stringf("next %s", log_id(mem->memid)));
1302 }
1303 }
1304
1305 while (!bad_properties.empty())
1306 {
1307 vector<int> todo;
1308 bad_properties.swap(todo);
1309
1310 int sid = get_bv_sid(1);
1311 int cursor = 0;
1312
1313 while (cursor+1 < GetSize(todo))
1314 {
1315 int nid_a = todo[cursor++];
1316 int nid_b = todo[cursor++];
1317 int nid = next_nid++;
1318
1319 bad_properties.push_back(nid);
1320 btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
1321 }
1322
1323 if (!bad_properties.empty()) {
1324 if (cursor < GetSize(todo))
1325 bad_properties.push_back(todo[cursor++]);
1326 log_assert(cursor == GetSize(todo));
1327 } else {
1328 int nid = next_nid++;
1329 log_assert(cursor == 0);
1330 log_assert(GetSize(todo) == 1);
1331 btorf("%d bad %d\n", nid, todo[cursor]);
1332 }
1333 }
1334
1335 if (!info_filename.empty())
1336 {
1337 for (auto &it : info_clocks)
1338 {
1339 switch (it.second)
1340 {
1341 case 1:
1342 infof("posedge %d\n", it.first);
1343 break;
1344 case 2:
1345 infof("negedge %d\n", it.first);
1346 break;
1347 case 3:
1348 infof("event %d\n", it.first);
1349 break;
1350 default:
1351 log_abort();
1352 }
1353 }
1354
1355 std::ofstream f;
1356 f.open(info_filename.c_str(), std::ofstream::trunc);
1357 if (f.fail())
1358 log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno));
1359 for (auto &it : info_lines)
1360 f << it;
1361 f.close();
1362 }
1363 }
1364 };
1365
1366 struct BtorBackend : public Backend {
1367 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1368 void help() override
1369 {
1370 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1371 log("\n");
1372 log(" write_btor [options] [filename]\n");
1373 log("\n");
1374 log("Write a BTOR description of the current design.\n");
1375 log("\n");
1376 log(" -v\n");
1377 log(" Add comments and indentation to BTOR output file\n");
1378 log("\n");
1379 log(" -s\n");
1380 log(" Output only a single bad property for all asserts\n");
1381 log("\n");
1382 log(" -c\n");
1383 log(" Output cover properties using 'bad' statements instead of asserts\n");
1384 log("\n");
1385 log(" -i <filename>\n");
1386 log(" Create additional info file with auxiliary information\n");
1387 log("\n");
1388 log(" -x\n");
1389 log(" Output symbols for internal netnames (starting with '$')\n");
1390 log("\n");
1391 }
1392 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
1393 {
1394 bool verbose = false, single_bad = false, cover_mode = false, print_internal_names = false;
1395 string info_filename;
1396
1397 log_header(design, "Executing BTOR backend.\n");
1398
1399 size_t argidx;
1400 for (argidx = 1; argidx < args.size(); argidx++)
1401 {
1402 if (args[argidx] == "-v") {
1403 verbose = true;
1404 continue;
1405 }
1406 if (args[argidx] == "-s") {
1407 single_bad = true;
1408 continue;
1409 }
1410 if (args[argidx] == "-c") {
1411 cover_mode = true;
1412 continue;
1413 }
1414 if (args[argidx] == "-i" && argidx+1 < args.size()) {
1415 info_filename = args[++argidx];
1416 continue;
1417 }
1418 if (args[argidx] == "-x") {
1419 print_internal_names = true;
1420 continue;
1421 }
1422 break;
1423 }
1424 extra_args(f, filename, args, argidx);
1425
1426 RTLIL::Module *topmod = design->top_module();
1427
1428 if (topmod == nullptr)
1429 log_cmd_error("No top module found.\n");
1430
1431 *f << stringf("; BTOR description generated by %s for module %s.\n",
1432 yosys_version_str, log_id(topmod));
1433
1434 BtorWorker(*f, topmod, verbose, single_bad, cover_mode, print_internal_names, info_filename);
1435
1436 *f << stringf("; end of yosys output\n");
1437 }
1438 } BtorBackend;
1439
1440 PRIVATE_NAMESPACE_END