2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 // [[CITE]] Btor2 , BtorMC and Boolector 3.0
21 // Aina Niemetz, Mathias Preiner, Clifford Wolf, Armin Biere
22 // Computer Aided Verification - 30th International Conference, CAV 2018
23 // https://cs.stanford.edu/people/niemetz/publication/2018/niemetzpreinerwolfbiere-cav18/
25 #include "kernel/rtlil.h"
26 #include "kernel/register.h"
27 #include "kernel/sigtools.h"
28 #include "kernel/celltypes.h"
29 #include "kernel/log.h"
33 PRIVATE_NAMESPACE_BEGIN
39 RTLIL::Module
*module
;
44 int initstate_nid
= -1;
47 dict
<int, int> sorts_bv
;
49 // (<address-width>, <data-width>) => <sid>
50 dict
<pair
<int, int>, int> sorts_mem
;
52 // SigBit => (<nid>, <bitidx>)
53 dict
<SigBit
, pair
<int, int>> bit_nid
;
56 dict
<int, int> nid_width
;
59 dict
<SigSpec
, int> sig_nid
;
61 // bit to driving cell
62 dict
<SigBit
, Cell
*> bit_cell
;
65 dict
<Const
, int> consts
;
67 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
68 vector
<pair
<int, Cell
*>> ff_todo
;
70 pool
<Cell
*> cell_recursion_guard
;
71 vector
<int> bad_properties
;
72 dict
<SigBit
, bool> initbits
;
73 pool
<Wire
*> statewires
;
76 void btorf(const char *fmt
, ...)
80 f
<< indent
<< vstringf(fmt
, ap
);
84 void btorf_push(const string
&id
)
87 f
<< indent
<< stringf(" ; begin %s\n", id
.c_str());
92 void btorf_pop(const string
&id
)
95 indent
= indent
.substr(4);
96 f
<< indent
<< stringf(" ; end %s\n", id
.c_str());
100 int get_bv_sid(int width
)
102 if (sorts_bv
.count(width
) == 0) {
103 int nid
= next_nid
++;
104 btorf("%d sort bitvec %d\n", nid
, width
);
105 sorts_bv
[width
] = nid
;
107 return sorts_bv
.at(width
);
110 int get_mem_sid(int abits
, int dbits
)
112 pair
<int, int> key(abits
, dbits
);
113 if (sorts_mem
.count(key
) == 0) {
114 int addr_sid
= get_bv_sid(abits
);
115 int data_sid
= get_bv_sid(dbits
);
116 int nid
= next_nid
++;
117 btorf("%d sort array %d %d\n", nid
, addr_sid
, data_sid
);
118 sorts_mem
[key
] = nid
;
120 return sorts_mem
.at(key
);
123 void add_nid_sig(int nid
, const SigSpec
&sig
)
126 f
<< indent
<< stringf("; %d %s\n", nid
, log_signal(sig
));
128 for (int i
= 0; i
< GetSize(sig
); i
++)
129 bit_nid
[sig
[i
]] = make_pair(nid
, i
);
132 nid_width
[nid
] = GetSize(sig
);
135 void export_cell(Cell
*cell
)
137 if (cell_recursion_guard
.count(cell
)) {
139 for (auto c
: cell_recursion_guard
)
140 cell_list
+= stringf("\n %s", log_id(c
));
141 log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell
), cell_list
.c_str());
144 cell_recursion_guard
.insert(cell
);
145 btorf_push(log_id(cell
));
147 if (cell
->type
.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
148 "$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
151 if (cell
->type
== "$add") btor_op
= "add";
152 if (cell
->type
== "$sub") btor_op
= "sub";
153 if (cell
->type
== "$mul") btor_op
= "mul";
154 if (cell
->type
.in("$shl", "$sshl")) btor_op
= "sll";
155 if (cell
->type
== "$shr") btor_op
= "srl";
156 if (cell
->type
== "$sshr") btor_op
= "sra";
157 if (cell
->type
.in("$shift", "$shiftx")) btor_op
= "shift";
158 if (cell
->type
.in("$and", "$_AND_")) btor_op
= "and";
159 if (cell
->type
.in("$or", "$_OR_")) btor_op
= "or";
160 if (cell
->type
.in("$xor", "$_XOR_")) btor_op
= "xor";
161 if (cell
->type
== "$concat") btor_op
= "concat";
162 if (cell
->type
== "$_NAND_") btor_op
= "nand";
163 if (cell
->type
== "$_NOR_") btor_op
= "nor";
164 if (cell
->type
.in("$xnor", "$_XNOR_")) btor_op
= "xnor";
165 log_assert(!btor_op
.empty());
167 int width
= GetSize(cell
->getPort("\\Y"));
168 width
= std::max(width
, GetSize(cell
->getPort("\\A")));
169 width
= std::max(width
, GetSize(cell
->getPort("\\B")));
171 bool a_signed
= cell
->hasParam("\\A_SIGNED") ? cell
->getParam("\\A_SIGNED").as_bool() : false;
172 bool b_signed
= cell
->hasParam("\\B_SIGNED") ? cell
->getParam("\\B_SIGNED").as_bool() : false;
174 if (btor_op
== "shift" && !b_signed
)
177 if (cell
->type
.in("$shl", "$sshl", "$shr", "$sshr"))
180 if (cell
->type
== "$sshr" && !a_signed
)
183 int sid
= get_bv_sid(width
);
186 if (btor_op
== "shift")
188 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, false);
189 int nid_b
= get_sig_nid(cell
->getPort("\\B"), width
, b_signed
);
191 int nid_r
= next_nid
++;
192 btorf("%d srl %d %d %d\n", nid_r
, sid
, nid_a
, nid_b
);
194 int nid_b_neg
= next_nid
++;
195 btorf("%d neg %d %d\n", nid_b_neg
, sid
, nid_b
);
197 int nid_l
= next_nid
++;
198 btorf("%d sll %d %d %d\n", nid_l
, sid
, nid_a
, nid_b_neg
);
200 int sid_bit
= get_bv_sid(1);
201 int nid_zero
= get_sig_nid(Const(0, width
));
202 int nid_b_ltz
= next_nid
++;
203 btorf("%d slt %d %d %d\n", nid_b_ltz
, sid_bit
, nid_b
, nid_zero
);
206 btorf("%d ite %d %d %d %d\n", nid
, sid
, nid_b_ltz
, nid_l
, nid_r
);
210 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, a_signed
);
211 int nid_b
= get_sig_nid(cell
->getPort("\\B"), width
, b_signed
);
214 btorf("%d %s %d %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
, nid_b
);
217 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
219 if (GetSize(sig
) < width
) {
220 int sid
= get_bv_sid(GetSize(sig
));
221 int nid2
= next_nid
++;
222 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, GetSize(sig
)-1);
226 add_nid_sig(nid
, sig
);
230 if (cell
->type
.in("$div", "$mod"))
233 if (cell
->type
== "$div") btor_op
= "div";
234 if (cell
->type
== "$mod") btor_op
= "rem";
235 log_assert(!btor_op
.empty());
237 int width
= GetSize(cell
->getPort("\\Y"));
238 width
= std::max(width
, GetSize(cell
->getPort("\\A")));
239 width
= std::max(width
, GetSize(cell
->getPort("\\B")));
241 bool a_signed
= cell
->hasParam("\\A_SIGNED") ? cell
->getParam("\\A_SIGNED").as_bool() : false;
242 bool b_signed
= cell
->hasParam("\\B_SIGNED") ? cell
->getParam("\\B_SIGNED").as_bool() : false;
244 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, a_signed
);
245 int nid_b
= get_sig_nid(cell
->getPort("\\B"), width
, b_signed
);
247 int sid
= get_bv_sid(width
);
248 int nid
= next_nid
++;
249 btorf("%d %c%s %d %d %d\n", nid
, a_signed
|| b_signed
? 's' : 'u', btor_op
.c_str(), sid
, nid_a
, nid_b
);
251 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
253 if (GetSize(sig
) < width
) {
254 int sid
= get_bv_sid(GetSize(sig
));
255 int nid2
= next_nid
++;
256 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, GetSize(sig
)-1);
260 add_nid_sig(nid
, sig
);
264 if (cell
->type
.in("$_ANDNOT_", "$_ORNOT_"))
266 int sid
= get_bv_sid(1);
267 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
268 int nid_b
= get_sig_nid(cell
->getPort("\\B"));
270 int nid1
= next_nid
++;
271 int nid2
= next_nid
++;
273 if (cell
->type
== "$_ANDNOT_") {
274 btorf("%d not %d %d\n", nid1
, sid
, nid_b
);
275 btorf("%d and %d %d %d\n", nid2
, sid
, nid_a
, nid1
);
278 if (cell
->type
== "$_ORNOT_") {
279 btorf("%d not %d %d\n", nid1
, sid
, nid_b
);
280 btorf("%d or %d %d %d\n", nid2
, sid
, nid_a
, nid1
);
283 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
284 add_nid_sig(nid2
, sig
);
288 if (cell
->type
.in("$_OAI3_", "$_AOI3_"))
290 int sid
= get_bv_sid(1);
291 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
292 int nid_b
= get_sig_nid(cell
->getPort("\\B"));
293 int nid_c
= get_sig_nid(cell
->getPort("\\C"));
295 int nid1
= next_nid
++;
296 int nid2
= next_nid
++;
297 int nid3
= next_nid
++;
299 if (cell
->type
== "$_OAI3_") {
300 btorf("%d or %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
301 btorf("%d and %d %d %d\n", nid2
, sid
, nid1
, nid_c
);
302 btorf("%d not %d %d\n", nid3
, sid
, nid2
);
305 if (cell
->type
== "$_AOI3_") {
306 btorf("%d and %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
307 btorf("%d or %d %d %d\n", nid2
, sid
, nid1
, nid_c
);
308 btorf("%d not %d %d\n", nid3
, sid
, nid2
);
311 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
312 add_nid_sig(nid3
, sig
);
316 if (cell
->type
.in("$_OAI4_", "$_AOI4_"))
318 int sid
= get_bv_sid(1);
319 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
320 int nid_b
= get_sig_nid(cell
->getPort("\\B"));
321 int nid_c
= get_sig_nid(cell
->getPort("\\C"));
322 int nid_d
= get_sig_nid(cell
->getPort("\\D"));
324 int nid1
= next_nid
++;
325 int nid2
= next_nid
++;
326 int nid3
= next_nid
++;
327 int nid4
= next_nid
++;
329 if (cell
->type
== "$_OAI4_") {
330 btorf("%d or %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
331 btorf("%d or %d %d %d\n", nid2
, sid
, nid_c
, nid_d
);
332 btorf("%d and %d %d %d\n", nid3
, sid
, nid1
, nid2
);
333 btorf("%d not %d %d\n", nid4
, sid
, nid3
);
336 if (cell
->type
== "$_AOI4_") {
337 btorf("%d and %d %d %d\n", nid1
, sid
, nid_a
, nid_b
);
338 btorf("%d and %d %d %d\n", nid2
, sid
, nid_c
, nid_d
);
339 btorf("%d or %d %d %d\n", nid3
, sid
, nid1
, nid2
);
340 btorf("%d not %d %d\n", nid4
, sid
, nid3
);
343 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
344 add_nid_sig(nid4
, sig
);
348 if (cell
->type
.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt"))
351 if (cell
->type
== "$lt") btor_op
= "lt";
352 if (cell
->type
== "$le") btor_op
= "lte";
353 if (cell
->type
.in("$eq", "$eqx")) btor_op
= "eq";
354 if (cell
->type
.in("$ne", "$nex")) btor_op
= "neq";
355 if (cell
->type
== "$ge") btor_op
= "gte";
356 if (cell
->type
== "$gt") btor_op
= "gt";
357 log_assert(!btor_op
.empty());
360 width
= std::max(width
, GetSize(cell
->getPort("\\A")));
361 width
= std::max(width
, GetSize(cell
->getPort("\\B")));
363 bool a_signed
= cell
->hasParam("\\A_SIGNED") ? cell
->getParam("\\A_SIGNED").as_bool() : false;
364 bool b_signed
= cell
->hasParam("\\B_SIGNED") ? cell
->getParam("\\B_SIGNED").as_bool() : false;
366 int sid
= get_bv_sid(1);
367 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, a_signed
);
368 int nid_b
= get_sig_nid(cell
->getPort("\\B"), width
, b_signed
);
370 int nid
= next_nid
++;
371 if (cell
->type
.in("$lt", "$le", "$ge", "$gt")) {
372 btorf("%d %c%s %d %d %d\n", nid
, a_signed
|| b_signed
? 's' : 'u', btor_op
.c_str(), sid
, nid_a
, nid_b
);
374 btorf("%d %s %d %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
, nid_b
);
377 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
379 if (GetSize(sig
) > 1) {
380 int sid
= get_bv_sid(GetSize(sig
));
381 int nid2
= next_nid
++;
382 btorf("%d uext %d %d %d\n", nid2
, sid
, nid
, GetSize(sig
) - 1);
386 add_nid_sig(nid
, sig
);
390 if (cell
->type
.in("$not", "$neg", "$_NOT_"))
393 if (cell
->type
.in("$not", "$_NOT_")) btor_op
= "not";
394 if (cell
->type
== "$neg") btor_op
= "neg";
395 log_assert(!btor_op
.empty());
397 int width
= GetSize(cell
->getPort("\\Y"));
398 width
= std::max(width
, GetSize(cell
->getPort("\\A")));
400 bool a_signed
= cell
->hasParam("\\A_SIGNED") ? cell
->getParam("\\A_SIGNED").as_bool() : false;
402 int sid
= get_bv_sid(width
);
403 int nid_a
= get_sig_nid(cell
->getPort("\\A"), width
, a_signed
);
405 int nid
= next_nid
++;
406 btorf("%d %s %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
);
408 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
410 if (GetSize(sig
) < width
) {
411 int sid
= get_bv_sid(GetSize(sig
));
412 int nid2
= next_nid
++;
413 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, GetSize(sig
)-1);
417 add_nid_sig(nid
, sig
);
421 if (cell
->type
.in("$logic_and", "$logic_or", "$logic_not"))
424 if (cell
->type
== "$logic_and") btor_op
= "and";
425 if (cell
->type
== "$logic_or") btor_op
= "or";
426 if (cell
->type
== "$logic_not") btor_op
= "not";
427 log_assert(!btor_op
.empty());
429 int sid
= get_bv_sid(1);
430 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
431 int nid_b
= btor_op
!= "not" ? get_sig_nid(cell
->getPort("\\B")) : 0;
433 if (GetSize(cell
->getPort("\\A")) > 1) {
434 int nid_red_a
= next_nid
++;
435 btorf("%d redor %d %d\n", nid_red_a
, sid
, nid_a
);
439 if (btor_op
!= "not" && GetSize(cell
->getPort("\\B")) > 1) {
440 int nid_red_b
= next_nid
++;
441 btorf("%d redor %d %d\n", nid_red_b
, sid
, nid_b
);
445 int nid
= next_nid
++;
446 if (btor_op
!= "not")
447 btorf("%d %s %d %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
, nid_b
);
449 btorf("%d %s %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
);
451 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
453 if (GetSize(sig
) > 1) {
454 int sid
= get_bv_sid(GetSize(sig
));
455 int zeros_nid
= get_sig_nid(Const(0, GetSize(sig
)-1));
456 int nid2
= next_nid
++;
457 btorf("%d concat %d %d %d\n", nid2
, sid
, zeros_nid
, nid
);
461 add_nid_sig(nid
, sig
);
465 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor"))
468 if (cell
->type
== "$reduce_and") btor_op
= "redand";
469 if (cell
->type
.in("$reduce_or", "$reduce_bool")) btor_op
= "redor";
470 if (cell
->type
.in("$reduce_xor", "$reduce_xnor")) btor_op
= "redxor";
471 log_assert(!btor_op
.empty());
473 int sid
= get_bv_sid(1);
474 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
476 int nid
= next_nid
++;
477 btorf("%d %s %d %d\n", nid
, btor_op
.c_str(), sid
, nid_a
);
479 if (cell
->type
== "$reduce_xnor") {
480 int nid2
= next_nid
++;
481 btorf("%d not %d %d %d\n", nid2
, sid
, nid
);
485 SigSpec sig
= sigmap(cell
->getPort("\\Y"));
487 if (GetSize(sig
) > 1) {
488 int sid
= get_bv_sid(GetSize(sig
));
489 int zeros_nid
= get_sig_nid(Const(0, GetSize(sig
)-1));
490 int nid2
= next_nid
++;
491 btorf("%d concat %d %d %d\n", nid2
, sid
, zeros_nid
, nid
);
495 add_nid_sig(nid
, sig
);
499 if (cell
->type
.in("$mux", "$_MUX_"))
501 SigSpec sig_a
= sigmap(cell
->getPort("\\A"));
502 SigSpec sig_b
= sigmap(cell
->getPort("\\B"));
503 SigSpec sig_s
= sigmap(cell
->getPort("\\S"));
504 SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
506 int nid_a
= get_sig_nid(sig_a
);
507 int nid_b
= get_sig_nid(sig_b
);
508 int nid_s
= get_sig_nid(sig_s
);
510 int sid
= get_bv_sid(GetSize(sig_y
));
511 int nid
= next_nid
++;
512 btorf("%d ite %d %d %d %d\n", nid
, sid
, nid_s
, nid_b
, nid_a
);
514 add_nid_sig(nid
, sig_y
);
518 if (cell
->type
== "$pmux")
520 SigSpec sig_a
= sigmap(cell
->getPort("\\A"));
521 SigSpec sig_b
= sigmap(cell
->getPort("\\B"));
522 SigSpec sig_s
= sigmap(cell
->getPort("\\S"));
523 SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
525 int width
= GetSize(sig_a
);
526 int sid
= get_bv_sid(width
);
527 int nid
= get_sig_nid(sig_a
);
529 for (int i
= 0; i
< GetSize(sig_s
); i
++) {
530 int nid_b
= get_sig_nid(sig_b
.extract(i
*width
, width
));
531 int nid_s
= get_sig_nid(sig_s
.extract(i
));
532 int nid2
= next_nid
++;
533 btorf("%d ite %d %d %d %d\n", nid2
, sid
, nid_s
, nid_b
, nid
);
537 add_nid_sig(nid
, sig_y
);
541 if (cell
->type
.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N", "$_FF_"))
543 SigSpec sig_d
= sigmap(cell
->getPort("\\D"));
544 SigSpec sig_q
= sigmap(cell
->getPort("\\Q"));
548 if (sig_q
.is_wire()) {
549 Wire
*w
= sig_q
.as_wire();
550 if (w
->port_id
== 0) {
551 statewires
.insert(w
);
557 for (int i
= 0; i
< GetSize(sig_q
); i
++)
558 if (initbits
.count(sig_q
[i
]))
559 initval
.bits
.push_back(initbits
.at(sig_q
[i
]) ? State::S1
: State::S0
);
561 initval
.bits
.push_back(State::Sx
);
563 int nid_init_val
= -1;
565 if (!initval
.is_fully_undef())
566 nid_init_val
= get_sig_nid(initval
);
568 int sid
= get_bv_sid(GetSize(sig_q
));
569 int nid
= next_nid
++;
572 btorf("%d state %d\n", nid
, sid
);
574 btorf("%d state %d %s\n", nid
, sid
, log_id(symbol
));
576 if (nid_init_val
>= 0) {
577 int nid_init
= next_nid
++;
579 btorf("; initval = %s\n", log_signal(initval
));
580 btorf("%d init %d %d %d\n", nid_init
, sid
, nid
, nid_init_val
);
583 ff_todo
.push_back(make_pair(nid
, cell
));
584 add_nid_sig(nid
, sig_q
);
588 if (cell
->type
.in("$anyconst", "$anyseq"))
590 SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
592 int sid
= get_bv_sid(GetSize(sig_y
));
593 int nid
= next_nid
++;
595 btorf("%d state %d\n", nid
, sid
);
597 if (cell
->type
== "$anyconst") {
598 int nid2
= next_nid
++;
599 btorf("%d next %d %d %d\n", nid2
, sid
, nid
, nid
);
602 add_nid_sig(nid
, sig_y
);
606 if (cell
->type
== "$initstate")
608 SigSpec sig_y
= sigmap(cell
->getPort("\\Y"));
610 if (initstate_nid
< 0)
612 int sid
= get_bv_sid(1);
613 int one_nid
= get_sig_nid(Const(1, 1));
614 int zero_nid
= get_sig_nid(Const(0, 1));
615 initstate_nid
= next_nid
++;
616 btorf("%d state %d\n", initstate_nid
, sid
);
617 btorf("%d init %d %d %d\n", next_nid
++, sid
, initstate_nid
, one_nid
);
618 btorf("%d next %d %d %d\n", next_nid
++, sid
, initstate_nid
, zero_nid
);
621 add_nid_sig(initstate_nid
, sig_y
);
625 if (cell
->type
== "$mem")
627 int abits
= cell
->getParam("\\ABITS").as_int();
628 int width
= cell
->getParam("\\WIDTH").as_int();
629 int nwords
= cell
->getParam("\\SIZE").as_int();
630 int rdports
= cell
->getParam("\\RD_PORTS").as_int();
631 int wrports
= cell
->getParam("\\WR_PORTS").as_int();
633 Const wr_clk_en
= cell
->getParam("\\WR_CLK_ENABLE");
634 Const rd_clk_en
= cell
->getParam("\\RD_CLK_ENABLE");
636 bool asyncwr
= wr_clk_en
.is_fully_zero();
638 if (!asyncwr
&& !wr_clk_en
.is_fully_ones())
639 log_error("Memory %s.%s has mixed async/sync write ports.\n",
640 log_id(module
), log_id(cell
));
642 if (!rd_clk_en
.is_fully_zero())
643 log_error("Memory %s.%s has sync read ports.\n",
644 log_id(module
), log_id(cell
));
646 SigSpec sig_rd_addr
= sigmap(cell
->getPort("\\RD_ADDR"));
647 SigSpec sig_rd_data
= sigmap(cell
->getPort("\\RD_DATA"));
649 SigSpec sig_wr_addr
= sigmap(cell
->getPort("\\WR_ADDR"));
650 SigSpec sig_wr_data
= sigmap(cell
->getPort("\\WR_DATA"));
651 SigSpec sig_wr_en
= sigmap(cell
->getPort("\\WR_EN"));
653 int data_sid
= get_bv_sid(width
);
654 int bool_sid
= get_bv_sid(1);
655 int sid
= get_mem_sid(abits
, width
);
657 Const initdata
= cell
->getParam("\\INIT");
658 initdata
.exts(nwords
*width
);
659 int nid_init_val
= -1;
661 if (!initdata
.is_fully_undef())
663 bool constword
= true;
664 Const firstword
= initdata
.extract(0, width
);
666 for (int i
= 1; i
< nwords
; i
++) {
667 Const thisword
= initdata
.extract(i
*width
, width
);
668 if (thisword
!= firstword
) {
677 btorf("; initval = %s\n", log_signal(firstword
));
678 nid_init_val
= get_sig_nid(firstword
);
682 int nid_init_val
= next_nid
++;
683 btorf("%d state %d\n", nid_init_val
, sid
);
685 for (int i
= 0; i
< nwords
; i
++) {
686 Const thisword
= initdata
.extract(i
*width
, width
);
687 if (thisword
.is_fully_undef())
689 Const
thisaddr(i
, abits
);
690 int nid_thisword
= get_sig_nid(thisword
);
691 int nid_thisaddr
= get_sig_nid(thisaddr
);
692 int last_nid_init_val
= nid_init_val
;
693 nid_init_val
= next_nid
++;
695 btorf("; initval[%d] = %s\n", i
, log_signal(thisword
));
696 btorf("%d write %d %d %d %d\n", nid_init_val
, sid
, last_nid_init_val
, nid_thisaddr
, nid_thisword
);
702 int nid
= next_nid
++;
705 if (cell
->name
[0] == '$')
706 btorf("%d state %d\n", nid
, sid
);
708 btorf("%d state %d %s\n", nid
, sid
, log_id(cell
));
710 if (nid_init_val
>= 0)
712 int nid_init
= next_nid
++;
713 btorf("%d init %d %d %d\n", nid_init
, sid
, nid
, nid_init_val
);
718 for (int port
= 0; port
< wrports
; port
++)
720 SigSpec wa
= sig_wr_addr
.extract(port
*abits
, abits
);
721 SigSpec wd
= sig_wr_data
.extract(port
*width
, width
);
722 SigSpec we
= sig_wr_en
.extract(port
*width
, width
);
724 int wa_nid
= get_sig_nid(wa
);
725 int wd_nid
= get_sig_nid(wd
);
726 int we_nid
= get_sig_nid(we
);
728 int nid2
= next_nid
++;
729 btorf("%d read %d %d %d\n", nid2
, data_sid
, nid_head
, wa_nid
);
731 int nid3
= next_nid
++;
732 btorf("%d not %d %d\n", nid3
, data_sid
, we_nid
);
734 int nid4
= next_nid
++;
735 btorf("%d and %d %d %d\n", nid4
, data_sid
, nid2
, nid3
);
737 int nid5
= next_nid
++;
738 btorf("%d and %d %d %d\n", nid5
, data_sid
, wd_nid
, we_nid
);
740 int nid6
= next_nid
++;
741 btorf("%d or %d %d %d\n", nid6
, data_sid
, nid5
, nid4
);
743 int nid7
= next_nid
++;
744 btorf("%d write %d %d %d %d\n", nid7
, sid
, nid_head
, wa_nid
, nid6
);
746 int nid8
= next_nid
++;
747 btorf("%d redor %d %d\n", nid8
, bool_sid
, we_nid
);
749 int nid9
= next_nid
++;
750 btorf("%d ite %d %d %d %d\n", nid9
, sid
, nid8
, nid7
, nid_head
);
756 for (int port
= 0; port
< rdports
; port
++)
758 SigSpec ra
= sig_rd_addr
.extract(port
*abits
, abits
);
759 SigSpec rd
= sig_rd_data
.extract(port
*width
, width
);
761 int ra_nid
= get_sig_nid(ra
);
762 int rd_nid
= next_nid
++;
764 btorf("%d read %d %d %d\n", rd_nid
, data_sid
, nid_head
, ra_nid
);
766 add_nid_sig(rd_nid
, rd
);
771 ff_todo
.push_back(make_pair(nid
, cell
));
775 int nid2
= next_nid
++;
776 btorf("%d next %d %d %d\n", nid2
, sid
, nid
, nid_head
);
782 log_error("Unsupported cell type: %s (%s)\n", log_id(cell
->type
), log_id(cell
));
785 btorf_pop(log_id(cell
));
786 cell_recursion_guard
.erase(cell
);
789 int get_sig_nid(SigSpec sig
, int to_width
= -1, bool is_signed
= false)
795 if (bit
== State::Sx
)
801 SigSpec sig_mask_undef
, sig_noundef
;
802 int first_undef
= -1;
804 for (int i
= 0; i
< GetSize(sig
); i
++)
805 if (sig
[i
] == State::Sx
) {
808 sig_mask_undef
.append(State::S1
);
809 sig_noundef
.append(State::S0
);
811 sig_mask_undef
.append(State::S0
);
812 sig_noundef
.append(sig
[i
]);
815 if (to_width
< 0 || first_undef
< to_width
)
817 int sid
= get_bv_sid(GetSize(sig
));
819 int nid_input
= next_nid
++;
820 btorf("%d input %d\n", nid_input
, sid
);
822 int nid_masked_input
;
823 if (sig_mask_undef
.is_fully_ones()) {
824 nid_masked_input
= nid_input
;
826 int nid_mask_undef
= get_sig_nid(sig_mask_undef
);
827 nid_masked_input
= next_nid
++;
828 btorf("%d and %d %d %d\n", nid_masked_input
, sid
, nid_input
, nid_mask_undef
);
831 if (sig_noundef
.is_fully_zero()) {
832 nid
= nid_masked_input
;
834 int nid_noundef
= get_sig_nid(sig_noundef
);
836 btorf("%d or %d %d %d\n", nid
, sid
, nid_masked_input
, nid_noundef
);
845 if (sig_nid
.count(sig
) == 0)
848 vector
<pair
<int, int>> nidbits
;
851 for (int i
= 0; i
< GetSize(sig
); i
++)
855 if (bit_nid
.count(bit
) == 0)
857 if (bit
.wire
== nullptr)
861 while (i
+GetSize(c
) < GetSize(sig
) && sig
[i
+GetSize(c
)].wire
== nullptr)
862 c
.bits
.push_back(sig
[i
+GetSize(c
)].data
);
864 if (consts
.count(c
) == 0) {
865 int sid
= get_bv_sid(GetSize(c
));
866 int nid
= next_nid
++;
867 btorf("%d const %d %s\n", nid
, sid
, c
.as_string().c_str());
869 nid_width
[nid
] = GetSize(c
);
872 int nid
= consts
.at(c
);
874 for (int j
= 0; j
< GetSize(c
); j
++)
875 nidbits
.push_back(make_pair(nid
, j
));
882 if (bit_cell
.count(bit
) == 0)
886 while (i
+GetSize(s
) < GetSize(sig
) && sig
[i
+GetSize(s
)].wire
!= nullptr &&
887 bit_cell
.count(sig
[i
+GetSize(s
)]) == 0)
888 s
.append(sig
[i
+GetSize(s
)]);
890 log_warning("No driver for signal %s.\n", log_signal(s
));
892 int sid
= get_bv_sid(GetSize(s
));
893 int nid
= next_nid
++;
894 btorf("%d input %d %s\n", nid
, sid
);
895 nid_width
[nid
] = GetSize(s
);
902 export_cell(bit_cell
.at(bit
));
903 log_assert(bit_nid
.count(bit
));
908 nidbits
.push_back(bit_nid
.at(bit
));
914 // group bits and emit slice-concat chain
915 for (int i
= 0; i
< GetSize(nidbits
); i
++)
917 int nid2
= nidbits
[i
].first
;
918 int lower
= nidbits
[i
].second
;
921 while (i
+1 < GetSize(nidbits
) && nidbits
[i
+1].first
== nidbits
[i
].first
&&
922 nidbits
[i
+1].second
== nidbits
[i
].second
+1)
927 if (lower
!= 0 || upper
+1 != nid_width
.at(nid2
)) {
928 int sid
= get_bv_sid(upper
-lower
+1);
930 btorf("%d slice %d %d %d %d\n", nid3
, sid
, nid2
, upper
, lower
);
936 int sid
= get_bv_sid(width
+upper
-lower
+1);
938 btorf("%d concat %d %d %d\n", nid4
, sid
, nid3
, nid
);
941 width
+= upper
-lower
+1;
946 nid_width
[nid
] = width
;
949 nid
= sig_nid
.at(sig
);
952 if (to_width
>= 0 && to_width
!= GetSize(sig
))
954 if (to_width
< GetSize(sig
))
956 int sid
= get_bv_sid(to_width
);
957 int nid2
= next_nid
++;
958 btorf("%d slice %d %d %d 0\n", nid2
, sid
, nid
, to_width
-1);
963 int sid
= get_bv_sid(to_width
);
964 int nid2
= next_nid
++;
965 btorf("%d %s %d %d %d\n", nid2
, is_signed
? "sext" : "uext",
966 sid
, nid
, to_width
- GetSize(sig
));
974 BtorWorker(std::ostream
&f
, RTLIL::Module
*module
, bool verbose
, bool single_bad
) :
975 f(f
), sigmap(module
), module(module
), verbose(verbose
), single_bad(single_bad
)
977 btorf_push("inputs");
979 for (auto wire
: module
->wires())
981 if (wire
->attributes
.count("\\init")) {
982 Const attrval
= wire
->attributes
.at("\\init");
983 for (int i
= 0; i
< GetSize(wire
) && i
< GetSize(attrval
); i
++)
984 if (attrval
[i
] == State::S0
|| attrval
[i
] == State::S1
)
985 initbits
[sigmap(SigBit(wire
, i
))] = (attrval
[i
] == State::S1
);
988 if (!wire
->port_id
|| !wire
->port_input
)
991 SigSpec sig
= sigmap(wire
);
992 int sid
= get_bv_sid(GetSize(sig
));
993 int nid
= next_nid
++;
995 btorf("%d input %d %s\n", nid
, sid
, log_id(wire
));
996 add_nid_sig(nid
, sig
);
1001 for (auto cell
: module
->cells())
1002 for (auto &conn
: cell
->connections())
1004 if (!cell
->output(conn
.first
))
1007 for (auto bit
: sigmap(conn
.second
))
1008 bit_cell
[bit
] = cell
;
1011 for (auto wire
: module
->wires())
1013 if (!wire
->port_id
|| !wire
->port_output
)
1016 btorf_push(stringf("output %s", log_id(wire
)));
1018 int nid
= get_sig_nid(wire
);
1019 btorf("%d output %d %s\n", next_nid
++, nid
, log_id(wire
));
1021 btorf_pop(stringf("output %s", log_id(wire
)));
1024 for (auto cell
: module
->cells())
1026 if (cell
->type
== "$assume")
1028 btorf_push(log_id(cell
));
1030 int sid
= get_bv_sid(1);
1031 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
1032 int nid_en
= get_sig_nid(cell
->getPort("\\EN"));
1033 int nid_not_en
= next_nid
++;
1034 int nid_a_or_not_en
= next_nid
++;
1035 int nid
= next_nid
++;
1037 btorf("%d not %d %d\n", nid_not_en
, sid
, nid_en
);
1038 btorf("%d or %d %d %d\n", nid_a_or_not_en
, sid
, nid_a
, nid_not_en
);
1039 btorf("%d constraint %d\n", nid
, nid_a_or_not_en
);
1041 btorf_pop(log_id(cell
));
1044 if (cell
->type
== "$assert")
1046 btorf_push(log_id(cell
));
1048 int sid
= get_bv_sid(1);
1049 int nid_a
= get_sig_nid(cell
->getPort("\\A"));
1050 int nid_en
= get_sig_nid(cell
->getPort("\\EN"));
1051 int nid_not_a
= next_nid
++;
1052 int nid_en_and_not_a
= next_nid
++;
1054 btorf("%d not %d %d\n", nid_not_a
, sid
, nid_a
);
1055 btorf("%d and %d %d %d\n", nid_en_and_not_a
, sid
, nid_en
, nid_not_a
);
1058 bad_properties
.push_back(nid_en_and_not_a
);
1060 int nid
= next_nid
++;
1061 btorf("%d bad %d\n", nid
, nid_en_and_not_a
);
1064 btorf_pop(log_id(cell
));
1068 for (auto wire
: module
->wires())
1070 if (wire
->port_id
|| wire
->name
[0] == '$')
1073 btorf_push(stringf("wire %s", log_id(wire
)));
1075 int sid
= get_bv_sid(GetSize(wire
));
1076 int nid
= get_sig_nid(sigmap(wire
));
1078 if (statewires
.count(wire
))
1081 int this_nid
= next_nid
++;
1082 btorf("%d uext %d %d %d %s\n", this_nid
, sid
, nid
, 0, log_id(wire
));
1084 btorf_pop(stringf("wire %s", log_id(wire
)));
1088 while (!ff_todo
.empty())
1090 vector
<pair
<int, Cell
*>> todo
;
1093 for (auto &it
: todo
)
1096 Cell
*cell
= it
.second
;
1098 btorf_push(stringf("next %s", log_id(cell
)));
1100 if (cell
->type
== "$mem")
1102 int abits
= cell
->getParam("\\ABITS").as_int();
1103 int width
= cell
->getParam("\\WIDTH").as_int();
1104 int wrports
= cell
->getParam("\\WR_PORTS").as_int();
1106 SigSpec sig_wr_addr
= sigmap(cell
->getPort("\\WR_ADDR"));
1107 SigSpec sig_wr_data
= sigmap(cell
->getPort("\\WR_DATA"));
1108 SigSpec sig_wr_en
= sigmap(cell
->getPort("\\WR_EN"));
1110 int data_sid
= get_bv_sid(width
);
1111 int bool_sid
= get_bv_sid(1);
1112 int sid
= get_mem_sid(abits
, width
);
1115 for (int port
= 0; port
< wrports
; port
++)
1117 SigSpec wa
= sig_wr_addr
.extract(port
*abits
, abits
);
1118 SigSpec wd
= sig_wr_data
.extract(port
*width
, width
);
1119 SigSpec we
= sig_wr_en
.extract(port
*width
, width
);
1121 int wa_nid
= get_sig_nid(wa
);
1122 int wd_nid
= get_sig_nid(wd
);
1123 int we_nid
= get_sig_nid(we
);
1125 int nid2
= next_nid
++;
1126 btorf("%d read %d %d %d\n", nid2
, data_sid
, nid_head
, wa_nid
);
1128 int nid3
= next_nid
++;
1129 btorf("%d not %d %d\n", nid3
, data_sid
, we_nid
);
1131 int nid4
= next_nid
++;
1132 btorf("%d and %d %d %d\n", nid4
, data_sid
, nid2
, nid3
);
1134 int nid5
= next_nid
++;
1135 btorf("%d and %d %d %d\n", nid5
, data_sid
, wd_nid
, we_nid
);
1137 int nid6
= next_nid
++;
1138 btorf("%d or %d %d %d\n", nid6
, data_sid
, nid5
, nid4
);
1140 int nid7
= next_nid
++;
1141 btorf("%d write %d %d %d %d\n", nid7
, sid
, nid_head
, wa_nid
, nid6
);
1143 int nid8
= next_nid
++;
1144 btorf("%d redor %d %d\n", nid8
, bool_sid
, we_nid
);
1146 int nid9
= next_nid
++;
1147 btorf("%d ite %d %d %d %d\n", nid9
, sid
, nid8
, nid7
, nid_head
);
1152 int nid2
= next_nid
++;
1153 btorf("%d next %d %d %d\n", nid2
, sid
, nid
, nid_head
);
1157 SigSpec sig
= sigmap(cell
->getPort("\\D"));
1158 int nid_q
= get_sig_nid(sig
);
1159 int sid
= get_bv_sid(GetSize(sig
));
1160 btorf("%d next %d %d %d\n", next_nid
++, sid
, nid
, nid_q
);
1163 btorf_pop(stringf("next %s", log_id(cell
)));
1167 while (!bad_properties
.empty())
1170 bad_properties
.swap(todo
);
1172 int sid
= get_bv_sid(1);
1175 while (cursor
+1 < GetSize(todo
))
1177 int nid_a
= todo
[cursor
++];
1178 int nid_b
= todo
[cursor
++];
1179 int nid
= next_nid
++;
1181 bad_properties
.push_back(nid
);
1182 btorf("%d or %d %d %d\n", nid
, sid
, nid_a
, nid_b
);
1185 if (!bad_properties
.empty()) {
1186 if (cursor
< GetSize(todo
))
1187 bad_properties
.push_back(todo
[cursor
++]);
1188 log_assert(cursor
== GetSize(todo
));
1190 int nid
= next_nid
++;
1191 log_assert(cursor
== 0);
1192 log_assert(GetSize(todo
) == 1);
1193 btorf("%d bad %d\n", nid
, todo
[cursor
]);
1199 struct BtorBackend
: public Backend
{
1200 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1201 void help() YS_OVERRIDE
1203 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1205 log(" write_btor [options] [filename]\n");
1207 log("Write a BTOR description of the current design.\n");
1210 log(" Add comments and indentation to BTOR output file\n");
1213 log(" Output only a single bad property for all asserts\n");
1216 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1218 bool verbose
= false, single_bad
= false;
1220 log_header(design
, "Executing BTOR backend.\n");
1223 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1225 if (args
[argidx
] == "-v") {
1229 if (args
[argidx
] == "-s") {
1235 extra_args(f
, filename
, args
, argidx
);
1237 RTLIL::Module
*topmod
= design
->top_module();
1239 if (topmod
== nullptr)
1240 log_cmd_error("No top module found.\n");
1242 *f
<< stringf("; BTOR description generated by %s for module %s.\n",
1243 yosys_version_str
, log_id(topmod
));
1245 BtorWorker(*f
, topmod
, verbose
, single_bad
);
1247 *f
<< stringf("; end of yosys output\n");
1251 PRIVATE_NAMESPACE_END