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Merge pull request #736 from whitequark/select_assert_list
[yosys.git] / backends / btor / btor.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
25 #include <string>
26
27 USING_YOSYS_NAMESPACE
28 PRIVATE_NAMESPACE_BEGIN
29
30 struct BtorWorker
31 {
32 std::ostream &f;
33 SigMap sigmap;
34 RTLIL::Module *module;
35 bool verbose;
36 bool single_bad;
37
38 int next_nid = 1;
39 int initstate_nid = -1;
40
41 // <width> => <sid>
42 dict<int, int> sorts_bv;
43
44 // (<address-width>, <data-width>) => <sid>
45 dict<pair<int, int>, int> sorts_mem;
46
47 // SigBit => (<nid>, <bitidx>)
48 dict<SigBit, pair<int, int>> bit_nid;
49
50 // <nid> => <bvwidth>
51 dict<int, int> nid_width;
52
53 // SigSpec => <nid>
54 dict<SigSpec, int> sig_nid;
55
56 // bit to driving cell
57 dict<SigBit, Cell*> bit_cell;
58
59 // nids for constants
60 dict<Const, int> consts;
61
62 // ff inputs that need to be evaluated (<nid>, <ff_cell>)
63 vector<pair<int, Cell*>> ff_todo;
64
65 pool<Cell*> cell_recursion_guard;
66 vector<int> bad_properties;
67 dict<SigBit, bool> initbits;
68 pool<Wire*> statewires;
69 string indent;
70
71 void btorf(const char *fmt, ...)
72 {
73 va_list ap;
74 va_start(ap, fmt);
75 f << indent << vstringf(fmt, ap);
76 va_end(ap);
77 }
78
79 void btorf_push(const string &id)
80 {
81 if (verbose) {
82 f << indent << stringf(" ; begin %s\n", id.c_str());
83 indent += " ";
84 }
85 }
86
87 void btorf_pop(const string &id)
88 {
89 if (verbose) {
90 indent = indent.substr(4);
91 f << indent << stringf(" ; end %s\n", id.c_str());
92 }
93 }
94
95 int get_bv_sid(int width)
96 {
97 if (sorts_bv.count(width) == 0) {
98 int nid = next_nid++;
99 btorf("%d sort bitvec %d\n", nid, width);
100 sorts_bv[width] = nid;
101 }
102 return sorts_bv.at(width);
103 }
104
105 int get_mem_sid(int abits, int dbits)
106 {
107 pair<int, int> key(abits, dbits);
108 if (sorts_mem.count(key) == 0) {
109 int addr_sid = get_bv_sid(abits);
110 int data_sid = get_bv_sid(dbits);
111 int nid = next_nid++;
112 btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
113 sorts_mem[key] = nid;
114 }
115 return sorts_mem.at(key);
116 }
117
118 void add_nid_sig(int nid, const SigSpec &sig)
119 {
120 if (verbose)
121 f << indent << stringf("; %d %s\n", nid, log_signal(sig));
122
123 for (int i = 0; i < GetSize(sig); i++)
124 bit_nid[sig[i]] = make_pair(nid, i);
125
126 sig_nid[sig] = nid;
127 nid_width[nid] = GetSize(sig);
128 }
129
130 void export_cell(Cell *cell)
131 {
132 log_assert(cell_recursion_guard.count(cell) == 0);
133 cell_recursion_guard.insert(cell);
134 btorf_push(log_id(cell));
135
136 if (cell->type.in("$add", "$sub", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
137 "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
138 {
139 string btor_op;
140 if (cell->type == "$add") btor_op = "add";
141 if (cell->type == "$sub") btor_op = "sub";
142 if (cell->type.in("$shl", "$sshl")) btor_op = "sll";
143 if (cell->type == "$shr") btor_op = "srl";
144 if (cell->type == "$sshr") btor_op = "sra";
145 if (cell->type.in("$shift", "$shiftx")) btor_op = "shift";
146 if (cell->type.in("$and", "$_AND_")) btor_op = "and";
147 if (cell->type.in("$or", "$_OR_")) btor_op = "or";
148 if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor";
149 if (cell->type == "$_NAND_") btor_op = "nand";
150 if (cell->type == "$_NOR_") btor_op = "nor";
151 if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
152 log_assert(!btor_op.empty());
153
154 int width = GetSize(cell->getPort("\\Y"));
155 width = std::max(width, GetSize(cell->getPort("\\A")));
156 width = std::max(width, GetSize(cell->getPort("\\B")));
157
158 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
159 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
160
161 if (btor_op == "shift" && !b_signed)
162 btor_op = "srl";
163
164 if (cell->type.in("$shl", "$sshl", "$shr", "$sshr"))
165 b_signed = false;
166
167 if (cell->type == "$sshr" && !a_signed)
168 btor_op = "srl";
169
170 int sid = get_bv_sid(width);
171 int nid;
172
173 if (btor_op == "shift")
174 {
175 int nid_a = get_sig_nid(cell->getPort("\\A"), width, false);
176 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
177
178 int nid_r = next_nid++;
179 btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);
180
181 int nid_b_neg = next_nid++;
182 btorf("%d neg %d %d\n", nid_b_neg, sid, nid_b);
183
184 int nid_l = next_nid++;
185 btorf("%d sll %d %d %d\n", nid_l, sid, nid_a, nid_b_neg);
186
187 int sid_bit = get_bv_sid(1);
188 int nid_zero = get_sig_nid(Const(0, width));
189 int nid_b_ltz = next_nid++;
190 btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
191
192 nid = next_nid++;
193 btorf("%d ite %d %d %d %d\n", nid, sid, nid_b_ltz, nid_l, nid_r);
194 }
195 else
196 {
197 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
198 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
199
200 nid = next_nid++;
201 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
202 }
203
204 SigSpec sig = sigmap(cell->getPort("\\Y"));
205
206 if (GetSize(sig) < width) {
207 int sid = get_bv_sid(GetSize(sig));
208 int nid2 = next_nid++;
209 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
210 nid = nid2;
211 }
212
213 add_nid_sig(nid, sig);
214 goto okay;
215 }
216
217 if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
218 {
219 int sid = get_bv_sid(1);
220 int nid_a = get_sig_nid(cell->getPort("\\A"));
221 int nid_b = get_sig_nid(cell->getPort("\\B"));
222
223 int nid1 = next_nid++;
224 int nid2 = next_nid++;
225
226 if (cell->type == "$_ANDNOT_") {
227 btorf("%d not %d %d\n", nid1, sid, nid_b);
228 btorf("%d and %d %d %d\n", nid2, sid, nid_a, nid1);
229 }
230
231 if (cell->type == "$_ORNOT_") {
232 btorf("%d not %d %d\n", nid1, sid, nid_b);
233 btorf("%d or %d %d %d\n", nid2, sid, nid_a, nid1);
234 }
235
236 SigSpec sig = sigmap(cell->getPort("\\Y"));
237 add_nid_sig(nid2, sig);
238 goto okay;
239 }
240
241 if (cell->type.in("$_OAI3_", "$_AOI3_"))
242 {
243 int sid = get_bv_sid(1);
244 int nid_a = get_sig_nid(cell->getPort("\\A"));
245 int nid_b = get_sig_nid(cell->getPort("\\B"));
246 int nid_c = get_sig_nid(cell->getPort("\\C"));
247
248 int nid1 = next_nid++;
249 int nid2 = next_nid++;
250 int nid3 = next_nid++;
251
252 if (cell->type == "$_OAI3_") {
253 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
254 btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
255 btorf("%d not %d %d\n", nid3, sid, nid2);
256 }
257
258 if (cell->type == "$_AOI3_") {
259 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
260 btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
261 btorf("%d not %d %d\n", nid3, sid, nid2);
262 }
263
264 SigSpec sig = sigmap(cell->getPort("\\Y"));
265 add_nid_sig(nid3, sig);
266 goto okay;
267 }
268
269 if (cell->type.in("$_OAI4_", "$_AOI4_"))
270 {
271 int sid = get_bv_sid(1);
272 int nid_a = get_sig_nid(cell->getPort("\\A"));
273 int nid_b = get_sig_nid(cell->getPort("\\B"));
274 int nid_c = get_sig_nid(cell->getPort("\\C"));
275 int nid_d = get_sig_nid(cell->getPort("\\D"));
276
277 int nid1 = next_nid++;
278 int nid2 = next_nid++;
279 int nid3 = next_nid++;
280 int nid4 = next_nid++;
281
282 if (cell->type == "$_OAI4_") {
283 btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
284 btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
285 btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
286 btorf("%d not %d %d\n", nid4, sid, nid3);
287 }
288
289 if (cell->type == "$_AOI4_") {
290 btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
291 btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
292 btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
293 btorf("%d not %d %d\n", nid4, sid, nid3);
294 }
295
296 SigSpec sig = sigmap(cell->getPort("\\Y"));
297 add_nid_sig(nid4, sig);
298 goto okay;
299 }
300
301 if (cell->type.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt"))
302 {
303 string btor_op;
304 if (cell->type == "$lt") btor_op = "lt";
305 if (cell->type == "$le") btor_op = "lte";
306 if (cell->type.in("$eq", "$eqx")) btor_op = "eq";
307 if (cell->type.in("$ne", "$nex")) btor_op = "ne";
308 if (cell->type == "$ge") btor_op = "gte";
309 if (cell->type == "$gt") btor_op = "gt";
310 log_assert(!btor_op.empty());
311
312 int width = 1;
313 width = std::max(width, GetSize(cell->getPort("\\A")));
314 width = std::max(width, GetSize(cell->getPort("\\B")));
315
316 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
317 bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
318
319 int sid = get_bv_sid(1);
320 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
321 int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
322
323 int nid = next_nid++;
324 if (cell->type.in("$lt", "$le", "$ge", "$gt")) {
325 btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);
326 } else {
327 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
328 }
329
330 SigSpec sig = sigmap(cell->getPort("\\Y"));
331
332 if (GetSize(sig) > 1) {
333 int sid = get_bv_sid(GetSize(sig));
334 int nid2 = next_nid++;
335 btorf("%d uext %d %d %d\n", nid2, sid, nid, GetSize(sig) - 1);
336 nid = nid2;
337 }
338
339 add_nid_sig(nid, sig);
340 goto okay;
341 }
342
343 if (cell->type.in("$not", "$neg", "$_NOT_"))
344 {
345 string btor_op;
346 if (cell->type.in("$not", "$_NOT_")) btor_op = "not";
347 if (cell->type == "$neg") btor_op = "neg";
348 log_assert(!btor_op.empty());
349
350 int width = GetSize(cell->getPort("\\Y"));
351 width = std::max(width, GetSize(cell->getPort("\\A")));
352
353 bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
354
355 int sid = get_bv_sid(width);
356 int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
357
358 int nid = next_nid++;
359 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
360
361 SigSpec sig = sigmap(cell->getPort("\\Y"));
362
363 if (GetSize(sig) < width) {
364 int sid = get_bv_sid(GetSize(sig));
365 int nid2 = next_nid++;
366 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
367 nid = nid2;
368 }
369
370 add_nid_sig(nid, sig);
371 goto okay;
372 }
373
374 if (cell->type.in("$logic_and", "$logic_or", "$logic_not"))
375 {
376 string btor_op;
377 if (cell->type == "$logic_and") btor_op = "and";
378 if (cell->type == "$logic_or") btor_op = "or";
379 if (cell->type == "$logic_not") btor_op = "not";
380 log_assert(!btor_op.empty());
381
382 int sid = get_bv_sid(1);
383 int nid_a = get_sig_nid(cell->getPort("\\A"));
384 int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort("\\B")) : 0;
385
386 if (GetSize(cell->getPort("\\A")) > 1) {
387 int nid_red_a = next_nid++;
388 btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
389 nid_a = nid_red_a;
390 }
391
392 if (btor_op != "not" && GetSize(cell->getPort("\\B")) > 1) {
393 int nid_red_b = next_nid++;
394 btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
395 nid_b = nid_red_b;
396 }
397
398 int nid = next_nid++;
399 if (btor_op != "not")
400 btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
401 else
402 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
403
404 SigSpec sig = sigmap(cell->getPort("\\Y"));
405
406 if (GetSize(sig) > 1) {
407 int sid = get_bv_sid(GetSize(sig));
408 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
409 int nid2 = next_nid++;
410 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
411 nid = nid2;
412 }
413
414 add_nid_sig(nid, sig);
415 goto okay;
416 }
417
418 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor"))
419 {
420 string btor_op;
421 if (cell->type == "$reduce_and") btor_op = "redand";
422 if (cell->type.in("$reduce_or", "$reduce_bool")) btor_op = "redor";
423 if (cell->type.in("$reduce_xor", "$reduce_xnor")) btor_op = "redxor";
424 log_assert(!btor_op.empty());
425
426 int sid = get_bv_sid(1);
427 int nid_a = get_sig_nid(cell->getPort("\\A"));
428
429 int nid = next_nid++;
430 btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);
431
432 if (cell->type == "$reduce_xnor") {
433 int nid2 = next_nid++;
434 btorf("%d not %d %d %d\n", nid2, sid, nid);
435 nid = nid2;
436 }
437
438 SigSpec sig = sigmap(cell->getPort("\\Y"));
439
440 if (GetSize(sig) > 1) {
441 int sid = get_bv_sid(GetSize(sig));
442 int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
443 int nid2 = next_nid++;
444 btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
445 nid = nid2;
446 }
447
448 add_nid_sig(nid, sig);
449 goto okay;
450 }
451
452 if (cell->type.in("$mux", "$_MUX_"))
453 {
454 SigSpec sig_a = sigmap(cell->getPort("\\A"));
455 SigSpec sig_b = sigmap(cell->getPort("\\B"));
456 SigSpec sig_s = sigmap(cell->getPort("\\S"));
457 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
458
459 int nid_a = get_sig_nid(sig_a);
460 int nid_b = get_sig_nid(sig_b);
461 int nid_s = get_sig_nid(sig_s);
462
463 int sid = get_bv_sid(GetSize(sig_y));
464 int nid = next_nid++;
465 btorf("%d ite %d %d %d %d\n", nid, sid, nid_s, nid_b, nid_a);
466
467 add_nid_sig(nid, sig_y);
468 goto okay;
469 }
470
471 if (cell->type == "$pmux")
472 {
473 SigSpec sig_a = sigmap(cell->getPort("\\A"));
474 SigSpec sig_b = sigmap(cell->getPort("\\B"));
475 SigSpec sig_s = sigmap(cell->getPort("\\S"));
476 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
477
478 int width = GetSize(sig_a);
479 int sid = get_bv_sid(width);
480 int nid = get_sig_nid(sig_a);
481
482 for (int i = 0; i < GetSize(sig_s); i++) {
483 int nid_b = get_sig_nid(sig_b.extract(i*width, width));
484 int nid_s = get_sig_nid(sig_s.extract(i));
485 int nid2 = next_nid++;
486 btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
487 nid = nid2;
488 }
489
490 add_nid_sig(nid, sig_y);
491 goto okay;
492 }
493
494 if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N", "$_FF_"))
495 {
496 SigSpec sig_d = sigmap(cell->getPort("\\D"));
497 SigSpec sig_q = sigmap(cell->getPort("\\Q"));
498
499 IdString symbol;
500
501 if (sig_q.is_wire()) {
502 Wire *w = sig_q.as_wire();
503 if (w->port_id == 0) {
504 statewires.insert(w);
505 symbol = w->name;
506 }
507 }
508
509 Const initval;
510 for (int i = 0; i < GetSize(sig_q); i++)
511 if (initbits.count(sig_q[i]))
512 initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
513 else
514 initval.bits.push_back(State::Sx);
515
516 int nid_init_val = -1;
517
518 if (!initval.is_fully_undef())
519 nid_init_val = get_sig_nid(initval);
520
521 int sid = get_bv_sid(GetSize(sig_q));
522 int nid = next_nid++;
523
524 if (symbol.empty())
525 btorf("%d state %d\n", nid, sid);
526 else
527 btorf("%d state %d %s\n", nid, sid, log_id(symbol));
528
529 if (nid_init_val >= 0) {
530 int nid_init = next_nid++;
531 if (verbose)
532 btorf("; initval = %s\n", log_signal(initval));
533 btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
534 }
535
536 ff_todo.push_back(make_pair(nid, cell));
537 add_nid_sig(nid, sig_q);
538 goto okay;
539 }
540
541 if (cell->type.in("$anyconst", "$anyseq"))
542 {
543 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
544
545 int sid = get_bv_sid(GetSize(sig_y));
546 int nid = next_nid++;
547
548 btorf("%d state %d\n", nid, sid);
549
550 if (cell->type == "$anyconst") {
551 int nid2 = next_nid++;
552 btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
553 }
554
555 add_nid_sig(nid, sig_y);
556 goto okay;
557 }
558
559 if (cell->type == "$initstate")
560 {
561 SigSpec sig_y = sigmap(cell->getPort("\\Y"));
562
563 if (initstate_nid < 0)
564 {
565 int sid = get_bv_sid(1);
566 int one_nid = get_sig_nid(Const(1, 1));
567 int zero_nid = get_sig_nid(Const(0, 1));
568 initstate_nid = next_nid++;
569 btorf("%d state %d\n", initstate_nid, sid);
570 btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
571 btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
572 }
573
574 add_nid_sig(initstate_nid, sig_y);
575 goto okay;
576 }
577
578 if (cell->type == "$mem")
579 {
580 int abits = cell->getParam("\\ABITS").as_int();
581 int width = cell->getParam("\\WIDTH").as_int();
582 int rdports = cell->getParam("\\RD_PORTS").as_int();
583 int wrports = cell->getParam("\\WR_PORTS").as_int();
584
585 Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE");
586 Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE");
587
588 bool asyncwr = wr_clk_en.is_fully_zero();
589
590 if (!asyncwr && !wr_clk_en.is_fully_ones())
591 log_error("Memory %s.%s has mixed async/sync write ports.\n",
592 log_id(module), log_id(cell));
593
594 if (!rd_clk_en.is_fully_zero())
595 log_error("Memory %s.%s has sync read ports.\n",
596 log_id(module), log_id(cell));
597
598 SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR"));
599 SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA"));
600
601 SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
602 SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
603 SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
604
605 int data_sid = get_bv_sid(width);
606 int bool_sid = get_bv_sid(1);
607 int sid = get_mem_sid(abits, width);
608 int nid = next_nid++;
609 int nid_head = nid;
610
611 if (cell->name[0] == '$')
612 btorf("%d state %d\n", nid, sid);
613 else
614 btorf("%d state %d %s\n", nid, sid, log_id(cell));
615
616 if (asyncwr)
617 {
618 for (int port = 0; port < wrports; port++)
619 {
620 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
621 SigSpec wd = sig_wr_data.extract(port*width, width);
622 SigSpec we = sig_wr_en.extract(port*width, width);
623
624 int wa_nid = get_sig_nid(wa);
625 int wd_nid = get_sig_nid(wd);
626 int we_nid = get_sig_nid(we);
627
628 int nid2 = next_nid++;
629 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
630
631 int nid3 = next_nid++;
632 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
633
634 int nid4 = next_nid++;
635 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
636
637 int nid5 = next_nid++;
638 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
639
640 int nid6 = next_nid++;
641 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
642
643 int nid7 = next_nid++;
644 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
645
646 int nid8 = next_nid++;
647 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
648
649 int nid9 = next_nid++;
650 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
651
652 nid_head = nid9;
653 }
654 }
655
656 for (int port = 0; port < rdports; port++)
657 {
658 SigSpec ra = sig_rd_addr.extract(port*abits, abits);
659 SigSpec rd = sig_rd_data.extract(port*width, width);
660
661 int ra_nid = get_sig_nid(ra);
662 int rd_nid = next_nid++;
663
664 btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);
665
666 add_nid_sig(rd_nid, rd);
667 }
668
669 if (!asyncwr)
670 {
671 ff_todo.push_back(make_pair(nid, cell));
672 }
673 else
674 {
675 int nid2 = next_nid++;
676 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
677 }
678
679 goto okay;
680 }
681
682 log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
683
684 okay:
685 btorf_pop(log_id(cell));
686 cell_recursion_guard.erase(cell);
687 }
688
689 int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false)
690 {
691 int nid = -1;
692 sigmap.apply(sig);
693
694 for (auto bit : sig)
695 if (bit == State::Sx)
696 goto has_undef_bits;
697
698 if (0)
699 {
700 has_undef_bits:
701 SigSpec sig_mask_undef, sig_noundef;
702 int first_undef = -1;
703
704 for (int i = 0; i < GetSize(sig); i++)
705 if (sig[i] == State::Sx) {
706 if (first_undef < 0)
707 first_undef = i;
708 sig_mask_undef.append(State::S1);
709 sig_noundef.append(State::S0);
710 } else {
711 sig_mask_undef.append(State::S0);
712 sig_noundef.append(sig[i]);
713 }
714
715 if (to_width < 0 || first_undef < to_width)
716 {
717 int sid = get_bv_sid(GetSize(sig));
718
719 int nid_input = next_nid++;
720 btorf("%d input %d\n", nid_input, sid);
721
722 int nid_masked_input;
723 if (sig_mask_undef.is_fully_ones()) {
724 nid_masked_input = nid_input;
725 } else {
726 int nid_mask_undef = get_sig_nid(sig_mask_undef);
727 nid_masked_input = next_nid++;
728 btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
729 }
730
731 if (sig_noundef.is_fully_zero()) {
732 nid = nid_masked_input;
733 } else {
734 int nid_noundef = get_sig_nid(sig_noundef);
735 nid = next_nid++;
736 btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
737 }
738
739 goto extend_or_trim;
740 }
741
742 sig = sig_noundef;
743 }
744
745 if (sig_nid.count(sig) == 0)
746 {
747 // <nid>, <bitidx>
748 vector<pair<int, int>> nidbits;
749
750 // collect all bits
751 for (int i = 0; i < GetSize(sig); i++)
752 {
753 SigBit bit = sig[i];
754
755 if (bit_nid.count(bit) == 0)
756 {
757 if (bit.wire == nullptr)
758 {
759 Const c(bit.data);
760
761 while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
762 c.bits.push_back(sig[i+GetSize(c)].data);
763
764 if (consts.count(c) == 0) {
765 int sid = get_bv_sid(GetSize(c));
766 int nid = next_nid++;
767 btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
768 consts[c] = nid;
769 nid_width[nid] = GetSize(c);
770 }
771
772 int nid = consts.at(c);
773
774 for (int j = 0; j < GetSize(c); j++)
775 nidbits.push_back(make_pair(nid, j));
776
777 i += GetSize(c)-1;
778 continue;
779 }
780 else
781 {
782 if (bit_cell.count(bit) == 0)
783 log_error("No driver for signal bit %s.\n", log_signal(bit));
784 export_cell(bit_cell.at(bit));
785 log_assert(bit_nid.count(bit));
786 }
787 }
788
789 nidbits.push_back(bit_nid.at(bit));
790 }
791
792 int width = 0;
793 int nid = -1;
794
795 // group bits and emit slice-concat chain
796 for (int i = 0; i < GetSize(nidbits); i++)
797 {
798 int nid2 = nidbits[i].first;
799 int lower = nidbits[i].second;
800 int upper = lower;
801
802 while (i+1 < GetSize(nidbits) && nidbits[i+1].first == nidbits[i].first &&
803 nidbits[i+1].second == nidbits[i].second+1)
804 upper++, i++;
805
806 int nid3 = nid2;
807
808 if (lower != 0 || upper+1 != nid_width.at(nid2)) {
809 int sid = get_bv_sid(upper-lower+1);
810 nid3 = next_nid++;
811 btorf("%d slice %d %d %d %d\n", nid3, sid, nid2, upper, lower);
812 }
813
814 int nid4 = nid3;
815
816 if (nid >= 0) {
817 int sid = get_bv_sid(width+upper-lower+1);
818 nid4 = next_nid++;
819 btorf("%d concat %d %d %d\n", nid4, sid, nid3, nid);
820 }
821
822 width += upper-lower+1;
823 nid = nid4;
824 }
825
826 sig_nid[sig] = nid;
827 nid_width[nid] = width;
828 }
829
830 nid = sig_nid.at(sig);
831
832 extend_or_trim:
833 if (to_width >= 0 && to_width != GetSize(sig))
834 {
835 if (to_width < GetSize(sig))
836 {
837 int sid = get_bv_sid(to_width);
838 int nid2 = next_nid++;
839 btorf("%d slice %d %d %d 0\n", nid2, sid, nid, to_width-1);
840 nid = nid2;
841 }
842 else
843 {
844 int sid = get_bv_sid(to_width);
845 int nid2 = next_nid++;
846 btorf("%d %s %d %d %d\n", nid2, is_signed ? "sext" : "uext",
847 sid, nid, to_width - GetSize(sig));
848 nid = nid2;
849 }
850 }
851
852 return nid;
853 }
854
855 BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad) :
856 f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad)
857 {
858 btorf_push("inputs");
859
860 for (auto wire : module->wires())
861 {
862 if (wire->attributes.count("\\init")) {
863 Const attrval = wire->attributes.at("\\init");
864 for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
865 if (attrval[i] == State::S0 || attrval[i] == State::S1)
866 initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
867 }
868
869 if (!wire->port_id || !wire->port_input)
870 continue;
871
872 SigSpec sig = sigmap(wire);
873 int sid = get_bv_sid(GetSize(sig));
874 int nid = next_nid++;
875
876 btorf("%d input %d %s\n", nid, sid, log_id(wire));
877 add_nid_sig(nid, sig);
878 }
879
880 btorf_pop("inputs");
881
882 for (auto cell : module->cells())
883 for (auto &conn : cell->connections())
884 {
885 if (!cell->output(conn.first))
886 continue;
887
888 for (auto bit : sigmap(conn.second))
889 bit_cell[bit] = cell;
890 }
891
892 for (auto wire : module->wires())
893 {
894 if (!wire->port_id || !wire->port_output)
895 continue;
896
897 btorf_push(stringf("output %s", log_id(wire)));
898
899 int sid = get_bv_sid(GetSize(wire));
900 int nid = get_sig_nid(wire);
901 btorf("%d output %d %d %s\n", next_nid++, sid, nid, log_id(wire));
902
903 btorf_pop(stringf("output %s", log_id(wire)));
904 }
905
906 for (auto cell : module->cells())
907 {
908 if (cell->type == "$assume")
909 {
910 btorf_push(log_id(cell));
911
912 int sid = get_bv_sid(1);
913 int nid_a = get_sig_nid(cell->getPort("\\A"));
914 int nid_en = get_sig_nid(cell->getPort("\\EN"));
915 int nid_not_en = next_nid++;
916 int nid_a_or_not_en = next_nid++;
917 int nid = next_nid++;
918
919 btorf("%d not %d %d\n", nid_not_en, sid, nid_en);
920 btorf("%d or %d %d %d\n", nid_a_or_not_en, sid, nid_a, nid_not_en);
921 btorf("%d constraint %d\n", nid, nid_a_or_not_en);
922
923 btorf_pop(log_id(cell));
924 }
925
926 if (cell->type == "$assert")
927 {
928 btorf_push(log_id(cell));
929
930 int sid = get_bv_sid(1);
931 int nid_a = get_sig_nid(cell->getPort("\\A"));
932 int nid_en = get_sig_nid(cell->getPort("\\EN"));
933 int nid_not_a = next_nid++;
934 int nid_en_and_not_a = next_nid++;
935
936 btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
937 btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);
938
939 if (single_bad) {
940 bad_properties.push_back(nid_en_and_not_a);
941 } else {
942 int nid = next_nid++;
943 btorf("%d bad %d\n", nid, nid_en_and_not_a);
944 }
945
946 btorf_pop(log_id(cell));
947 }
948 }
949
950 for (auto wire : module->wires())
951 {
952 if (wire->port_id || wire->name[0] == '$')
953 continue;
954
955 btorf_push(stringf("wire %s", log_id(wire)));
956
957 int sid = get_bv_sid(GetSize(wire));
958 int nid = get_sig_nid(sigmap(wire));
959
960 if (statewires.count(wire))
961 continue;
962
963 int this_nid = next_nid++;
964 btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, log_id(wire));
965
966 btorf_pop(stringf("wire %s", log_id(wire)));
967 continue;
968 }
969
970 while (!ff_todo.empty())
971 {
972 vector<pair<int, Cell*>> todo;
973 todo.swap(ff_todo);
974
975 for (auto &it : todo)
976 {
977 int nid = it.first;
978 Cell *cell = it.second;
979
980 btorf_push(stringf("next %s", log_id(cell)));
981
982 if (cell->type == "$mem")
983 {
984 int abits = cell->getParam("\\ABITS").as_int();
985 int width = cell->getParam("\\WIDTH").as_int();
986 int wrports = cell->getParam("\\WR_PORTS").as_int();
987
988 SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
989 SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
990 SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
991
992 int data_sid = get_bv_sid(width);
993 int bool_sid = get_bv_sid(1);
994 int sid = get_mem_sid(abits, width);
995 int nid_head = nid;
996
997 for (int port = 0; port < wrports; port++)
998 {
999 SigSpec wa = sig_wr_addr.extract(port*abits, abits);
1000 SigSpec wd = sig_wr_data.extract(port*width, width);
1001 SigSpec we = sig_wr_en.extract(port*width, width);
1002
1003 int wa_nid = get_sig_nid(wa);
1004 int wd_nid = get_sig_nid(wd);
1005 int we_nid = get_sig_nid(we);
1006
1007 int nid2 = next_nid++;
1008 btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
1009
1010 int nid3 = next_nid++;
1011 btorf("%d not %d %d\n", nid3, data_sid, we_nid);
1012
1013 int nid4 = next_nid++;
1014 btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
1015
1016 int nid5 = next_nid++;
1017 btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
1018
1019 int nid6 = next_nid++;
1020 btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
1021
1022 int nid7 = next_nid++;
1023 btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
1024
1025 int nid8 = next_nid++;
1026 btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);
1027
1028 int nid9 = next_nid++;
1029 btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);
1030
1031 nid_head = nid9;
1032 }
1033
1034 int nid2 = next_nid++;
1035 btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
1036 }
1037 else
1038 {
1039 SigSpec sig = sigmap(cell->getPort("\\D"));
1040 int nid_q = get_sig_nid(sig);
1041 int sid = get_bv_sid(GetSize(sig));
1042 btorf("%d next %d %d %d\n", next_nid++, sid, nid, nid_q);
1043 }
1044
1045 btorf_pop(stringf("next %s", log_id(cell)));
1046 }
1047 }
1048
1049 while (!bad_properties.empty())
1050 {
1051 vector<int> todo;
1052 bad_properties.swap(todo);
1053
1054 int sid = get_bv_sid(1);
1055 int cursor = 0;
1056
1057 while (cursor+1 < GetSize(todo))
1058 {
1059 int nid_a = todo[cursor++];
1060 int nid_b = todo[cursor++];
1061 int nid = next_nid++;
1062
1063 bad_properties.push_back(nid);
1064 btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
1065 }
1066
1067 if (!bad_properties.empty()) {
1068 if (cursor < GetSize(todo))
1069 bad_properties.push_back(todo[cursor++]);
1070 log_assert(cursor == GetSize(todo));
1071 } else {
1072 int nid = next_nid++;
1073 log_assert(cursor == 0);
1074 log_assert(GetSize(todo) == 1);
1075 btorf("%d bad %d\n", nid, todo[cursor]);
1076 }
1077 }
1078 }
1079 };
1080
1081 struct BtorBackend : public Backend {
1082 BtorBackend() : Backend("btor", "write design to BTOR file") { }
1083 void help() YS_OVERRIDE
1084 {
1085 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1086 log("\n");
1087 log(" write_btor [options] [filename]\n");
1088 log("\n");
1089 log("Write a BTOR description of the current design.\n");
1090 log("\n");
1091 log(" -v\n");
1092 log(" Add comments and indentation to BTOR output file\n");
1093 log("\n");
1094 log(" -s\n");
1095 log(" Output only a single bad property for all asserts\n");
1096 log("\n");
1097 }
1098 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1099 {
1100 bool verbose = false, single_bad = false;
1101
1102 log_header(design, "Executing BTOR backend.\n");
1103
1104 size_t argidx;
1105 for (argidx = 1; argidx < args.size(); argidx++)
1106 {
1107 if (args[argidx] == "-v") {
1108 verbose = true;
1109 continue;
1110 }
1111 if (args[argidx] == "-s") {
1112 single_bad = true;
1113 continue;
1114 }
1115 break;
1116 }
1117 extra_args(f, filename, args, argidx);
1118
1119 RTLIL::Module *topmod = design->top_module();
1120
1121 if (topmod == nullptr)
1122 log_cmd_error("No top module found.\n");
1123
1124 *f << stringf("; BTOR description generated by %s for module %s.\n",
1125 yosys_version_str, log_id(topmod));
1126
1127 BtorWorker(*f, topmod, verbose, single_bad);
1128
1129 *f << stringf("; end of yosys output\n");
1130 }
1131 } BtorBackend;
1132
1133 PRIVATE_NAMESPACE_END